Added LMI initialization code(TODO).
This commit is contained in:
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ca588dca3c
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GPG Key ID:
885EC2B5A8A6F8A7
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@ -9,6 +9,7 @@ set(TARGET_LDSCRIPT "${CMAKE_SOURCE_DIR}/stx7105.ld")
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set(TARGET_SOURCES
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"src/main.c"
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"startup_stx7105.S"
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"startup_stx7105_init_ram.S"
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)
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set(TARGET_INCLUDES
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@ -0,0 +1,7 @@
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Copyright 2022 imi415
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Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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@ -0,0 +1,3 @@
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This project uses some initialization code from STLinux U-Boot,
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the license header is kept in the corresponding files.
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Check these files for license.
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42
src/main.c
42
src/main.c
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@ -1,5 +1,45 @@
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#include <stdint.h>
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#define ST_GPIO0_BASE_ADDR (0xFD020000)
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#define ST_GPIO0_OFFSET_POUT 0x00U
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#define ST_GPIO0_OFFSET_SET_POUT 0x04U
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#define ST_GPIO0_OFFSET_CLR_POUT 0x08U
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#define ST_GPIO0_OFFSET_PC0 0x20U
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#define ST_GPIO0_OFFSET_SET_PC0 0x24U
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#define ST_GPIO0_OFFSET_CLR_PC0 0x28U
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#define ST_GPIO0_OFFSET_PC1 0x30U
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#define ST_GPIO0_OFFSET_SET_PC1 0x34U
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#define ST_GPIO0_OFFSET_CLR_PC1 0x38U
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#define ST_GPIO0_OFFSET_PC2 0x40U
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#define ST_GPIO0_OFFSET_SET_PC2 0x44U
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#define ST_GPIO0_OFFSET_CLR_PC2 0x48U
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#define LED_RED_PIN 4U
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#define LED_BLUE_PIN 5U
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static void init_led(uint8_t pin) {
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*(uint32_t *)(ST_GPIO0_BASE_ADDR + ST_GPIO0_OFFSET_SET_PC0) = (1 << pin);
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*(uint32_t *)(ST_GPIO0_BASE_ADDR + ST_GPIO0_OFFSET_SET_PC1) = (1 << pin);
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*(uint32_t *)(ST_GPIO0_BASE_ADDR + ST_GPIO0_OFFSET_CLR_PC2) = (1 << pin);
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}
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static void set_led(uint8_t pin, uint8_t val) {
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if (val) {
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*(uint32_t *)(ST_GPIO0_BASE_ADDR + ST_GPIO0_OFFSET_SET_POUT) = (1 << pin);
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} else {
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*(uint32_t *)(ST_GPIO0_BASE_ADDR + ST_GPIO0_OFFSET_CLR_POUT) = (1 << pin);
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}
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}
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int main(void) {
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for(;;) {
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init_led(LED_RED_PIN);
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init_led(LED_BLUE_PIN);
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set_led(LED_RED_PIN, 1);
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set_led(LED_BLUE_PIN, 0);
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for (;;) {
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/* Dead loop */
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}
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}
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@ -1,11 +1,52 @@
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/* Startup code, we can't use non-PIC code nor RAM before the LMI is initialized:
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* The CPU starts with physical address 0x0, however the linker is linked to virtual
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* addresses and LMI.
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* Non-PIC code means any indirect addressing other than relative to PC.
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*/
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.section .text.init, "ax"
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.global _start
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.global start
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_start:
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start:
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nop
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nop
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/* Initialize Blue LED P0_4 */
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mov #16, r0
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mov.l gpio_clr_k, r1
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mov.l r0, @r1
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mov.l gpio_clr_pc0_k, r1
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mov.l r0, @r1
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mov.l gpio_set_pc1_k, r1
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mov.l r0, @r1
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mov.l gpio_clr_pc2_k, r1
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mov.l r0, @r1
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/* Initialize Red LED P0_5 */
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mov #32, r0
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mov.l gpio_clr_k, r1
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mov.l r0, @r1
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mov.l gpio_clr_pc0_k, r1
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mov.l r0, @r1
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mov.l gpio_set_pc1_k, r1
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mov.l r0, @r1
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mov.l gpio_clr_pc2_k, r1
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mov.l r0, @r1
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mov.l sr_k, r0
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ldc r0, sr
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mov.l stack_k, sp /* Setup R15(SP) */
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/* Turn on Red LED */
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mov #32, r0
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mov.l gpio_set_k, r1
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mov.l r0, @r1
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/* TODO: Initialize PMB, setup caches !! */
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/* TODO: Switch to 32-bit mode */
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/* TODO: Initialize LMI */
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mova init_ram_k, r0 /* The init_ram may be placed too far away, load the pointer to r0 */
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mov.l @r0, r1 /* Load actual function address to r1 */
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add r1, r0 /* address in r1 is relative to init_ram_k */
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jsr @r0 /* Jump to the init_ram function */
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nop
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copy_data:
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mov.l sidata_k, r0
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@ -19,6 +60,11 @@ loop_copy_data:
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cmp/ge r1, r2
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bt loop_copy_data
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/* Turn on Blue LED */
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mov #16, r0
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mov.l gpio_set_k, r1
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mov.l r0, @r1
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zero_bss:
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mov.l edata_k, r0
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mov.l end_k, r1
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@ -36,8 +82,7 @@ setup_fpu:
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mov #0, r4
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lds r3, fpscr
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mov.l main_k,r0
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mov.l main_k, r0
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jsr @r0
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or r0, r0
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@ -47,8 +92,20 @@ setup_fpu:
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or r0, r0
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/* It would be more efficient by using indirect addressing instead of 8 instructions... */
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.align 2
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/* Align to 4 byte boundary since we are loading the whole word */
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.align 4
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sr_k:
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.long 0x400000F0
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gpio_set_k:
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.long 0xFD020004
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gpio_clr_k:
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.long 0xFD020008
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gpio_clr_pc0_k:
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.long 0xFD020028
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gpio_set_pc1_k:
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.long 0xFD020034
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gpio_clr_pc2_k:
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.long 0xFD020048
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set_fpscr_k:
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.long ___set_fpscr
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stack_k:
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@ -61,6 +118,8 @@ edata_k:
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.long _edata
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end_k:
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.long _end
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init_ram_k:
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.long init_ram
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main_k:
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.long _main /* Same address as main */
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exit_k:
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@ -0,0 +1,281 @@
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/*
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* (C) Copyright 2004-2009 STMicroelectronics.
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*
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* Andy Sturges <andy.sturges@st.com>
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* Start Menefy <stuart.menefy@st.com>
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* Sean McGoogan <Sean.McGoogan@st.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* These macros are compatible to STLinux U-boot. */
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#define POKE32(addr, value) .long 0x00000004, addr, value
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#define UPDATE32(addr, mask, value) .long 0x00000006, addr, mask, value
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#define WHILE_NE32(addr, mask, value) .long 0x00000007, addr, mask, value
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#define DELAY(val) /* ST did nothing */
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#define END_MARKER .long 0x00000000, 0x00000000, 0x00000000
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/* Poke operation list */
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.section .rodata.init, "a"
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__memory_setup_table:
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#include "vendor/pdk7105.romgen"
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/*
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* Note that we also manually need to move the LMI base addresses to
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* their 32-bit SE mode locations as defined in the datasheet and change the
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* 'upper bound addresses' (in row attribute registers) for the LMIs.
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*/
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/* STX7105_SYSCONF_SYS_CFG38 */
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UPDATE32(0xfe001000 + 0x0198, 0xFFFFFF00, 0x00000040)
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/*
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* Change LMI upper bound addresses
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* Upper LMI addr=0x40000000 + 512MiB=0x60000000
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*/
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/* ST40_LMI_SDRA0_0 -> ST40_LMI_REGS_BASE + 0x000030 */
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UPDATE32(0xFE901000 + 0x30, 0x001FFFFF, 0x60000000)
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/* ST40_LMI_SDRA1_0 -> ST40_LMI_REGS_BASE + 0x000038 */
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UPDATE32(0xFE901000 + 0x38, 0x001FFFFF, 0x60000000)
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END_MARKER
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__memory_setup_table_end:
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.long 0x00000000
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/*
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* NOTE: ALL THIS CODE MUST BE PIC !!!!
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*
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* This code expects to be run with the caches enabled.
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*/
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.section .text.init, "ax"
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.global init_ram
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init_ram:
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/* Stash the pr somewhere safe */
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sts pr, r14
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/*
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* We need to get the poke loop & associated data
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* into caches. The poke loop is structured so that it is
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* all pulled into cache on it 1st iteration.
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* To get the poke table into D-cache, we simply read it all.
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*/
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mova poke_loop_address, r0 /* R6: &poke_loop() */
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mov.l @r0, r6
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add r0, r6
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mov.l p2_to_p1_mask, r3 /* R3: P2 -> P1 mapping */
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and r3, r6 /* convert to P1 addresses */
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mov.l data_start_address, r1 /* R1 = start address */
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add r0, r1
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mov.l data_end_address, r2 /* R2 = end address */
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add r0, r2
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and r3, r1 /* convert to a P1 addresses */
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and r3, r2
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mov r1, r5 /* R5 = scratch data ptr */
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1:
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mov.l @r5+, r4 /* Load poke table in D$ */
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cmp/eq r5, r2
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bf 1b
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/*
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* Its now safe to call the poke loop with real data, since it
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* and its associated data table are in onchip caches. Setting
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* up the memory interfaces may cause the EMI (where this FLASH
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* image resides) to briefly hang - but the CPU will be safely
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* executing from cache should this happen.
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*/
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do_pokes:
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jsr @r6 /* R6 still points poke_loop() */
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nop
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/* Restore the PR */
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lds r14, pr
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rts
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nop
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.balign 4
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poke_loop_address: .long poke_loop - poke_loop_address
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data_start_address: .long __memory_setup_table - poke_loop_address
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data_end_address: .long __memory_setup_table_end - poke_loop_address
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p2_to_p1_mask: .long ~0x20000000
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/*
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* This is derived from STMicroelectronics gnu toolchain example:
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* sh-superh-elf/examples/os21/romdynamic/bootstrap.S
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* but it is not identical, because concurrently U-Boot added the
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* IF_DEVID, IF_NOT_DEVID, ELSE and ENDIF commands, while the toolset
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* added IF. This merged version supports both.
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*/
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/*
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* The poke table is a series of long words, in the format
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*
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* opcode, address, operand, ...
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*
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* An opcode of 0 marks the table end
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*/
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/*
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* Routine to setup peripheral registers.
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* It is executed from within the I-cache,
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* with all its data in the D-cache
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*/
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poke_loop:
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mov.l @r1+, r0 /* opcode */
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mov.l @r1+, r2 /* address */
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mov.l @r1+, r3 /* value */
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cmp/eq #0, r0 /* End marker ? */
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bf 1f
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rts /* Return point */
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nop
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1:
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cmp/eq #4, r0 /* 4 byte write... */
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bf 1f
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mov.l r3, @r2
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1:
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cmp/eq #2, r0 /* 2 byte write... */
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bf 1f
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mov.w r3, @r2
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1:
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cmp/eq #1, r0 /* 1 byte write... */
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bf 1f
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mov.b r3, @r2
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1:
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cmp/eq #5, r0 /* 4 byte OR... */
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bf 1f
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mov.l @r2,r4
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or r3,r4
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mov.l r4,@r2
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1:
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cmp/eq #6, r0 /* 4 byte UPDATE... */
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bf 1f
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mov.l @r2,r4
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and r3,r4
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mov.l @r1+,r3
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or r3,r4
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mov.l r4,@r2
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1:
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cmp/eq #8, r0 /* 4 byte write UPDATE... */
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bf 1f
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mov.l @r3,r4
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mov.l @r1+,r3
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and r3,r4
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mov.l @r1+,r3
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shld r3,r4
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mov.l @r1+,r3
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or r3,r4
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mov.l r4,@r2
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1:
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cmp/eq #7, r0 /* WHILE != ... */
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bf 1f
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mov.l @r1+,r5
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2:
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mov.l @r2,r4
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and r3,r4
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cmp/eq r4,r5
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bf 2b
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1:
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cmp/eq #9, r0 /* IF_DEVID */
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bf 1f /* r2 skip offset, r3 condition, r7 holds out cut value */
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cmp/eq r3, r7
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bt poke_loop /* go ahead with these pokes */
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add r2, r1
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bra poke_loop
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nop
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1:
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cmp/eq #10, r0 /* IF_NOT_DEVID */
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bf 1f /* r2 skip offset, r3 condition, r7 holds out cut value */
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cmp/eq r3, r7
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bf poke_loop /* go ahead with these pokes */
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add r2, r1
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bra poke_loop
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nop
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1: cmp/eq #11, r0 /* ELSE */
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bf 1f /* r2 skip offset, r3 condition, r7 holds out cut value */
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add r2, r1
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bra poke_loop
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nop
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1:
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cmp/eq #12,r0 /* IF == ... next op */
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bf delay
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mov.l @r1+,r5
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mov.l @r2,r4
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and r3,r4
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cmp/eq r4,r5
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bt poke_loop /* Compare succeeded - perform next op */
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2: /* Skip the next operation (read past it) */
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mov.l @r1+,r0 /* R0 = opcode */
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mov.l @r1+,r2 /* skip address */
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mov.l @r1+,r2 /* skip value */
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/* How many further reads do we need to skip? */
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cmp/eq #12,r0 /* If it's another IF, skip 1 and go back to start of skip loop */
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bf 3f
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mov.l @r1+,r2
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bra 2b
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nop
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3:
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mov #5,r2
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cmp/gt r2,r0
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bf 5f /* 0 further reads */
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cmp/eq #8,r0 /* Is it number 8 (3 reads, otherwise 1 read) */
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bf 4f
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mov.l @r1+,r2 /* Skip 1 read */
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mov.l @r1+,r2 /* Skip 1 read */
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4:
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mov.l @r1+,r2 /* Skip 1 read and continue */
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5:
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bra poke_loop
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nop
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delay:
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mov #1,r0 /* small delay after EACH opcode */
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swap.w r0, r0 /* 0x10000 iterations (~65k) */
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2:
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add #-1,r0
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cmp/eq #0, r0
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bf 2b
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bt poke_loop
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@ -2,13 +2,13 @@
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HEAP_SIZE = 0x10000;
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STACK_SIZE = 0x10000;
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ENTRY(_start)
|
||||
ENTRY(start)
|
||||
|
||||
/* For bare-metal applications, we use 29-bit addressing mode. */
|
||||
/* We don't use 29-bit mode since PMB and LMI initialization has to be done anyway. */
|
||||
|
||||
MEMORY {
|
||||
EMI (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 /* EMI physical address: 0x0000_0000 */
|
||||
LMI (rwx) : ORIGIN = 0x0C000000, LENGTH = 0x10000000 /* LMI physical address: 0x0C00_0000 */
|
||||
EMI (rx) : ORIGIN = 0xA0000000, LENGTH = 0x00100000 /* EMI virtual address: 0xA000_0000 */
|
||||
LMI (rwx) : ORIGIN = 0x80000000, LENGTH = 0x10000000 /* LMI virtual address: 0x8000_0000 */
|
||||
}
|
||||
|
||||
SECTIONS {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,549 @@
|
|||
|
||||
/*
|
||||
sdk7105 connect start - parameters {'no_devid_validate': '1', 'no_convertor_abort': '1', 'no_devid_abort': '1'}
|
||||
Initialization TCK frequency set to 1562500 Hz
|
||||
Device id 0x1d43e041
|
||||
tapmux connect(): boot mode single core setup
|
||||
tapmux setup to bypass to core st40, channel 1
|
||||
sdk7105 initialization start ...
|
||||
sdk7105_setup - parameters {'tapmux_bypass_init': u'st40', 'no_devid_validate': '1', 'no_convertor_abort': '1', 'reset_low_period': 360000, 'no_devid_abort': '1'}
|
||||
Chip infos
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
stx7105_sysconf_regs.SYSCONF_DEVICEID0
|
||||
PEEK(0xfe001000) (used target peek value 0x1d43e041)
|
||||
Device ID = 0x1D43E041 ==> STi7105 cut 2
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
stx7105_sysconf_regs.SYSCONF_STA1
|
||||
PEEK(0xfe00100c) (used target peek value 0x00001015)
|
||||
Mode pins = 0x00001015 ==> ClockgenA ref : SYSCLKIN/OSC
|
||||
Boot mode ... : ST40 first
|
||||
Boot port size: 16-bits
|
||||
Boot device . : NOR flash
|
||||
*/
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG40*/
|
||||
POKE32(0xfe0011a0, 0x00000005)
|
||||
POKE32(0xfe0011a0, 0x00000005)
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG04*/
|
||||
POKE32(0xfe001110, 0x000001a6)
|
||||
|
||||
/* Magic sequence to configure the ClockGenA switch control to reset values*/
|
||||
/* These do not appear to be correctly reset on WDT reset so do it here */
|
||||
/* CLOCKGEN A CKGA_CLKOPSRC_SWITCH_CFG reset=0 */
|
||||
POKE32(0xfe213014, 0x00000000)
|
||||
/* CLOCKGEN A CKGA_CLKOPSRC_SWITCH_CFG2 reset=0 */
|
||||
POKE32(0xfe213024, 0x00000000)
|
||||
|
||||
/*stx7105_clockgena_regs.CKGA_PLL0_ENABLE_FB*/
|
||||
WHILE_NE32(0xfe21301c, 0xffffffff, 0x00000000)
|
||||
|
||||
/*stx7105_clockgena_regs.CKGA_PLL1_ENABLE_FB*/
|
||||
WHILE_NE32(0xfe213020, 0xffffffff, 0x00000000)
|
||||
|
||||
/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/
|
||||
POKE32(0xfe213000, 0x80101e02)
|
||||
|
||||
/*stx7105_clockgena_regs.CKGA_POWER_CFG*/
|
||||
POKE32(0xfe213010, 0x00000001)
|
||||
|
||||
|
||||
/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/
|
||||
POKE32(0xfe213000, 0x00180f01)
|
||||
|
||||
/*stx7105_clockgena_regs.CKGA_POWER_CFG*/
|
||||
POKE32(0xfe213010, 0x00000000)
|
||||
|
||||
|
||||
/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/
|
||||
WHILE_NE32(0xfe213000, 0x80000000, 0x80000000)
|
||||
|
||||
|
||||
/*stx7105_clockgena_regs.CKGA_PLL0_CFG*/
|
||||
POKE32(0xfe213000, 0x80000f01)
|
||||
|
||||
|
||||
/*stx7105_clockgena_regs.CKGA_PLL1_CFG*/
|
||||
POKE32(0xfe213004, 0x80102803)
|
||||
|
||||
|
||||
POKE32(0xfe213b00, 0x00000001) /*stx7105_clockgena_regs.CKGA_PLL1_DIV0_CFG*/
|
||||
POKE32(0xfe213b04, 0x00000001) /*stx7105_clockgena_regs.CKGA_PLL1_DIV1_CFG*/
|
||||
POKE32(0xfe213b08, 0x00000001) /*stx7105_clockgena_regs.CKGA_PLL1_DIV2_CFG*/
|
||||
POKE32(0xfe213b0c, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV3_CFG*/
|
||||
POKE32(0xfe213a10, 0x00010100) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV4_CFG*/
|
||||
POKE32(0xfe213b14, 0x00000307) /*stx7105_clockgena_regs.CKGA_PLL1_DIV5_CFG*/
|
||||
POKE32(0xfe213a18, 0x00010100) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV6_CFG*/
|
||||
POKE32(0xfe213a1c, 0x00010100) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV7_CFG*/
|
||||
POKE32(0xfe213b20, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV8_CFG*/
|
||||
POKE32(0xfe213b24, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV9_CFG*/
|
||||
POKE32(0xfe213b28, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV10_CFG*/
|
||||
POKE32(0xfe213b2c, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV11_CFG*/
|
||||
POKE32(0xfe213b30, 0x00000102) /*stx7105_clockgena_regs.CKGA_PLL1_DIV12_CFG*/
|
||||
POKE32(0xfe213a34, 0x00000811) /*stx7105_clockgena_regs.CKGA_PLL0LS_DIV13_CFG*/
|
||||
POKE32(0xfe213b38, 0x0000050b) /*stx7105_clockgena_regs.CKGA_PLL1_DIV14_CFG*/
|
||||
POKE32(0xfe213b3c, 0x00000307) /*stx7105_clockgena_regs.CKGA_PLL1_DIV15_CFG*/
|
||||
POKE32(0xfe213b40, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV16_CFG*/
|
||||
POKE32(0xfe213b44, 0x00000103) /*stx7105_clockgena_regs.CKGA_PLL1_DIV17_CFG*/
|
||||
|
||||
|
||||
POKE32(0xfe213010, 0x00000002) /*stx7105_clockgena_regs.CKGA_POWER_CFG*/
|
||||
POKE32(0xfe213004, 0x00182803) /*stx7105_clockgena_regs.CKGA_PLL1_CFG*/
|
||||
POKE32(0xfe213010, 0x00000000) /*stx7105_clockgena_regs.CKGA_POWER_CFG*/
|
||||
WHILE_NE32(0xfe213004, 0x80000000, 0x80000000) /*stx7105_clockgena_regs.CKGA_PLL1_CFG*/
|
||||
POKE32(0xfe213004, 0x80002803) /*stx7105_clockgena_regs.CKGA_PLL1_CFG*/
|
||||
POKE32(0xfe213014, 0xa6aa59aa) /*stx7105_clockgena_regs.CKGA_CLKOPSRC_SWITCH_CFG*/
|
||||
POKE32(0xfe213024, 0x0000000a) /*stx7105_clockgena_regs.CKGA_CLKOPSRC_SWITCH_CFG2*/
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG11*/
|
||||
POKE32(0xfe00112c, 0x00001d28)
|
||||
POKE32(0xfe00112c, 0x00001af4)
|
||||
POKE32(0xfe00112c, 0x00000af4)
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_STA3*/
|
||||
WHILE_NE32(0xfe001014, 0x00000001, 0x00000000)
|
||||
|
||||
|
||||
/*set_lmi2x_freq: freq=800.000 rdiv=0x3, ddiv=0x50 Clock frequencies*/
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG04*/
|
||||
POKE32(0xfe001110, 0x000001a2)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG11*/
|
||||
POKE32(0xfe00112c, 0x08000af5)
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG12*/
|
||||
POKE32(0xfe001130, 0xa000380f)
|
||||
POKE32(0xfe001130, 0xa000380f)
|
||||
POKE32(0xfe001130, 0xa000380f)
|
||||
POKE32(0xfe001130, 0xa000380f)
|
||||
POKE32(0xfe001130, 0xa000380f)
|
||||
POKE32(0xfe001130, 0xa000380f)
|
||||
POKE32(0xfe001130, 0xa200380f)
|
||||
POKE32(0xfe001130, 0xa200380f)
|
||||
POKE32(0xfe001130, 0xa200380f)
|
||||
POKE32(0xfe001130, 0xa200380f)
|
||||
POKE32(0xfe001130, 0xa200380f)
|
||||
POKE32(0xfe001130, 0xa200780f)
|
||||
POKE32(0xfe001130, 0xa200780f)
|
||||
POKE32(0xfe001130, 0xa200680f)
|
||||
POKE32(0xfe001130, 0xa200680f)
|
||||
POKE32(0xfe001130, 0xa200680f)
|
||||
POKE32(0xfe001130, 0xa200680f)
|
||||
POKE32(0xfe001130, 0xa200680f)
|
||||
POKE32(0xfe001130, 0xa200684f)
|
||||
POKE32(0xfe001130, 0xa200686f)
|
||||
/*
|
||||
POKE32(0xfe001130, 0xa200687f)
|
||||
POKE32(0xfe001130, 0xa200687f)
|
||||
POKE32(0xfe001130, 0xa200687f)
|
||||
POKE32(0xfe001130, 0xa200687f)
|
||||
POKE32(0xfe001130, 0xa200687f)
|
||||
*/
|
||||
|
||||
POKE32(0xfe001130, 0xa200687f)
|
||||
POKE32(0xfe001130, 0xa200687f)
|
||||
POKE32(0xfe001130, 0xa200687f)
|
||||
POKE32(0xfe001130, 0xa200687f)
|
||||
POKE32(0xfe001130, 0xa200687f)
|
||||
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG13*/
|
||||
POKE32(0xfe001134, 0x00400000)
|
||||
POKE32(0xfe001134, 0x00600000)
|
||||
POKE32(0xfe001134, 0x00600000)
|
||||
POKE32(0xfe001134, 0x00600000)
|
||||
POKE32(0xfe001134, 0x00600000)
|
||||
POKE32(0xfe001134, 0x00600000)
|
||||
POKE32(0xfe001134, 0x00600000)
|
||||
POKE32(0xfe001134, 0x00600000)
|
||||
POKE32(0xfe001134, 0x00600000)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG14*/
|
||||
POKE32(0xfe001138, 0x00000000)
|
||||
POKE32(0xfe001138, 0x00000000)
|
||||
POKE32(0xfe001138, 0x00000000)
|
||||
POKE32(0xfe001138, 0x00000000)
|
||||
POKE32(0xfe001138, 0x00000000)
|
||||
POKE32(0xfe001138, 0x00000000)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG38*/
|
||||
POKE32(0xfe001198, 0x0000fe00)
|
||||
POKE32(0xfe001198, 0x0000fe00)
|
||||
POKE32(0xfe001198, 0x0000fe00)
|
||||
POKE32(0xfe001198, 0x0020fe00)
|
||||
POKE32(0xfe001198, 0x0020fe00)
|
||||
POKE32(0xfe001198, 0x002cfe00)
|
||||
POKE32(0xfe001198, 0x002ffe00)
|
||||
POKE32(0xfe001198, 0x002ffe0c)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG40*/
|
||||
POKE32(0xfe0011a0, 0x00000005)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG42*/
|
||||
POKE32(0xfe0011a8, 0x20000000)
|
||||
POKE32(0xfe0011a8, 0x28000000)
|
||||
POKE32(0xfe0011a8, 0x2fb80000)
|
||||
POKE32(0xfe0011a8, 0x2fbbdc00)
|
||||
POKE32(0xfe0011a8, 0x2fbbddee)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG43*/
|
||||
POKE32(0xfe0011ac, 0x00000000)
|
||||
POKE32(0xfe0011ac, 0x18000000)
|
||||
POKE32(0xfe0011ac, 0x18a00000)
|
||||
POKE32(0xfe0011ac, 0x18a001ee)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG51*/
|
||||
POKE32(0xfe0011cc, 0x00000000)
|
||||
POKE32(0xfe0011cc, 0x00000000)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG52*/
|
||||
POKE32(0xfe0011d0, 0x00000000)
|
||||
POKE32(0xfe0011d0, 0x00000000)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG55*/
|
||||
POKE32(0xfe0011dc, 0x00002000)
|
||||
POKE32(0xfe0011dc, 0x00002000)
|
||||
POKE32(0xfe0011dc, 0x00002000)
|
||||
POKE32(0xfe0011dc, 0x07fc2000)
|
||||
POKE32(0xfe0011dc, 0x07fc2000)
|
||||
POKE32(0xfe0011dc, 0x07fc2000)
|
||||
POKE32(0xfe0011dc, 0x07fc2000)
|
||||
POKE32(0xfe0011dc, 0x07fc2280)
|
||||
POKE32(0xfe0011dc, 0x07fc22c0)
|
||||
POKE32(0xfe0011dc, 0x07fc22c0)
|
||||
POKE32(0xfe0011dc, 0x07fc22c4)
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG04*/
|
||||
POKE32(0xfe001110, 0x000001a6)
|
||||
DELAY(10)
|
||||
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG13*/
|
||||
POKE32(0xfe001134, 0x00600000)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG14*/
|
||||
POKE32(0xfe001138, 0x00000000)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG42*/
|
||||
POKE32(0xfe0011a8, 0x2fbbddee)
|
||||
POKE32(0xfe0011a8, 0x2fbbddee)
|
||||
POKE32(0xfe0011a8, 0x2fbbddee)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG43*/
|
||||
POKE32(0xfe0011ac, 0x18a001ee)
|
||||
POKE32(0xfe0011ac, 0x18a001ee)
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG51*/
|
||||
POKE32(0xfe0011cc, 0x00000000)
|
||||
POKE32(0xfe0011cc, 0x00000000)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG52*/
|
||||
POKE32(0xfe0011d0, 0x00000000)
|
||||
POKE32(0xfe0011d0, 0x00000000)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG55*/
|
||||
POKE32(0xfe0011dc, 0x07fc22c4)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG04*/
|
||||
POKE32(0xfe001110, 0x000001a2)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG11*/
|
||||
POKE32(0xfe00112c, 0x00000af5)
|
||||
POKE32(0xfe00112c, 0x00000af4)
|
||||
DELAY(10)
|
||||
POKE32(0xfe00112c, 0x08000af4)
|
||||
POKE32(0xfe00112c, 0x08000af5)
|
||||
DELAY(10)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG04*/
|
||||
POKE32(0xfe001110, 0x000001a6)
|
||||
DELAY(10)
|
||||
|
||||
|
||||
/*st40_emi_regs.EMI_BANK_ENABLE*/
|
||||
POKE32(0xfe700860, 0x00000005)
|
||||
|
||||
POKE32(0xfe700800, 0x00000000) /*st40_emi_regs.EMI_BANK0_BASEADDRESS*/
|
||||
POKE32(0xfe700810, 0x00000010) /*st40_emi_regs.EMI_BANK1_BASEADDRESS*/
|
||||
POKE32(0xfe700820, 0x00000018) /*st40_emi_regs.EMI_BANK2_BASEADDRESS*/
|
||||
POKE32(0xfe700830, 0x0000001a) /*st40_emi_regs.EMI_BANK3_BASEADDRESS*/
|
||||
POKE32(0xfe700840, 0x0000001c) /*st40_emi_regs.EMI_BANK4_BASEADDRESS*/
|
||||
|
||||
|
||||
|
||||
/*st40_emi_regs.EMI_BANK0_EMICONFIGDATA0-3*/
|
||||
POKE32(0xfe700100, 0x001016d1)
|
||||
POKE32(0xfe700108, 0x9d200000)
|
||||
POKE32(0xfe700110, 0x9d220000)
|
||||
POKE32(0xfe700118, 0x00000000)
|
||||
|
||||
|
||||
/*st40_emi_regs.EMI_BANK1_EMICONFIGDATA0-3*/
|
||||
POKE32(0xfe700140, 0x002016d1)
|
||||
POKE32(0xfe700148, 0x9d222200)
|
||||
POKE32(0xfe700150, 0x9d220044)
|
||||
POKE32(0xfe700158, 0x00000000)
|
||||
|
||||
|
||||
/*st40_emi_regs.EMI_BANK2_EMICONFIGDATA0-3*/
|
||||
POKE32(0xfe700180, 0x002046f9)
|
||||
POKE32(0xfe700188, 0xa5a00000)
|
||||
POKE32(0xfe700190, 0xa5a20000)
|
||||
POKE32(0xfe700198, 0x00000000)
|
||||
|
||||
|
||||
/*st40_emi_regs.EMI_BANK3_EMICONFIGDATA0-3*/
|
||||
POKE32(0xfe7001c0, 0x002016d1)
|
||||
POKE32(0xfe7001c8, 0x9d222200)
|
||||
POKE32(0xfe7001d0, 0x9d220044)
|
||||
POKE32(0xfe7001d8, 0x00000000)
|
||||
|
||||
|
||||
/*st40_emi_regs.EMI_BANK4_EMICONFIGDATA0-3*/
|
||||
POKE32(0xfe700200, 0x002016d1)
|
||||
POKE32(0xfe700208, 0x9d222200)
|
||||
POKE32(0xfe700210, 0x9d220044)
|
||||
POKE32(0xfe700218, 0x00000000)
|
||||
|
||||
|
||||
/*st40_emi_regs.EMI_GENCFG*/
|
||||
POKE32(0xfe700028, 0x00000010)
|
||||
|
||||
|
||||
/*st40_lmigp_regs.LMI_MIM_0-1*/
|
||||
POKE32(0xfe901008, 0x0b30017b)
|
||||
POKE32(0xfe90100c, 0x000000b0)
|
||||
|
||||
|
||||
/*st40_lmigp_regs.LMI_STR_0-1*/
|
||||
POKE32(0xfe901018, 0xcf35b424)
|
||||
POKE32(0xfe90101c, 0x00242ed8)
|
||||
|
||||
/*st40_lmigp_regs.LMI_SDRA0_0-1*/
|
||||
POKE32(0xfe901030, 0x1c001a20)
|
||||
POKE32(0xfe901038, 0x1c001a20)
|
||||
DELAY(200000)
|
||||
|
||||
|
||||
/*st40_lmigp_regs.LMI_SCR_0*/
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020023)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020022)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
|
||||
|
||||
/*st40_lmigp_regs.LMI_SDMR0_0*/
|
||||
POKE32(0xfe901048, 0x00010000)
|
||||
|
||||
/*st40_lmigp_regs.LMI_SDMR0_0*/
|
||||
POKE32(0xfe901048, 0x00018000)
|
||||
|
||||
/*st40_lmigp_regs.LMI_SDMR0_0*/
|
||||
POKE32(0xfe901048, 0x00008006)
|
||||
|
||||
/*st40_lmigp_regs.LMI_SDMR0_0*/
|
||||
POKE32(0xfe901048, 0x00004363)
|
||||
|
||||
/*st40_lmigp_regs.LMI_SCR_0*/
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020022)
|
||||
POKE32(0xfe901010, 0x00020024)
|
||||
POKE32(0xfe901010, 0x00020024)
|
||||
|
||||
|
||||
/*st40_lmigp_regs.LMI_SDMR0_0*/
|
||||
POKE32(0xfe901048, 0x00004263)
|
||||
|
||||
/*st40_lmigp_regs.LMI_MIM_0*/
|
||||
POKE32(0xfe901008, 0x0b30037b)
|
||||
POKE32(0xfe901008, 0x0b30037b)
|
||||
|
||||
|
||||
/*st40_lmigp_regs.LMI_SCR_0*/
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
POKE32(0xfe901010, 0x00020021)
|
||||
|
||||
|
||||
/*st40_lmigp_regs.LMI_GCC_0*/
|
||||
POKE32(0xfe901028, 0x00000000)
|
||||
|
||||
/*Info: correcting interco reset setup*/
|
||||
POKE32(0xfe20d200, 0x00000005)
|
||||
POKE32(0xfe20d204, 0x00000004)
|
||||
POKE32(0xfe20d208, 0x00000003)
|
||||
POKE32(0xfe20d20c, 0x00000002)
|
||||
POKE32(0xfe20d210, 0x00000001)
|
||||
POKE32(0xfe20d214, 0x00000001)
|
||||
POKE32(0xfe20d218, 0x00000001)
|
||||
POKE32(0xfe20d21c, 0x00000001)
|
||||
POKE32(0xfe20d220, 0x00000001)
|
||||
POKE32(0xfe2410fc, 0x00000005)
|
||||
POKE32(0xfe20a0ec, 0x00000002)
|
||||
POKE32(0xfe20a0f0, 0x00000005)
|
||||
POKE32(0xfe20a0f4, 0x00000003)
|
||||
POKE32(0xfe20a0f8, 0x00000003)
|
||||
POKE32(0xfe20a1ec, 0x00000002)
|
||||
POKE32(0xfe20a1f0, 0x00000005)
|
||||
POKE32(0xfe20a1f4, 0x00000003)
|
||||
POKE32(0xfe20a1f8, 0x00000003)
|
||||
POKE32(0xfe20a1fc, 0x00000000)
|
||||
POKE32(0xfe20a2ec, 0x00000002)
|
||||
POKE32(0xfe20a2f0, 0x00000005)
|
||||
POKE32(0xfe20a2f4, 0x00000003)
|
||||
POKE32(0xfe20a2f8, 0x00000003)
|
||||
POKE32(0xfe20a2fc, 0x00000000)
|
||||
POKE32(0xfe20a3ec, 0x00000002)
|
||||
POKE32(0xfe20a3f0, 0x00000005)
|
||||
POKE32(0xfe20a3f4, 0x00000003)
|
||||
POKE32(0xfe20a3f8, 0x00000003)
|
||||
POKE32(0xfe20a3fc, 0x00000000)
|
||||
POKE32(0xfe20aefc, 0x00000005)
|
||||
POKE32(0xfe540034, 0x00000003)
|
||||
POKE32(0xfe540038, 0x00000000)
|
||||
POKE32(0xfe540110, 0x00010303)
|
||||
POKE32(0xfe540114, 0x00000000)
|
||||
POKE32(0xfe540030, 0x00000005)
|
||||
POKE32(0xfe54010c, 0x00000005)
|
||||
POKE32(0xfe540600, 0x00000006)
|
||||
POKE32(0xfe540604, 0x00000005)
|
||||
POKE32(0xfe540608, 0x00000004)
|
||||
POKE32(0xfe54060c, 0x00000003)
|
||||
POKE32(0xfe540610, 0x00000002)
|
||||
POKE32(0xfe540614, 0x00000001)
|
||||
POKE32(0xfe540618, 0x00000000)
|
||||
POKE32(0xfe540680, 0x00000001)
|
||||
POKE32(0xfe540684, 0x00000000)
|
||||
POKE32(0xfe20bb04, 0x00000005)
|
||||
POKE32(0xfe20bb08, 0x00000003)
|
||||
POKE32(0xfe20bb10, 0x00000002)
|
||||
POKE32(0xfe20bb24, 0x00000005)
|
||||
POKE32(0xfe20bb28, 0x00000003)
|
||||
POKE32(0xfe20bb2c, 0x00000000)
|
||||
POKE32(0xfe20bb30, 0x00000002)
|
||||
POKE32(0xfe20bb44, 0x00000005)
|
||||
POKE32(0xfe20bb48, 0x00000003)
|
||||
POKE32(0xfe20bb4c, 0x00000000)
|
||||
POKE32(0xfe20bb50, 0x00000002)
|
||||
POKE32(0xfe20bb84, 0x00000005)
|
||||
POKE32(0xfe20bb88, 0x00000003)
|
||||
POKE32(0xfe20bb8c, 0x00000000)
|
||||
POKE32(0xfe20bb90, 0x00000002)
|
||||
POKE32(0xfe20a0fc, 0x00000000)
|
||||
POKE32(0xfe20bb0c, 0x00000000)
|
||||
POKE32(0xfe231010, 0x00000008)
|
||||
POKE32(0xfe231080, 0x00000221)
|
||||
POKE32(0xfe261010, 0x00000008)
|
||||
POKE32(0xfe261080, 0x00000221)
|
||||
POKE32(0xfd101024, 0x0003c000)
|
||||
POKE32(0xfd101824, 0x0003c000)
|
||||
POKE32(0xfd104d24, 0x0003c000)
|
||||
POKE32(0xfd102024, 0x0003c000)
|
||||
/* PEEK(0xfe001180) (used target peek value 0x00000b35) */
|
||||
POKE32(0xfe001180, 0x00000b05)
|
||||
POKE32(0xfe1fff04, 0x00254608)
|
||||
POKE32(0xfeafff04, 0x00254608)
|
||||
/* PEEK(0xfe00111c) (used target peek value 0x08081508) */
|
||||
POKE32(0xfe00111c, 0x08091508)
|
||||
POKE32(0xfd117000, 0x0025c608)
|
||||
POKE32(0xfd111000, 0x00201004)
|
||||
/* PEEK(0xfe001180) (used target peek value 0x00000b05) */
|
||||
POKE32(0xfe001180, 0x00000b01)
|
||||
POKE32(0xfe401744, 0x0025c005)
|
||||
|
||||
|
||||
/*st40_ccn_regs.CCN_CCR*/
|
||||
POKE32(0xff00001c, 0x8000090d)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG09*/
|
||||
POKE32(0xfe001124, 0x08000a8c)
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG05*/
|
||||
POKE32(0xfe001114, 0x04000040)
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG26*/
|
||||
POKE32(0xfe001168, 0xfe804001)
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG27*/
|
||||
POKE32(0xfe00116c, 0x00001fd1)
|
||||
POKE32(0xfe00116c, 0x00001fd0)
|
||||
|
||||
/*stx7105: booted audio companion*/
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG09*/
|
||||
POKE32(0xfe001124, 0x08000a8c)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG05*/
|
||||
POKE32(0xfe001114, 0x04000040)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG28*/
|
||||
POKE32(0xfe001170, 0xfe604001)
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG29*/
|
||||
POKE32(0xfe001174, 0x00001fcd)
|
||||
|
||||
|
||||
/*stx7105_sysconf_regs.SYSCONF_CFG29*/
|
||||
POKE32(0xfe001174, 0x00001fcc)
|
||||
|
||||
/* stx7105: booted video companion*/
|
||||
/* TCK frequency set to 12500000 Hz*/
|
||||
/* tapmux complete_connect(): single core setup*/
|
||||
/* sdk7105 initialization complete*/
|
||||
Loading…
Reference in New Issue