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STM32H750VB_Bootloader/build/stm32h7xx_hal_msp.lst

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Updated HAL library.
2020-12-20 16:04:43 +00:00
ARM GAS /tmp/ccYeBZUP.s page 1
1 .cpu cortex-m7
2 .eabi_attribute 28, 1
3 .eabi_attribute 20, 1
4 .eabi_attribute 21, 1
5 .eabi_attribute 23, 3
6 .eabi_attribute 24, 1
7 .eabi_attribute 25, 1
8 .eabi_attribute 26, 1
9 .eabi_attribute 30, 1
10 .eabi_attribute 34, 1
11 .eabi_attribute 18, 4
12 .file "stm32h7xx_hal_msp.c"
13 .text
14 .Ltext0:
15 .cfi_sections .debug_frame
16 .section .text.HAL_MspInit,"ax",%progbits
17 .align 1
18 .global HAL_MspInit
19 .arch armv7e-m
20 .syntax unified
21 .thumb
22 .thumb_func
23 .fpu fpv5-d16
25 HAL_MspInit:
26 .LFB141:
27 .file 1 "Core/Src/stm32h7xx_hal_msp.c"
1:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Header */
2:Core/Src/stm32h7xx_hal_msp.c **** /**
3:Core/Src/stm32h7xx_hal_msp.c **** ******************************************************************************
4:Core/Src/stm32h7xx_hal_msp.c **** * File Name : stm32h7xx_hal_msp.c
5:Core/Src/stm32h7xx_hal_msp.c **** * Description : This file provides code for the MSP Initialization
6:Core/Src/stm32h7xx_hal_msp.c **** * and de-Initialization codes.
7:Core/Src/stm32h7xx_hal_msp.c **** ******************************************************************************
8:Core/Src/stm32h7xx_hal_msp.c **** * @attention
9:Core/Src/stm32h7xx_hal_msp.c **** *
10:Core/Src/stm32h7xx_hal_msp.c **** * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
11:Core/Src/stm32h7xx_hal_msp.c **** * All rights reserved.</center></h2>
12:Core/Src/stm32h7xx_hal_msp.c **** *
13:Core/Src/stm32h7xx_hal_msp.c **** * This software component is licensed by ST under BSD 3-Clause license,
14:Core/Src/stm32h7xx_hal_msp.c **** * the "License"; You may not use this file except in compliance with the
15:Core/Src/stm32h7xx_hal_msp.c **** * License. You may obtain a copy of the License at:
16:Core/Src/stm32h7xx_hal_msp.c **** * opensource.org/licenses/BSD-3-Clause
17:Core/Src/stm32h7xx_hal_msp.c **** *
18:Core/Src/stm32h7xx_hal_msp.c **** ******************************************************************************
19:Core/Src/stm32h7xx_hal_msp.c **** */
20:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Header */
21:Core/Src/stm32h7xx_hal_msp.c ****
22:Core/Src/stm32h7xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
23:Core/Src/stm32h7xx_hal_msp.c **** #include "main.h"
24:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Includes */
25:Core/Src/stm32h7xx_hal_msp.c ****
26:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Includes */
27:Core/Src/stm32h7xx_hal_msp.c ****
28:Core/Src/stm32h7xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
29:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TD */
30:Core/Src/stm32h7xx_hal_msp.c ****
31:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TD */
ARM GAS /tmp/ccYeBZUP.s page 2
32:Core/Src/stm32h7xx_hal_msp.c ****
33:Core/Src/stm32h7xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
34:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Define */
35:Core/Src/stm32h7xx_hal_msp.c ****
36:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Define */
37:Core/Src/stm32h7xx_hal_msp.c ****
38:Core/Src/stm32h7xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
39:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Macro */
40:Core/Src/stm32h7xx_hal_msp.c ****
41:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Macro */
42:Core/Src/stm32h7xx_hal_msp.c ****
43:Core/Src/stm32h7xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
44:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN PV */
45:Core/Src/stm32h7xx_hal_msp.c ****
46:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END PV */
47:Core/Src/stm32h7xx_hal_msp.c ****
48:Core/Src/stm32h7xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
49:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN PFP */
50:Core/Src/stm32h7xx_hal_msp.c ****
51:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END PFP */
52:Core/Src/stm32h7xx_hal_msp.c ****
53:Core/Src/stm32h7xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
54:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
55:Core/Src/stm32h7xx_hal_msp.c ****
56:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
57:Core/Src/stm32h7xx_hal_msp.c ****
58:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN 0 */
59:Core/Src/stm32h7xx_hal_msp.c ****
60:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END 0 */
61:Core/Src/stm32h7xx_hal_msp.c **** /**
62:Core/Src/stm32h7xx_hal_msp.c **** * Initializes the Global MSP.
63:Core/Src/stm32h7xx_hal_msp.c **** */
64:Core/Src/stm32h7xx_hal_msp.c **** void HAL_MspInit(void)
65:Core/Src/stm32h7xx_hal_msp.c **** {
28 .loc 1 65 1 view -0
29 .cfi_startproc
30 @ args = 0, pretend = 0, frame = 8
31 @ frame_needed = 0, uses_anonymous_args = 0
32 0000 00B5 push {lr}
33 .LCFI0:
34 .cfi_def_cfa_offset 4
35 .cfi_offset 14, -4
36 0002 83B0 sub sp, sp, #12
37 .LCFI1:
38 .cfi_def_cfa_offset 16
66:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */
67:Core/Src/stm32h7xx_hal_msp.c ****
68:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END MspInit 0 */
69:Core/Src/stm32h7xx_hal_msp.c ****
70:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_SYSCFG_CLK_ENABLE();
39 .loc 1 70 3 view .LVU1
40 .LBB2:
41 .loc 1 70 3 view .LVU2
42 .loc 1 70 3 view .LVU3
43 0004 1B4B ldr r3, .L3
44 0006 D3F8F420 ldr r2, [r3, #244]
45 000a 42F00202 orr r2, r2, #2
ARM GAS /tmp/ccYeBZUP.s page 3
46 000e C3F8F420 str r2, [r3, #244]
47 .loc 1 70 3 view .LVU4
48 0012 D3F8F430 ldr r3, [r3, #244]
49 0016 03F00203 and r3, r3, #2
50 001a 0193 str r3, [sp, #4]
51 .loc 1 70 3 view .LVU5
52 001c 019B ldr r3, [sp, #4]
53 .LBE2:
54 .loc 1 70 3 view .LVU6
71:Core/Src/stm32h7xx_hal_msp.c ****
72:Core/Src/stm32h7xx_hal_msp.c **** /* System interrupt init*/
73:Core/Src/stm32h7xx_hal_msp.c ****
74:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral interrupt init */
75:Core/Src/stm32h7xx_hal_msp.c **** /* PVD_AVD_IRQn interrupt configuration */
76:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(PVD_AVD_IRQn, 0, 0);
55 .loc 1 76 3 view .LVU7
56 001e 0022 movs r2, #0
57 0020 1146 mov r1, r2
58 0022 0120 movs r0, #1
59 0024 FFF7FEFF bl HAL_NVIC_SetPriority
60 .LVL0:
77:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(PVD_AVD_IRQn);
61 .loc 1 77 3 view .LVU8
62 0028 0120 movs r0, #1
63 002a FFF7FEFF bl HAL_NVIC_EnableIRQ
64 .LVL1:
78:Core/Src/stm32h7xx_hal_msp.c **** /* FLASH_IRQn interrupt configuration */
79:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(FLASH_IRQn, 0, 0);
65 .loc 1 79 3 view .LVU9
66 002e 0022 movs r2, #0
67 0030 1146 mov r1, r2
68 0032 0420 movs r0, #4
69 0034 FFF7FEFF bl HAL_NVIC_SetPriority
70 .LVL2:
80:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(FLASH_IRQn);
71 .loc 1 80 3 view .LVU10
72 0038 0420 movs r0, #4
73 003a FFF7FEFF bl HAL_NVIC_EnableIRQ
74 .LVL3:
81:Core/Src/stm32h7xx_hal_msp.c **** /* RCC_IRQn interrupt configuration */
82:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(RCC_IRQn, 0, 0);
75 .loc 1 82 3 view .LVU11
76 003e 0022 movs r2, #0
77 0040 1146 mov r1, r2
78 0042 0520 movs r0, #5
79 0044 FFF7FEFF bl HAL_NVIC_SetPriority
80 .LVL4:
83:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(RCC_IRQn);
81 .loc 1 83 3 view .LVU12
82 0048 0520 movs r0, #5
83 004a FFF7FEFF bl HAL_NVIC_EnableIRQ
84 .LVL5:
84:Core/Src/stm32h7xx_hal_msp.c **** /* FPU_IRQn interrupt configuration */
85:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(FPU_IRQn, 0, 0);
85 .loc 1 85 3 view .LVU13
86 004e 0022 movs r2, #0
87 0050 1146 mov r1, r2
ARM GAS /tmp/ccYeBZUP.s page 4
88 0052 5120 movs r0, #81
89 0054 FFF7FEFF bl HAL_NVIC_SetPriority
90 .LVL6:
86:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(FPU_IRQn);
91 .loc 1 86 3 view .LVU14
92 0058 5120 movs r0, #81
93 005a FFF7FEFF bl HAL_NVIC_EnableIRQ
94 .LVL7:
87:Core/Src/stm32h7xx_hal_msp.c **** /* HSEM1_IRQn interrupt configuration */
88:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(HSEM1_IRQn, 0, 0);
95 .loc 1 88 3 view .LVU15
96 005e 0022 movs r2, #0
97 0060 1146 mov r1, r2
98 0062 7D20 movs r0, #125
99 0064 FFF7FEFF bl HAL_NVIC_SetPriority
100 .LVL8:
89:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(HSEM1_IRQn);
101 .loc 1 89 3 view .LVU16
102 0068 7D20 movs r0, #125
103 006a FFF7FEFF bl HAL_NVIC_EnableIRQ
104 .LVL9:
90:Core/Src/stm32h7xx_hal_msp.c ****
91:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */
92:Core/Src/stm32h7xx_hal_msp.c ****
93:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END MspInit 1 */
94:Core/Src/stm32h7xx_hal_msp.c **** }
105 .loc 1 94 1 is_stmt 0 view .LVU17
106 006e 03B0 add sp, sp, #12
107 .LCFI2:
108 .cfi_def_cfa_offset 4
109 @ sp needed
110 0070 5DF804FB ldr pc, [sp], #4
111 .L4:
112 .align 2
113 .L3:
114 0074 00440258 .word 1476543488
115 .cfi_endproc
116 .LFE141:
118 .section .text.HAL_QSPI_MspInit,"ax",%progbits
119 .align 1
120 .global HAL_QSPI_MspInit
121 .syntax unified
122 .thumb
123 .thumb_func
124 .fpu fpv5-d16
126 HAL_QSPI_MspInit:
127 .LVL10:
128 .LFB142:
95:Core/Src/stm32h7xx_hal_msp.c ****
96:Core/Src/stm32h7xx_hal_msp.c **** /**
97:Core/Src/stm32h7xx_hal_msp.c **** * @brief QSPI MSP Initialization
98:Core/Src/stm32h7xx_hal_msp.c **** * This function configures the hardware resources used in this example
99:Core/Src/stm32h7xx_hal_msp.c **** * @param hqspi: QSPI handle pointer
100:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
101:Core/Src/stm32h7xx_hal_msp.c **** */
102:Core/Src/stm32h7xx_hal_msp.c **** void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
103:Core/Src/stm32h7xx_hal_msp.c **** {
ARM GAS /tmp/ccYeBZUP.s page 5
129 .loc 1 103 1 is_stmt 1 view -0
130 .cfi_startproc
131 @ args = 0, pretend = 0, frame = 40
132 @ frame_needed = 0, uses_anonymous_args = 0
133 .loc 1 103 1 is_stmt 0 view .LVU19
134 0000 F0B5 push {r4, r5, r6, r7, lr}
135 .LCFI3:
136 .cfi_def_cfa_offset 20
137 .cfi_offset 4, -20
138 .cfi_offset 5, -16
139 .cfi_offset 6, -12
140 .cfi_offset 7, -8
141 .cfi_offset 14, -4
142 0002 8BB0 sub sp, sp, #44
143 .LCFI4:
144 .cfi_def_cfa_offset 64
104:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
145 .loc 1 104 3 is_stmt 1 view .LVU20
146 .loc 1 104 20 is_stmt 0 view .LVU21
147 0004 0023 movs r3, #0
148 0006 0593 str r3, [sp, #20]
149 0008 0693 str r3, [sp, #24]
150 000a 0793 str r3, [sp, #28]
151 000c 0893 str r3, [sp, #32]
152 000e 0993 str r3, [sp, #36]
105:Core/Src/stm32h7xx_hal_msp.c **** if(hqspi->Instance==QUADSPI)
153 .loc 1 105 3 is_stmt 1 view .LVU22
154 .loc 1 105 11 is_stmt 0 view .LVU23
155 0010 0268 ldr r2, [r0]
156 .loc 1 105 5 view .LVU24
157 0012 354B ldr r3, .L9
158 0014 9A42 cmp r2, r3
159 0016 01D0 beq .L8
160 .LVL11:
161 .L5:
106:Core/Src/stm32h7xx_hal_msp.c **** {
107:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspInit 0 */
108:Core/Src/stm32h7xx_hal_msp.c ****
109:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END QUADSPI_MspInit 0 */
110:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */
111:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_QSPI_CLK_ENABLE();
112:Core/Src/stm32h7xx_hal_msp.c ****
113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOE_CLK_ENABLE();
114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
115:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
116:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration
117:Core/Src/stm32h7xx_hal_msp.c **** PE2 ------> QUADSPI_BK1_IO2
118:Core/Src/stm32h7xx_hal_msp.c **** PB2 ------> QUADSPI_CLK
119:Core/Src/stm32h7xx_hal_msp.c **** PD11 ------> QUADSPI_BK1_IO0
120:Core/Src/stm32h7xx_hal_msp.c **** PD12 ------> QUADSPI_BK1_IO1
121:Core/Src/stm32h7xx_hal_msp.c **** PD13 ------> QUADSPI_BK1_IO3
122:Core/Src/stm32h7xx_hal_msp.c **** PB6 ------> QUADSPI_BK1_NCS
123:Core/Src/stm32h7xx_hal_msp.c **** */
124:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_2;
125:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
126:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
127:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
ARM GAS /tmp/ccYeBZUP.s page 6
128:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
129:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
130:Core/Src/stm32h7xx_hal_msp.c ****
131:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_2;
132:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
133:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
134:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
135:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
136:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
137:Core/Src/stm32h7xx_hal_msp.c ****
138:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13;
139:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
140:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
141:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
142:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
143:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
144:Core/Src/stm32h7xx_hal_msp.c ****
145:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_6;
146:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
147:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
148:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
149:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
150:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
151:Core/Src/stm32h7xx_hal_msp.c ****
152:Core/Src/stm32h7xx_hal_msp.c **** /* QUADSPI interrupt Init */
153:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(QUADSPI_IRQn, 1, 0);
154:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
155:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspInit 1 */
156:Core/Src/stm32h7xx_hal_msp.c ****
157:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END QUADSPI_MspInit 1 */
158:Core/Src/stm32h7xx_hal_msp.c **** }
159:Core/Src/stm32h7xx_hal_msp.c ****
160:Core/Src/stm32h7xx_hal_msp.c **** }
162 .loc 1 160 1 view .LVU25
163 0018 0BB0 add sp, sp, #44
164 .LCFI5:
165 .cfi_remember_state
166 .cfi_def_cfa_offset 20
167 @ sp needed
168 001a F0BD pop {r4, r5, r6, r7, pc}
169 .LVL12:
170 .L8:
171 .LCFI6:
172 .cfi_restore_state
111:Core/Src/stm32h7xx_hal_msp.c ****
173 .loc 1 111 5 is_stmt 1 view .LVU26
174 .LBB3:
111:Core/Src/stm32h7xx_hal_msp.c ****
175 .loc 1 111 5 view .LVU27
111:Core/Src/stm32h7xx_hal_msp.c ****
176 .loc 1 111 5 view .LVU28
177 001c 334B ldr r3, .L9+4
178 001e D3F8D420 ldr r2, [r3, #212]
179 0022 42F48042 orr r2, r2, #16384
180 0026 C3F8D420 str r2, [r3, #212]
111:Core/Src/stm32h7xx_hal_msp.c ****
181 .loc 1 111 5 view .LVU29
ARM GAS /tmp/ccYeBZUP.s page 7
182 002a D3F8D420 ldr r2, [r3, #212]
183 002e 02F48042 and r2, r2, #16384
184 0032 0192 str r2, [sp, #4]
111:Core/Src/stm32h7xx_hal_msp.c ****
185 .loc 1 111 5 view .LVU30
186 0034 019A ldr r2, [sp, #4]
187 .LBE3:
111:Core/Src/stm32h7xx_hal_msp.c ****
188 .loc 1 111 5 view .LVU31
113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
189 .loc 1 113 5 view .LVU32
190 .LBB4:
113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
191 .loc 1 113 5 view .LVU33
113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
192 .loc 1 113 5 view .LVU34
193 0036 D3F8E020 ldr r2, [r3, #224]
194 003a 42F01002 orr r2, r2, #16
195 003e C3F8E020 str r2, [r3, #224]
113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
196 .loc 1 113 5 view .LVU35
197 0042 D3F8E020 ldr r2, [r3, #224]
198 0046 02F01002 and r2, r2, #16
199 004a 0292 str r2, [sp, #8]
113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
200 .loc 1 113 5 view .LVU36
201 004c 029A ldr r2, [sp, #8]
202 .LBE4:
113:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
203 .loc 1 113 5 view .LVU37
114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
204 .loc 1 114 5 view .LVU38
205 .LBB5:
114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
206 .loc 1 114 5 view .LVU39
114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
207 .loc 1 114 5 view .LVU40
208 004e D3F8E020 ldr r2, [r3, #224]
209 0052 42F00202 orr r2, r2, #2
210 0056 C3F8E020 str r2, [r3, #224]
114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
211 .loc 1 114 5 view .LVU41
212 005a D3F8E020 ldr r2, [r3, #224]
213 005e 02F00202 and r2, r2, #2
214 0062 0392 str r2, [sp, #12]
114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
215 .loc 1 114 5 view .LVU42
216 0064 039A ldr r2, [sp, #12]
217 .LBE5:
114:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
218 .loc 1 114 5 view .LVU43
115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration
219 .loc 1 115 5 view .LVU44
220 .LBB6:
115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration
221 .loc 1 115 5 view .LVU45
115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration
ARM GAS /tmp/ccYeBZUP.s page 8
222 .loc 1 115 5 view .LVU46
223 0066 D3F8E020 ldr r2, [r3, #224]
224 006a 42F00802 orr r2, r2, #8
225 006e C3F8E020 str r2, [r3, #224]
115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration
226 .loc 1 115 5 view .LVU47
227 0072 D3F8E030 ldr r3, [r3, #224]
228 0076 03F00803 and r3, r3, #8
229 007a 0493 str r3, [sp, #16]
115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration
230 .loc 1 115 5 view .LVU48
231 007c 049B ldr r3, [sp, #16]
232 .LBE6:
115:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration
233 .loc 1 115 5 view .LVU49
124:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
234 .loc 1 124 5 view .LVU50
124:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
235 .loc 1 124 25 is_stmt 0 view .LVU51
236 007e 0424 movs r4, #4
237 0080 0594 str r4, [sp, #20]
125:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
238 .loc 1 125 5 is_stmt 1 view .LVU52
125:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
239 .loc 1 125 26 is_stmt 0 view .LVU53
240 0082 0225 movs r5, #2
241 0084 0695 str r5, [sp, #24]
126:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
242 .loc 1 126 5 is_stmt 1 view .LVU54
127:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
243 .loc 1 127 5 view .LVU55
128:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
244 .loc 1 128 5 view .LVU56
128:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
245 .loc 1 128 31 is_stmt 0 view .LVU57
246 0086 0926 movs r6, #9
247 0088 0996 str r6, [sp, #36]
129:Core/Src/stm32h7xx_hal_msp.c ****
248 .loc 1 129 5 is_stmt 1 view .LVU58
249 008a 05A9 add r1, sp, #20
250 008c 1848 ldr r0, .L9+8
251 .LVL13:
129:Core/Src/stm32h7xx_hal_msp.c ****
252 .loc 1 129 5 is_stmt 0 view .LVU59
253 008e FFF7FEFF bl HAL_GPIO_Init
254 .LVL14:
131:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
255 .loc 1 131 5 is_stmt 1 view .LVU60
131:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
256 .loc 1 131 25 is_stmt 0 view .LVU61
257 0092 0594 str r4, [sp, #20]
132:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
258 .loc 1 132 5 is_stmt 1 view .LVU62
132:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
259 .loc 1 132 26 is_stmt 0 view .LVU63
260 0094 0695 str r5, [sp, #24]
133:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
ARM GAS /tmp/ccYeBZUP.s page 9
261 .loc 1 133 5 is_stmt 1 view .LVU64
133:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
262 .loc 1 133 26 is_stmt 0 view .LVU65
263 0096 0024 movs r4, #0
264 0098 0794 str r4, [sp, #28]
134:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
265 .loc 1 134 5 is_stmt 1 view .LVU66
134:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
266 .loc 1 134 27 is_stmt 0 view .LVU67
267 009a 0894 str r4, [sp, #32]
135:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
268 .loc 1 135 5 is_stmt 1 view .LVU68
135:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
269 .loc 1 135 31 is_stmt 0 view .LVU69
270 009c 0996 str r6, [sp, #36]
136:Core/Src/stm32h7xx_hal_msp.c ****
271 .loc 1 136 5 is_stmt 1 view .LVU70
272 009e 154F ldr r7, .L9+12
273 00a0 05A9 add r1, sp, #20
274 00a2 3846 mov r0, r7
275 00a4 FFF7FEFF bl HAL_GPIO_Init
276 .LVL15:
138:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
277 .loc 1 138 5 view .LVU71
138:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
278 .loc 1 138 25 is_stmt 0 view .LVU72
279 00a8 4FF46053 mov r3, #14336
280 00ac 0593 str r3, [sp, #20]
139:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
281 .loc 1 139 5 is_stmt 1 view .LVU73
139:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
282 .loc 1 139 26 is_stmt 0 view .LVU74
283 00ae 0695 str r5, [sp, #24]
140:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
284 .loc 1 140 5 is_stmt 1 view .LVU75
140:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
285 .loc 1 140 26 is_stmt 0 view .LVU76
286 00b0 0794 str r4, [sp, #28]
141:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
287 .loc 1 141 5 is_stmt 1 view .LVU77
141:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
288 .loc 1 141 27 is_stmt 0 view .LVU78
289 00b2 0894 str r4, [sp, #32]
142:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
290 .loc 1 142 5 is_stmt 1 view .LVU79
142:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
291 .loc 1 142 31 is_stmt 0 view .LVU80
292 00b4 0996 str r6, [sp, #36]
143:Core/Src/stm32h7xx_hal_msp.c ****
293 .loc 1 143 5 is_stmt 1 view .LVU81
294 00b6 05A9 add r1, sp, #20
295 00b8 0F48 ldr r0, .L9+16
296 00ba FFF7FEFF bl HAL_GPIO_Init
297 .LVL16:
145:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
298 .loc 1 145 5 view .LVU82
145:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
ARM GAS /tmp/ccYeBZUP.s page 10
299 .loc 1 145 25 is_stmt 0 view .LVU83
300 00be 4023 movs r3, #64
301 00c0 0593 str r3, [sp, #20]
146:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
302 .loc 1 146 5 is_stmt 1 view .LVU84
146:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
303 .loc 1 146 26 is_stmt 0 view .LVU85
304 00c2 0695 str r5, [sp, #24]
147:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
305 .loc 1 147 5 is_stmt 1 view .LVU86
147:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
306 .loc 1 147 26 is_stmt 0 view .LVU87
307 00c4 0794 str r4, [sp, #28]
148:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
308 .loc 1 148 5 is_stmt 1 view .LVU88
148:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
309 .loc 1 148 27 is_stmt 0 view .LVU89
310 00c6 0894 str r4, [sp, #32]
149:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
311 .loc 1 149 5 is_stmt 1 view .LVU90
149:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
312 .loc 1 149 31 is_stmt 0 view .LVU91
313 00c8 0A23 movs r3, #10
314 00ca 0993 str r3, [sp, #36]
150:Core/Src/stm32h7xx_hal_msp.c ****
315 .loc 1 150 5 is_stmt 1 view .LVU92
316 00cc 05A9 add r1, sp, #20
317 00ce 3846 mov r0, r7
318 00d0 FFF7FEFF bl HAL_GPIO_Init
319 .LVL17:
153:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
320 .loc 1 153 5 view .LVU93
321 00d4 2246 mov r2, r4
322 00d6 0121 movs r1, #1
323 00d8 5C20 movs r0, #92
324 00da FFF7FEFF bl HAL_NVIC_SetPriority
325 .LVL18:
154:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspInit 1 */
326 .loc 1 154 5 view .LVU94
327 00de 5C20 movs r0, #92
328 00e0 FFF7FEFF bl HAL_NVIC_EnableIRQ
329 .LVL19:
330 .loc 1 160 1 is_stmt 0 view .LVU95
331 00e4 98E7 b .L5
332 .L10:
333 00e6 00BF .align 2
334 .L9:
335 00e8 00500052 .word 1375752192
336 00ec 00440258 .word 1476543488
337 00f0 00100258 .word 1476530176
338 00f4 00040258 .word 1476527104
339 00f8 000C0258 .word 1476529152
340 .cfi_endproc
341 .LFE142:
343 .section .text.HAL_QSPI_MspDeInit,"ax",%progbits
344 .align 1
345 .global HAL_QSPI_MspDeInit
ARM GAS /tmp/ccYeBZUP.s page 11
346 .syntax unified
347 .thumb
348 .thumb_func
349 .fpu fpv5-d16
351 HAL_QSPI_MspDeInit:
352 .LVL20:
353 .LFB143:
161:Core/Src/stm32h7xx_hal_msp.c ****
162:Core/Src/stm32h7xx_hal_msp.c **** /**
163:Core/Src/stm32h7xx_hal_msp.c **** * @brief QSPI MSP De-Initialization
164:Core/Src/stm32h7xx_hal_msp.c **** * This function freeze the hardware resources used in this example
165:Core/Src/stm32h7xx_hal_msp.c **** * @param hqspi: QSPI handle pointer
166:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
167:Core/Src/stm32h7xx_hal_msp.c **** */
168:Core/Src/stm32h7xx_hal_msp.c **** void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi)
169:Core/Src/stm32h7xx_hal_msp.c **** {
354 .loc 1 169 1 is_stmt 1 view -0
355 .cfi_startproc
356 @ args = 0, pretend = 0, frame = 0
357 @ frame_needed = 0, uses_anonymous_args = 0
358 .loc 1 169 1 is_stmt 0 view .LVU97
359 0000 08B5 push {r3, lr}
360 .LCFI7:
361 .cfi_def_cfa_offset 8
362 .cfi_offset 3, -8
363 .cfi_offset 14, -4
170:Core/Src/stm32h7xx_hal_msp.c **** if(hqspi->Instance==QUADSPI)
364 .loc 1 170 3 is_stmt 1 view .LVU98
365 .loc 1 170 11 is_stmt 0 view .LVU99
366 0002 0268 ldr r2, [r0]
367 .loc 1 170 5 view .LVU100
368 0004 0D4B ldr r3, .L15
369 0006 9A42 cmp r2, r3
370 0008 00D0 beq .L14
371 .LVL21:
372 .L11:
171:Core/Src/stm32h7xx_hal_msp.c **** {
172:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspDeInit 0 */
173:Core/Src/stm32h7xx_hal_msp.c ****
174:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END QUADSPI_MspDeInit 0 */
175:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */
176:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_QSPI_CLK_DISABLE();
177:Core/Src/stm32h7xx_hal_msp.c ****
178:Core/Src/stm32h7xx_hal_msp.c **** /**QUADSPI GPIO Configuration
179:Core/Src/stm32h7xx_hal_msp.c **** PE2 ------> QUADSPI_BK1_IO2
180:Core/Src/stm32h7xx_hal_msp.c **** PB2 ------> QUADSPI_CLK
181:Core/Src/stm32h7xx_hal_msp.c **** PD11 ------> QUADSPI_BK1_IO0
182:Core/Src/stm32h7xx_hal_msp.c **** PD12 ------> QUADSPI_BK1_IO1
183:Core/Src/stm32h7xx_hal_msp.c **** PD13 ------> QUADSPI_BK1_IO3
184:Core/Src/stm32h7xx_hal_msp.c **** PB6 ------> QUADSPI_BK1_NCS
185:Core/Src/stm32h7xx_hal_msp.c **** */
186:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2);
187:Core/Src/stm32h7xx_hal_msp.c ****
188:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_2|GPIO_PIN_6);
189:Core/Src/stm32h7xx_hal_msp.c ****
190:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOD, GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13);
191:Core/Src/stm32h7xx_hal_msp.c ****
ARM GAS /tmp/ccYeBZUP.s page 12
192:Core/Src/stm32h7xx_hal_msp.c **** /* QUADSPI interrupt DeInit */
193:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_DisableIRQ(QUADSPI_IRQn);
194:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspDeInit 1 */
195:Core/Src/stm32h7xx_hal_msp.c ****
196:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END QUADSPI_MspDeInit 1 */
197:Core/Src/stm32h7xx_hal_msp.c **** }
198:Core/Src/stm32h7xx_hal_msp.c ****
199:Core/Src/stm32h7xx_hal_msp.c **** }
373 .loc 1 199 1 view .LVU101
374 000a 08BD pop {r3, pc}
375 .LVL22:
376 .L14:
176:Core/Src/stm32h7xx_hal_msp.c ****
377 .loc 1 176 5 is_stmt 1 view .LVU102
378 000c 0C4A ldr r2, .L15+4
379 000e D2F8D430 ldr r3, [r2, #212]
380 0012 23F48043 bic r3, r3, #16384
381 0016 C2F8D430 str r3, [r2, #212]
186:Core/Src/stm32h7xx_hal_msp.c ****
382 .loc 1 186 5 view .LVU103
383 001a 0421 movs r1, #4
384 001c 0948 ldr r0, .L15+8
385 .LVL23:
186:Core/Src/stm32h7xx_hal_msp.c ****
386 .loc 1 186 5 is_stmt 0 view .LVU104
387 001e FFF7FEFF bl HAL_GPIO_DeInit
388 .LVL24:
188:Core/Src/stm32h7xx_hal_msp.c ****
389 .loc 1 188 5 is_stmt 1 view .LVU105
390 0022 4421 movs r1, #68
391 0024 0848 ldr r0, .L15+12
392 0026 FFF7FEFF bl HAL_GPIO_DeInit
393 .LVL25:
190:Core/Src/stm32h7xx_hal_msp.c ****
394 .loc 1 190 5 view .LVU106
395 002a 4FF46051 mov r1, #14336
396 002e 0748 ldr r0, .L15+16
397 0030 FFF7FEFF bl HAL_GPIO_DeInit
398 .LVL26:
193:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN QUADSPI_MspDeInit 1 */
399 .loc 1 193 5 view .LVU107
400 0034 5C20 movs r0, #92
401 0036 FFF7FEFF bl HAL_NVIC_DisableIRQ
402 .LVL27:
403 .loc 1 199 1 is_stmt 0 view .LVU108
404 003a E6E7 b .L11
405 .L16:
406 .align 2
407 .L15:
408 003c 00500052 .word 1375752192
409 0040 00440258 .word 1476543488
410 0044 00100258 .word 1476530176
411 0048 00040258 .word 1476527104
412 004c 000C0258 .word 1476529152
413 .cfi_endproc
414 .LFE143:
416 .section .text.HAL_UART_MspInit,"ax",%progbits
ARM GAS /tmp/ccYeBZUP.s page 13
417 .align 1
418 .global HAL_UART_MspInit
419 .syntax unified
420 .thumb
421 .thumb_func
422 .fpu fpv5-d16
424 HAL_UART_MspInit:
425 .LVL28:
426 .LFB144:
200:Core/Src/stm32h7xx_hal_msp.c ****
201:Core/Src/stm32h7xx_hal_msp.c **** /**
202:Core/Src/stm32h7xx_hal_msp.c **** * @brief UART MSP Initialization
203:Core/Src/stm32h7xx_hal_msp.c **** * This function configures the hardware resources used in this example
204:Core/Src/stm32h7xx_hal_msp.c **** * @param huart: UART handle pointer
205:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
206:Core/Src/stm32h7xx_hal_msp.c **** */
207:Core/Src/stm32h7xx_hal_msp.c **** void HAL_UART_MspInit(UART_HandleTypeDef* huart)
208:Core/Src/stm32h7xx_hal_msp.c **** {
427 .loc 1 208 1 is_stmt 1 view -0
428 .cfi_startproc
429 @ args = 0, pretend = 0, frame = 32
430 @ frame_needed = 0, uses_anonymous_args = 0
431 .loc 1 208 1 is_stmt 0 view .LVU110
432 0000 00B5 push {lr}
433 .LCFI8:
434 .cfi_def_cfa_offset 4
435 .cfi_offset 14, -4
436 0002 89B0 sub sp, sp, #36
437 .LCFI9:
438 .cfi_def_cfa_offset 40
209:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
439 .loc 1 209 3 is_stmt 1 view .LVU111
440 .loc 1 209 20 is_stmt 0 view .LVU112
441 0004 0023 movs r3, #0
442 0006 0393 str r3, [sp, #12]
443 0008 0493 str r3, [sp, #16]
444 000a 0593 str r3, [sp, #20]
445 000c 0693 str r3, [sp, #24]
446 000e 0793 str r3, [sp, #28]
210:Core/Src/stm32h7xx_hal_msp.c **** if(huart->Instance==USART1)
447 .loc 1 210 3 is_stmt 1 view .LVU113
448 .loc 1 210 11 is_stmt 0 view .LVU114
449 0010 0268 ldr r2, [r0]
450 .loc 1 210 5 view .LVU115
451 0012 03F18043 add r3, r3, #1073741824
452 0016 03F58833 add r3, r3, #69632
453 001a 9A42 cmp r2, r3
454 001c 02D0 beq .L20
455 .LVL29:
456 .L17:
211:Core/Src/stm32h7xx_hal_msp.c **** {
212:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspInit 0 */
213:Core/Src/stm32h7xx_hal_msp.c ****
214:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END USART1_MspInit 0 */
215:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */
216:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_USART1_CLK_ENABLE();
217:Core/Src/stm32h7xx_hal_msp.c ****
ARM GAS /tmp/ccYeBZUP.s page 14
218:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
219:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration
220:Core/Src/stm32h7xx_hal_msp.c **** PA9 ------> USART1_TX
221:Core/Src/stm32h7xx_hal_msp.c **** PA10 ------> USART1_RX
222:Core/Src/stm32h7xx_hal_msp.c **** */
223:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
224:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
225:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
226:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
227:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
228:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
229:Core/Src/stm32h7xx_hal_msp.c ****
230:Core/Src/stm32h7xx_hal_msp.c **** /* USART1 interrupt Init */
231:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(USART1_IRQn, 1, 0);
232:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(USART1_IRQn);
233:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspInit 1 */
234:Core/Src/stm32h7xx_hal_msp.c ****
235:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END USART1_MspInit 1 */
236:Core/Src/stm32h7xx_hal_msp.c **** }
237:Core/Src/stm32h7xx_hal_msp.c ****
238:Core/Src/stm32h7xx_hal_msp.c **** }
457 .loc 1 238 1 view .LVU116
458 001e 09B0 add sp, sp, #36
459 .LCFI10:
460 .cfi_remember_state
461 .cfi_def_cfa_offset 4
462 @ sp needed
463 0020 5DF804FB ldr pc, [sp], #4
464 .LVL30:
465 .L20:
466 .LCFI11:
467 .cfi_restore_state
216:Core/Src/stm32h7xx_hal_msp.c ****
468 .loc 1 216 5 is_stmt 1 view .LVU117
469 .LBB7:
216:Core/Src/stm32h7xx_hal_msp.c ****
470 .loc 1 216 5 view .LVU118
216:Core/Src/stm32h7xx_hal_msp.c ****
471 .loc 1 216 5 view .LVU119
472 0024 164B ldr r3, .L21
473 0026 D3F8F020 ldr r2, [r3, #240]
474 002a 42F01002 orr r2, r2, #16
475 002e C3F8F020 str r2, [r3, #240]
216:Core/Src/stm32h7xx_hal_msp.c ****
476 .loc 1 216 5 view .LVU120
477 0032 D3F8F020 ldr r2, [r3, #240]
478 0036 02F01002 and r2, r2, #16
479 003a 0192 str r2, [sp, #4]
216:Core/Src/stm32h7xx_hal_msp.c ****
480 .loc 1 216 5 view .LVU121
481 003c 019A ldr r2, [sp, #4]
482 .LBE7:
216:Core/Src/stm32h7xx_hal_msp.c ****
483 .loc 1 216 5 view .LVU122
218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration
484 .loc 1 218 5 view .LVU123
485 .LBB8:
ARM GAS /tmp/ccYeBZUP.s page 15
218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration
486 .loc 1 218 5 view .LVU124
218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration
487 .loc 1 218 5 view .LVU125
488 003e D3F8E020 ldr r2, [r3, #224]
489 0042 42F00102 orr r2, r2, #1
490 0046 C3F8E020 str r2, [r3, #224]
218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration
491 .loc 1 218 5 view .LVU126
492 004a D3F8E030 ldr r3, [r3, #224]
493 004e 03F00103 and r3, r3, #1
494 0052 0293 str r3, [sp, #8]
218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration
495 .loc 1 218 5 view .LVU127
496 0054 029B ldr r3, [sp, #8]
497 .LBE8:
218:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration
498 .loc 1 218 5 view .LVU128
223:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
499 .loc 1 223 5 view .LVU129
223:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
500 .loc 1 223 25 is_stmt 0 view .LVU130
501 0056 4FF4C063 mov r3, #1536
502 005a 0393 str r3, [sp, #12]
224:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
503 .loc 1 224 5 is_stmt 1 view .LVU131
224:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
504 .loc 1 224 26 is_stmt 0 view .LVU132
505 005c 0223 movs r3, #2
506 005e 0493 str r3, [sp, #16]
225:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
507 .loc 1 225 5 is_stmt 1 view .LVU133
226:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
508 .loc 1 226 5 view .LVU134
227:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
509 .loc 1 227 5 view .LVU135
227:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
510 .loc 1 227 31 is_stmt 0 view .LVU136
511 0060 0723 movs r3, #7
512 0062 0793 str r3, [sp, #28]
228:Core/Src/stm32h7xx_hal_msp.c ****
513 .loc 1 228 5 is_stmt 1 view .LVU137
514 0064 03A9 add r1, sp, #12
515 0066 0748 ldr r0, .L21+4
516 .LVL31:
228:Core/Src/stm32h7xx_hal_msp.c ****
517 .loc 1 228 5 is_stmt 0 view .LVU138
518 0068 FFF7FEFF bl HAL_GPIO_Init
519 .LVL32:
231:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(USART1_IRQn);
520 .loc 1 231 5 is_stmt 1 view .LVU139
521 006c 0022 movs r2, #0
522 006e 0121 movs r1, #1
523 0070 2520 movs r0, #37
524 0072 FFF7FEFF bl HAL_NVIC_SetPriority
525 .LVL33:
232:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspInit 1 */
ARM GAS /tmp/ccYeBZUP.s page 16
526 .loc 1 232 5 view .LVU140
527 0076 2520 movs r0, #37
528 0078 FFF7FEFF bl HAL_NVIC_EnableIRQ
529 .LVL34:
530 .loc 1 238 1 is_stmt 0 view .LVU141
531 007c CFE7 b .L17
532 .L22:
533 007e 00BF .align 2
534 .L21:
535 0080 00440258 .word 1476543488
536 0084 00000258 .word 1476526080
537 .cfi_endproc
538 .LFE144:
540 .section .text.HAL_UART_MspDeInit,"ax",%progbits
541 .align 1
542 .global HAL_UART_MspDeInit
543 .syntax unified
544 .thumb
545 .thumb_func
546 .fpu fpv5-d16
548 HAL_UART_MspDeInit:
549 .LVL35:
550 .LFB145:
239:Core/Src/stm32h7xx_hal_msp.c ****
240:Core/Src/stm32h7xx_hal_msp.c **** /**
241:Core/Src/stm32h7xx_hal_msp.c **** * @brief UART MSP De-Initialization
242:Core/Src/stm32h7xx_hal_msp.c **** * This function freeze the hardware resources used in this example
243:Core/Src/stm32h7xx_hal_msp.c **** * @param huart: UART handle pointer
244:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
245:Core/Src/stm32h7xx_hal_msp.c **** */
246:Core/Src/stm32h7xx_hal_msp.c **** void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
247:Core/Src/stm32h7xx_hal_msp.c **** {
551 .loc 1 247 1 is_stmt 1 view -0
552 .cfi_startproc
553 @ args = 0, pretend = 0, frame = 0
554 @ frame_needed = 0, uses_anonymous_args = 0
555 .loc 1 247 1 is_stmt 0 view .LVU143
556 0000 08B5 push {r3, lr}
557 .LCFI12:
558 .cfi_def_cfa_offset 8
559 .cfi_offset 3, -8
560 .cfi_offset 14, -4
248:Core/Src/stm32h7xx_hal_msp.c **** if(huart->Instance==USART1)
561 .loc 1 248 3 is_stmt 1 view .LVU144
562 .loc 1 248 11 is_stmt 0 view .LVU145
563 0002 0268 ldr r2, [r0]
564 .loc 1 248 5 view .LVU146
565 0004 094B ldr r3, .L27
566 0006 9A42 cmp r2, r3
567 0008 00D0 beq .L26
568 .LVL36:
569 .L23:
249:Core/Src/stm32h7xx_hal_msp.c **** {
250:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspDeInit 0 */
251:Core/Src/stm32h7xx_hal_msp.c ****
252:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END USART1_MspDeInit 0 */
253:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */
ARM GAS /tmp/ccYeBZUP.s page 17
254:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_USART1_CLK_DISABLE();
255:Core/Src/stm32h7xx_hal_msp.c ****
256:Core/Src/stm32h7xx_hal_msp.c **** /**USART1 GPIO Configuration
257:Core/Src/stm32h7xx_hal_msp.c **** PA9 ------> USART1_TX
258:Core/Src/stm32h7xx_hal_msp.c **** PA10 ------> USART1_RX
259:Core/Src/stm32h7xx_hal_msp.c **** */
260:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
261:Core/Src/stm32h7xx_hal_msp.c ****
262:Core/Src/stm32h7xx_hal_msp.c **** /* USART1 interrupt DeInit */
263:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_DisableIRQ(USART1_IRQn);
264:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspDeInit 1 */
265:Core/Src/stm32h7xx_hal_msp.c ****
266:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END USART1_MspDeInit 1 */
267:Core/Src/stm32h7xx_hal_msp.c **** }
268:Core/Src/stm32h7xx_hal_msp.c ****
269:Core/Src/stm32h7xx_hal_msp.c **** }
570 .loc 1 269 1 view .LVU147
571 000a 08BD pop {r3, pc}
572 .LVL37:
573 .L26:
254:Core/Src/stm32h7xx_hal_msp.c ****
574 .loc 1 254 5 is_stmt 1 view .LVU148
575 000c 084A ldr r2, .L27+4
576 000e D2F8F030 ldr r3, [r2, #240]
577 0012 23F01003 bic r3, r3, #16
578 0016 C2F8F030 str r3, [r2, #240]
260:Core/Src/stm32h7xx_hal_msp.c ****
579 .loc 1 260 5 view .LVU149
580 001a 4FF4C061 mov r1, #1536
581 001e 0548 ldr r0, .L27+8
582 .LVL38:
260:Core/Src/stm32h7xx_hal_msp.c ****
583 .loc 1 260 5 is_stmt 0 view .LVU150
584 0020 FFF7FEFF bl HAL_GPIO_DeInit
585 .LVL39:
263:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN USART1_MspDeInit 1 */
586 .loc 1 263 5 is_stmt 1 view .LVU151
587 0024 2520 movs r0, #37
588 0026 FFF7FEFF bl HAL_NVIC_DisableIRQ
589 .LVL40:
590 .loc 1 269 1 is_stmt 0 view .LVU152
591 002a EEE7 b .L23
592 .L28:
593 .align 2
594 .L27:
595 002c 00100140 .word 1073811456
596 0030 00440258 .word 1476543488
597 0034 00000258 .word 1476526080
598 .cfi_endproc
599 .LFE145:
601 .text
602 .Letext0:
603 .file 2 "/usr/arm-none-eabi/include/machine/_default_types.h"
604 .file 3 "/usr/arm-none-eabi/include/sys/_stdint.h"
605 .file 4 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h"
606 .file 5 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h"
607 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h"
ARM GAS /tmp/ccYeBZUP.s page 18
608 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h"
609 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h"
610 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h"
611 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h"
612 .file 11 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h"
ARM GAS /tmp/ccYeBZUP.s page 19
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32h7xx_hal_msp.c
/tmp/ccYeBZUP.s:17 .text.HAL_MspInit:0000000000000000 $t
/tmp/ccYeBZUP.s:25 .text.HAL_MspInit:0000000000000000 HAL_MspInit
/tmp/ccYeBZUP.s:114 .text.HAL_MspInit:0000000000000074 $d
/tmp/ccYeBZUP.s:119 .text.HAL_QSPI_MspInit:0000000000000000 $t
/tmp/ccYeBZUP.s:126 .text.HAL_QSPI_MspInit:0000000000000000 HAL_QSPI_MspInit
/tmp/ccYeBZUP.s:335 .text.HAL_QSPI_MspInit:00000000000000e8 $d
/tmp/ccYeBZUP.s:344 .text.HAL_QSPI_MspDeInit:0000000000000000 $t
/tmp/ccYeBZUP.s:351 .text.HAL_QSPI_MspDeInit:0000000000000000 HAL_QSPI_MspDeInit
/tmp/ccYeBZUP.s:408 .text.HAL_QSPI_MspDeInit:000000000000003c $d
/tmp/ccYeBZUP.s:417 .text.HAL_UART_MspInit:0000000000000000 $t
/tmp/ccYeBZUP.s:424 .text.HAL_UART_MspInit:0000000000000000 HAL_UART_MspInit
/tmp/ccYeBZUP.s:535 .text.HAL_UART_MspInit:0000000000000080 $d
/tmp/ccYeBZUP.s:541 .text.HAL_UART_MspDeInit:0000000000000000 $t
/tmp/ccYeBZUP.s:548 .text.HAL_UART_MspDeInit:0000000000000000 HAL_UART_MspDeInit
/tmp/ccYeBZUP.s:595 .text.HAL_UART_MspDeInit:000000000000002c $d
UNDEFINED SYMBOLS
HAL_NVIC_SetPriority
HAL_NVIC_EnableIRQ
HAL_GPIO_Init
HAL_GPIO_DeInit
HAL_NVIC_DisableIRQ
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