Fixed LVGL.
continuous-integration/drone/push Build is passing
Details
continuous-integration/drone/push Build is passing
Details
This commit is contained in:
parent
61fbc21f8f
commit
3ab650c6aa
GPG Key ID:
17F01E106F9F5E0A
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@ -64,7 +64,7 @@
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#define configTICK_RATE_HZ ((TickType_t)1000)
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#define configMAX_PRIORITIES ( 56 )
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#define configMINIMAL_STACK_SIZE ((uint16_t)128)
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#define configTOTAL_HEAP_SIZE ((size_t)81920)
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#define configTOTAL_HEAP_SIZE ((size_t)262144)
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#define configMAX_TASK_NAME_LEN ( 16 )
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#define configUSE_TRACE_FACILITY 1
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#define configUSE_16_BIT_TICKS 0
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@ -48,7 +48,7 @@
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/* Default display refresh period.
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* Can be changed in the display driver (`lv_disp_drv_t`).*/
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#define LV_DISP_DEF_REFR_PERIOD 30 /*[ms]*/
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#define LV_DISP_DEF_REFR_PERIOD 60000 /*[ms]*/
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/* Dot Per Inch: used to initialize default sizes.
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* E.g. a button with width = LV_DPI / 2 -> half inch wide
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@ -355,9 +355,9 @@ static void MX_SPI2_Init(void)
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hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
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hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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hspi2.Init.CRCPolynomial = 0x0;
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hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
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hspi2.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
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hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
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hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_16DATA;
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hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
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hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
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hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
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hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
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@ -379,7 +379,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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/* USART1 interrupt Init */
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HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
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HAL_NVIC_SetPriority(USART1_IRQn, 6, 0);
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HAL_NVIC_EnableIRQ(USART1_IRQn);
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/* USER CODE BEGIN USART1_MspInit 1 */
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@ -8,7 +8,6 @@ extern osSemaphoreId_t g_epd_busy_semphr;
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extern osSemaphoreId_t g_spi2_semphr;
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void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
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// FIXME
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if(GPIO_Pin == SPI2_BUSY_Pin) {
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if(osKernelGetState() == osKernelRunning) { // Kernel has started, release semaphore.
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osSemaphoreRelease(g_epd_busy_semphr);
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@ -7,18 +7,8 @@ void _epd_set_px_cb(lv_disp_drv_t *disp_drv, uint8_t *buf,
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uint16_t byte_index;
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uint8_t bit_index;
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if(epd->direction == DEPG0213_HORIZONTAL) {
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byte_index = x + (y / 8) * buf_w;
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bit_index = y & 7;
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}
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else if(epd->direction == DEPG0213_HORIZONTAL_INVERSE) {
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byte_index = x + (y / 8) * buf_w;
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bit_index = 7 - (y & 7);
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}
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else {
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byte_index = y + (x / 8) * buf_w;
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bit_index = x & 7;
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}
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byte_index = x + (y / 8) * buf_w;
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bit_index = 7 - (y & 7);
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if(color.full) {
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buf[byte_index] |= 1U << bit_index;
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@ -35,7 +25,7 @@ void _epd_rounder_cb(lv_disp_drv_t *disp_drv, lv_area_t *area) {
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area->y1 = (area->y1 / 8) * 8;
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area->y2 = (area->y2 / 8) * 8 + 7;
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}
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else {
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else { // Vertical mode
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area->x1 = (area->x1 / 8) * 8;
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area->x2 = (area->x2 / 8) * 8 + 7;
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}
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@ -44,7 +34,7 @@ void _epd_rounder_cb(lv_disp_drv_t *disp_drv, lv_area_t *area) {
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void _epd_flush_cb(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p) {
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depg0213_epd_t *epd = disp_drv->user_data;
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if(depg0213_epd_load(epd, color_p, color_p, area->x1, area->x2, area->y1, area->y2) != DEPG0213_OK) {
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if(depg0213_epd_load(epd, color_p, NULL, area->x1, area->x2, area->y1, area->y2) != DEPG0213_OK) {
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return;
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}
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@ -1,3 +1,5 @@
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#include <stdio.h>
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#include "cmsis_os2.h"
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#include "lvgl.h"
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@ -16,7 +18,7 @@ void user_task_hello(void *arguments);
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uint8_t _user_tasks_init_epd(void);
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uint8_t _user_tasks_init_lvgl(void);
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#define FRAME_BUFFER_SIZE (212 * 10 / 8)
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#define FRAME_BUFFER_SIZE (212 * 10)
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// Globals
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depg0213_epd_t g_epd = {
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@ -40,14 +42,14 @@ osSemaphoreId_t g_lvgl_semphr;
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osThreadId_t g_flush_epd_task_handle;
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const osThreadAttr_t g_flush_epd_task_attributes = {
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.name = "flushEPD",
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.priority = (osPriority_t) osPriorityNormal,
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.priority = (osPriority_t) osPriorityBelowNormal,
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.stack_size = 2048 * 4
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};
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osThreadId_t g_lvgl_tick_handle;
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const osThreadAttr_t g_lvgl_tick_attributes = {
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.name = "lvglTICK",
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.priority = (osPriority_t) osPriorityNormal,
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.priority = (osPriority_t) osPriorityBelowNormal,
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.stack_size = 1024 * 4
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};
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@ -55,7 +57,7 @@ osThreadId_t g_task_hello_handle;
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const osThreadAttr_t g_task_hello_attributes = {
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.name = "HELLO",
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.priority = (osPriority_t) osPriorityNormal,
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.stack_size = 2048 * 4
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.stack_size = 1024 * 4
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};
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void user_tasks_initialize(void) {
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@ -65,31 +67,30 @@ void user_tasks_initialize(void) {
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if(_user_tasks_init_epd()) return;
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if(_user_tasks_init_lvgl()) return;
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uint8_t bw_1[512];
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uint8_t rd_1[512];
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memset(bw_1, 0xFF, 512);
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memset(rd_1, 0xFF, 512);
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depg0213_epd_window(&g_epd, DEPG0213_HORIZONTAL, 0, 211, 0, 103);
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depg0213_epd_load(&g_epd, bw_1, rd_1, 0, 31, 0, 103);
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depg0213_epd_update(&g_epd);
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HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0);
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HAL_NVIC_SetPriority(SPI2_IRQn, 6, 0);
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//g_flush_epd_task_handle = osThreadNew(user_task_flush_epd, NULL, &g_flush_epd_task_attributes);
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//g_lvgl_tick_handle = osThreadNew(user_task_lvgl_tick, NULL, &g_lvgl_tick_attributes);
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//g_task_hello_handle = osThreadNew(user_task_hello, NULL, &g_task_hello_attributes);
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g_flush_epd_task_handle = osThreadNew(user_task_flush_epd, NULL, &g_flush_epd_task_attributes);
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g_lvgl_tick_handle = osThreadNew(user_task_lvgl_tick, NULL, &g_lvgl_tick_attributes);
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g_task_hello_handle = osThreadNew(user_task_hello, NULL, &g_task_hello_attributes);
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}
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void user_task_hello(void *arguments) {
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lv_obj_t *hello_label;
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char buf[32];
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osSemaphoreAcquire(g_lvgl_semphr, osWaitForever);
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lv_obj_t *hello_label = lv_label_create(lv_scr_act(), NULL);
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hello_label = lv_label_create(lv_scr_act(), NULL);
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lv_label_set_align(hello_label, LV_LABEL_ALIGN_CENTER);
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lv_label_set_text(hello_label, "Hello LVGL!!");
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osSemaphoreRelease(g_lvgl_semphr);
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for(;;) {
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osDelay(10000);
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snprintf(buf, 32, "LVGL@%ld", osKernelGetTickCount());
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osSemaphoreAcquire(g_lvgl_semphr, osWaitForever);
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lv_label_set_align(hello_label, LV_LABEL_ALIGN_CENTER);
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lv_label_set_text(hello_label, buf);
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osSemaphoreRelease(g_lvgl_semphr);
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}
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}
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@ -123,9 +124,21 @@ uint8_t _user_tasks_init_epd(void) {
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ret = depg0213_epd_init(&g_epd);
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if(ret != DEPG0213_OK) return -2;
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ret = depg0213_epd_window(&g_epd, DEPG0213_HORIZONTAL_INVERSE, 0, 211, 0, 103);
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ret = depg0213_epd_window(&g_epd, DEPG0213_HORIZONTAL, 0, 211, 0, 103);
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if(ret != DEPG0213_OK) return -3;
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uint8_t buffer = 0x00;
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for(uint16_t i = 0; i < 212; i++) {
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for(uint16_t j = 0; j < 13; j++) {
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depg0213_epd_load(&g_epd, NULL, &buffer, i, i, j * 8, j * 8 + 7);
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}
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}
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buffer = 0xFF;
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for(uint16_t i = 0; i < 212; i++) {
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for(uint16_t j = 0; j < 13; j++) {
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depg0213_epd_load(&g_epd, &buffer, NULL, i, i, j * 8, j * 8 + 7);
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}
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}
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ret = depg0213_epd_deepsleep(&g_epd);
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if(ret != DEPG0213_OK) return -6;
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@ -137,10 +150,10 @@ uint8_t _user_tasks_init_lvgl(void) {
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if(g_lvgl_semphr == NULL) return -1;
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lv_init();
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lv_disp_buf_init(&g_disp_buf, g_epd_frame, NULL, FRAME_BUFFER_SIZE);
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lv_disp_drv_t disp_drv;
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/*
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lv_disp_drv_init(&disp_drv);
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disp_drv.buffer = &g_disp_buf;
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disp_drv.set_px_cb = _epd_set_px_cb;
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@ -155,7 +168,6 @@ uint8_t _user_tasks_init_lvgl(void) {
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//
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}
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}
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*/
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return 0;
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}
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@ -1 +1 @@
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Subproject commit 4c31481910fbecf61528f1857db5a76efbc4749c
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Subproject commit 77b9c803d81d5b7a5fd9cf2bcb13f4df1a545dc7
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2
Makefile
2
Makefile
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@ -1,5 +1,5 @@
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##########################################################################################################################
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# File automatically-generated by tool: [projectgenerator] version: [3.11.2] date: [Sun Jan 17 20:33:52 CST 2021]
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# File automatically-generated by tool: [projectgenerator] version: [3.11.2] date: [Sun Jan 17 23:36:54 CST 2021]
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##########################################################################################################################
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# ------------------------------------------------
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@ -1,7 +1,7 @@
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#MicroXplorer Configuration settings - do not modify
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Mcu.Family=STM32H7
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NVIC.FLASH_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
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RCC.DIVQ2Freq_Value=16125000
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RCC.DIVQ2Freq_Value=100000000
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ProjectManager.MainLocation=Core/Src
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Dma.SPI2_TX.0.MemInc=DMA_MINC_ENABLE
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SPI2.VirtualNSS=VM_NSSHARD
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@ -27,7 +27,7 @@ RCC.RTCFreq_Value=32768
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PC9.Locked=true
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CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_REGION_FULL_ACCESS
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RCC.CpuClockFreq_Value=240000000
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RCC.VCO2OutputFreq_Value=32250000
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RCC.VCO2OutputFreq_Value=200000000
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Dma.SPI2_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
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USART1.IPParameters=VirtualMode-Asynchronous
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PD8.GPIO_PuPd=GPIO_PULLUP
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@ -98,6 +98,7 @@ NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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PB2.Signal=QUADSPI_CLK
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CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_REGION_SIZE_128KB
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Mcu.IP10=USART1
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RCC.DIVM2=4
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NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true
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RCC.DIVM1=4
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RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
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@ -120,17 +121,17 @@ PA14\ (JTCK/SWCLK).Mode=Serial_Wire
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NVIC.SPI2_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
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NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
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Dma.SPI2_TX.0.RequestNumber=1
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RCC.DIVR2Freq_Value=16125000
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RCC.DIVR2Freq_Value=100000000
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CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_INSTRUCTION_ACCESS_ENABLE
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Dma.RequestsNb=1
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ProjectManager.HalAssertFull=false
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FREERTOS.configTOTAL_HEAP_SIZE=81920
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RCC.DIVP2Freq_Value=16125000
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FREERTOS.configTOTAL_HEAP_SIZE=262144
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RCC.DIVP2Freq_Value=25000000
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ProjectManager.ProjectName=STM32H750_EPD
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RCC.APB3Freq_Value=120000000
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RCC.MCO2PinFreq_Value=240000000
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Mcu.Package=LQFP100
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SPI2.FifoThreshold=SPI_FIFO_THRESHOLD_16DATA
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SPI2.FifoThreshold=SPI_FIFO_THRESHOLD_01DATA
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PB12.Mode=NSS_Signal_Hard_Output
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NVIC.TimeBase=TIM7_IRQn
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SPI2.Mode=SPI_MODE_MASTER
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@ -155,7 +156,7 @@ RCC.LPUART1Freq_Value=120000000
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NVIC.DMA1_Stream0_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true
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SPI2.Direction=SPI_DIRECTION_2LINES_TXONLY
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PB13.Mode=TX_Only_Simplex_Unidirect_Master
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NVIC.USART1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
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NVIC.USART1_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
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Dma.Request0=SPI2_TX
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PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
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NVIC.TIM7_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
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@ -191,9 +192,10 @@ CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS
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RCC.SWPMI1Freq_Value=120000000
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CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_CACHEABLE
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RCC.SAI4BFreq_Value=60000000
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SPI2.NSSPMode=SPI_NSS_PULSE_ENABLE
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SPI2.NSSPMode=SPI_NSS_PULSE_DISABLE
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PC10.Mode=Single Bank 1
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ProjectManager.DefaultFWLocation=true
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RCC.DIVP2=8
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PD9.Signal=GPXTI9
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ProjectManager.DeletePrevious=true
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PB14.Locked=true
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@ -220,6 +222,7 @@ CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_TEX_LE
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RCC.VCO1OutputFreq_Value=480000000
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PA9.Signal=USART1_TX
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RCC.AXIClockFreq_Value=120000000
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RCC.DIVN2=100
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CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_CACHEABLE
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RCC.DIVN1=240
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CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
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@ -248,12 +251,12 @@ RCC.FDCANFreq_Value=60000000
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Dma.SPI2_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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RCC.RNGFreq_Value=48000000
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CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_SHAREABLE
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RCC.ADCFreq_Value=16125000
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RCC.ADCFreq_Value=25000000
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CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_FULL_ACCESS
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NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
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NVIC.HSEM1_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
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ProjectManager.FreePins=false
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RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPICLockSelection,QSPIFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
|
||||
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVN1,DIVN2,DIVP1Freq_Value,DIVP2,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPICLockSelection,QSPIFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
|
||||
ProjectManager.AskForMigrate=true
|
||||
Mcu.Name=STM32H750VBTx
|
||||
RCC.LPTIM2Freq_Value=120000000
|
||||
|
|
@ -315,7 +318,7 @@ CORTEX_M7.CPU_DCache=Enabled
|
|||
RCC.HCLK3ClockFreq_Value=120000000
|
||||
PB12.GPIO_PuPd=GPIO_PULLUP
|
||||
Dma.SPI2_TX.0.Direction=DMA_MEMORY_TO_PERIPH
|
||||
RCC.VCOInput2Freq_Value=250000
|
||||
RCC.VCOInput2Freq_Value=2000000
|
||||
PD9.Locked=true
|
||||
RCC.APB1Freq_Value=120000000
|
||||
PD8.PinState=GPIO_PIN_SET
|
||||
|
|
|
|||
Loading…
Reference in New Issue