LVGL testing, custom OpenOCD configuration
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@ -20,8 +20,8 @@
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*====================*/
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/* Maximal horizontal and vertical resolution to support by the library.*/
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#define LV_HOR_RES_MAX (104)
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#define LV_VER_RES_MAX (212)
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#define LV_HOR_RES_MAX (212)
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#define LV_VER_RES_MAX (104)
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/* Color depth:
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* - 1: 1 byte per pixel
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@ -216,7 +216,7 @@ typedef void * lv_fs_drv_user_data_t;
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#endif
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/*1: Add a `user_data` to drivers and objects*/
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#define LV_USE_USER_DATA 0
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#define LV_USE_USER_DATA 1
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/*1: Show CPU usage and FPS count in the right bottom corner*/
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#define LV_USE_PERF_MONITOR 0
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@ -59,6 +59,7 @@ void RCC_IRQHandler(void);
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void DMA1_Stream0_IRQHandler(void);
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void EXTI9_5_IRQHandler(void);
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void SPI2_IRQHandler(void);
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void USART1_IRQHandler(void);
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void TIM7_IRQHandler(void);
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void FPU_IRQHandler(void);
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void QUADSPI_IRQHandler(void);
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@ -0,0 +1,14 @@
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#ifndef __USER_LVGL_DISP_H
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#define __USER_LVGL_DISP_H
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#include "lvgl.h"
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#include "depg0213_epd.h"
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void _epd_set_px_cb(lv_disp_drv_t *disp_drv, uint8_t *buf,
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lv_coord_t buf_w, lv_coord_t x, lv_coord_t y, lv_color_t color, lv_opa_t opa);
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void _epd_rounder_cb(lv_disp_drv_t *disp_drv, lv_area_t *area);
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void _epd_flush_cb(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p);
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#endif
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@ -567,12 +567,12 @@ void MPU_Config(void)
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MPU_InitStruct.BaseAddress = 0x20000000;
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MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
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MPU_InitStruct.SubRegionDisable = 0x0;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
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MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
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MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
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MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
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MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
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MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
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MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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/** Initializes and configures the Region and the memory to be protected
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@ -591,7 +591,7 @@ void MPU_Config(void)
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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/* Enables the MPU */
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HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
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HAL_MPU_Enable(MPU_HFNMI_PRIVDEF_NONE);
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}
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/**
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@ -378,6 +378,9 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
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GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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/* USART1 interrupt Init */
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HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(USART1_IRQn);
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/* USER CODE BEGIN USART1_MspInit 1 */
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/* USER CODE END USART1_MspInit 1 */
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@ -407,6 +410,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
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*/
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HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
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/* USART1 interrupt DeInit */
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HAL_NVIC_DisableIRQ(USART1_IRQn);
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/* USER CODE BEGIN USART1_MspDeInit 1 */
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/* USER CODE END USART1_MspDeInit 1 */
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@ -59,6 +59,7 @@
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extern QSPI_HandleTypeDef hqspi;
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extern DMA_HandleTypeDef hdma_spi2_tx;
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extern SPI_HandleTypeDef hspi2;
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extern UART_HandleTypeDef huart1;
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extern TIM_HandleTypeDef htim7;
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/* USER CODE BEGIN EV */
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@ -247,6 +248,20 @@ void SPI2_IRQHandler(void)
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/* USER CODE END SPI2_IRQn 1 */
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}
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/**
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* @brief This function handles USART1 global interrupt.
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*/
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void USART1_IRQHandler(void)
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{
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/* USER CODE BEGIN USART1_IRQn 0 */
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/* USER CODE END USART1_IRQn 0 */
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HAL_UART_IRQHandler(&huart1);
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/* USER CODE BEGIN USART1_IRQn 1 */
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/* USER CODE END USART1_IRQn 1 */
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}
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/**
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* @brief This function handles TIM7 global interrupt.
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*/
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@ -0,0 +1,56 @@
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#include "user_lvgl_disp.h"
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void _epd_set_px_cb(lv_disp_drv_t *disp_drv, uint8_t *buf,
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lv_coord_t buf_w, lv_coord_t x, lv_coord_t y, lv_color_t color, lv_opa_t opa) {
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depg0213_epd_t *epd = disp_drv->user_data;
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uint16_t byte_index;
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uint8_t bit_index;
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if(epd->direction == DEPG0213_HORIZONTAL) {
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byte_index = x + (y / 8) * buf_w;
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bit_index = y & 7;
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}
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else if(epd->direction == DEPG0213_HORIZONTAL_INVERSE) {
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byte_index = x + (y / 8) * buf_w;
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bit_index = 7 - (y & 7);
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}
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else {
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byte_index = y + (x / 8) * buf_w;
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bit_index = x & 7;
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}
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if(color.full) {
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buf[byte_index] |= 1U << bit_index;
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}
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else {
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buf[byte_index] &= ~(1U << bit_index);
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}
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}
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void _epd_rounder_cb(lv_disp_drv_t *disp_drv, lv_area_t *area) {
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depg0213_epd_t *epd = disp_drv->user_data;
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if(epd->direction == DEPG0213_HORIZONTAL || epd->direction == DEPG0213_HORIZONTAL_INVERSE) {
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area->y1 = (area->y1 / 8) * 8;
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area->y2 = (area->y2 / 8) * 8 + 7;
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}
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else {
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area->x1 = (area->x1 / 8) * 8;
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area->x2 = (area->x2 / 8) * 8 + 7;
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}
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}
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void _epd_flush_cb(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p) {
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depg0213_epd_t *epd = disp_drv->user_data;
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if(depg0213_epd_load(epd, color_p, color_p, area->x1, area->x2, area->y1, area->y2) != DEPG0213_OK) {
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return;
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}
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if(lv_disp_flush_is_last(disp_drv)) {
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if(depg0213_epd_update(epd) != DEPG0213_OK) return;
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}
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lv_disp_flush_ready(disp_drv);
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}
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@ -3,14 +3,20 @@
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#include "lvgl.h"
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#include "user_epd_impl.h"
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#include "user_lvgl_disp.h"
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// Defined in main.c
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extern SPI_HandleTypeDef hspi2;
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// Private function prototypes
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void user_task_flush_epd(void *arguments);
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void user_task_lvgl_tick(void *arguments);
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void user_task_hello(void *arguments);
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uint8_t _user_tasks_init_epd(void);
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void _user_tasks_init_lvgl(void);
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uint8_t _user_tasks_init_lvgl(void);
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#define FRAME_BUFFER_SIZE (212 * 10 / 8)
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// Globals
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depg0213_epd_t g_epd = {
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}
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};
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lv_disp_buf_t g_disp_buf;
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lv_color_t g_epd_frame[FRAME_BUFFER_SIZE];
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lv_disp_t *g_epd_disp;
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osSemaphoreId_t g_epd_busy_semphr;
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osSemaphoreId_t g_spi2_semphr;
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osSemaphoreId_t g_lvgl_semphr;
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osThreadId_t g_flush_epd_task_handle;
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const osThreadAttr_t g_flush_epd_task_attributes = {
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.name = "flushEPD",
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.priority = (osPriority_t) osPriorityNormal,
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.stack_size = 512 * 4
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.stack_size = 2048 * 4
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};
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uint8_t frame_buffer_wb[212 * 104 / 8];
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uint8_t frame_buffer_rd[212 * 104 / 8];
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osThreadId_t g_lvgl_tick_handle;
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const osThreadAttr_t g_lvgl_tick_attributes = {
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.name = "lvglTICK",
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.priority = (osPriority_t) osPriorityNormal,
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.stack_size = 1024 * 4
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};
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osThreadId_t g_task_hello_handle;
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const osThreadAttr_t g_task_hello_attributes = {
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.name = "HELLO",
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.priority = (osPriority_t) osPriorityNormal,
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.stack_size = 2048 * 4
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};
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void user_tasks_initialize(void) {
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HAL_NVIC_SetPriority(EXTI9_5_IRQn, 4, 0);
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HAL_NVIC_SetPriority(SPI2_IRQn, 4, 0);
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if(_user_tasks_init_epd()) return;
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_user_tasks_init_lvgl();
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if(_user_tasks_init_lvgl()) return;
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uint8_t bw_1[512];
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uint8_t rd_1[512];
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memset(bw_1, 0xFF, 512);
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memset(rd_1, 0xFF, 512);
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depg0213_epd_window(&g_epd, DEPG0213_HORIZONTAL, 0, 211, 0, 103);
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depg0213_epd_load(&g_epd, bw_1, rd_1, 0, 31, 0, 103);
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depg0213_epd_update(&g_epd);
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HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0);
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HAL_NVIC_SetPriority(SPI2_IRQn, 6, 0);
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g_flush_epd_task_handle = osThreadNew(user_task_flush_epd, NULL, &g_flush_epd_task_attributes);
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//g_flush_epd_task_handle = osThreadNew(user_task_flush_epd, NULL, &g_flush_epd_task_attributes);
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//g_lvgl_tick_handle = osThreadNew(user_task_lvgl_tick, NULL, &g_lvgl_tick_attributes);
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//g_task_hello_handle = osThreadNew(user_task_hello, NULL, &g_task_hello_attributes);
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}
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void user_task_hello(void *arguments) {
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osSemaphoreAcquire(g_lvgl_semphr, osWaitForever);
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lv_obj_t *hello_label = lv_label_create(lv_scr_act(), NULL);
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lv_label_set_align(hello_label, LV_LABEL_ALIGN_CENTER);
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lv_label_set_text(hello_label, "Hello LVGL!!");
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osSemaphoreRelease(g_lvgl_semphr);
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for(;;) {
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osDelay(10000);
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}
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}
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void user_task_flush_epd(void *arguments) {
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for(;;) {
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memset(frame_buffer_wb, 0xFF, 212 * 104 / 8);
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memset(frame_buffer_rd, 0x00, 212 * 104 / 8);
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depg0213_epd_load(&g_epd, frame_buffer_wb, frame_buffer_rd);
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depg0213_epd_deepsleep(&g_epd);
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osDelay(300000);
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osSemaphoreAcquire(g_lvgl_semphr, osWaitForever);
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lv_task_handler();
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osSemaphoreRelease(g_lvgl_semphr);
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osDelay(200);
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}
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}
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void user_task_lvgl_tick(void *arguments) {
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for(;;) {
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osSemaphoreAcquire(g_lvgl_semphr, osWaitForever);
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lv_tick_inc(50);
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osSemaphoreRelease(g_lvgl_semphr);
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osDelay(50);
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}
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}
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@ -71,15 +123,39 @@ uint8_t _user_tasks_init_epd(void) {
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ret = depg0213_epd_init(&g_epd);
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if(ret != DEPG0213_OK) return -2;
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ret = depg0213_epd_direction(&g_epd, DEPG0213_HORIZONTAL_INVERSE);
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ret = depg0213_epd_window(&g_epd, DEPG0213_HORIZONTAL_INVERSE, 0, 211, 0, 103);
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if(ret != DEPG0213_OK) return -3;
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ret = depg0213_epd_deepsleep(&g_epd);
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if(ret != DEPG0213_OK) return -4;
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if(ret != DEPG0213_OK) return -6;
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return 0;
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}
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void _user_tasks_init_lvgl(void) {
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uint8_t _user_tasks_init_lvgl(void) {
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g_lvgl_semphr = osSemaphoreNew(1U, 1U, NULL); // Max: 1, initial 1, attr NULL
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if(g_lvgl_semphr == NULL) return -1;
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lv_init();
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lv_disp_buf_init(&g_disp_buf, g_epd_frame, NULL, FRAME_BUFFER_SIZE);
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lv_disp_drv_t disp_drv;
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/*
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lv_disp_drv_init(&disp_drv);
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disp_drv.buffer = &g_disp_buf;
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disp_drv.set_px_cb = _epd_set_px_cb;
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disp_drv.flush_cb = _epd_flush_cb;
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disp_drv.rounder_cb = _epd_rounder_cb;
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disp_drv.user_data = &g_epd;
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g_epd_disp = lv_disp_drv_register(&disp_drv);
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if(g_epd_disp == NULL) {
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for(;;) {
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//
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}
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}
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*/
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return 0;
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}
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@ -1 +1 @@
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Subproject commit 8abed07c233edb7fd2379eb5cc23d15abb10bcbe
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Subproject commit 4c31481910fbecf61528f1857db5a76efbc4749c
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8
Makefile
8
Makefile
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@ -1,5 +1,5 @@
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##########################################################################################################################
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# File automatically-generated by tool: [projectgenerator] version: [3.11.2] date: [Fri Jan 15 00:23:26 CST 2021]
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# File automatically-generated by tool: [projectgenerator] version: [3.11.2] date: [Sun Jan 17 19:15:28 CST 2021]
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##########################################################################################################################
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# ------------------------------------------------
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@ -42,6 +42,7 @@ Core/Src/stm32h7xx_hal_msp.c \
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Core/Src/user_epd_impl.c \
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Core/Src/user_tasks.c \
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Core/Src/user_irq_handlers.c \
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Core/Src/user_lvgl_disp.c \
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Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \
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Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \
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Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \
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@ -242,7 +243,8 @@ AS_DEFS =
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C_DEFS = \
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-DUSE_HAL_DRIVER \
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-DSTM32H750xx \
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-DLV_CONF_INCLUDE_SIMPLE
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-DLV_CONF_INCLUDE_SIMPLE \
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-DDEPG0213_LUT_OTP=1
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# AS includes
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@ -285,7 +287,7 @@ LDSCRIPT = STM32H750VBTx_FLASH.ld
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# libraries
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LIBS = -lc -lm -lnosys
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LIBDIR =
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LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
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LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections -Wl,--print-memory-usage
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# default action: build all
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all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
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@ -53,7 +53,7 @@
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = 0x20020000; /* end of RAM */
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_estack = 0x24080000; /* end of RAM */
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/* Generate a link error if heap and stack don't fit into RAM */
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
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@ -147,7 +147,7 @@ SECTIONS
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. = ALIGN(4);
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_edata = .; /* define a global symbol at data end */
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} >DTCMRAM AT> FLASH
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} >RAM_D1 AT> FLASH
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/* Uninitialized data section */
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@ -164,7 +164,7 @@ SECTIONS
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. = ALIGN(4);
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_ebss = .; /* define a global symbol at bss end */
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__bss_end__ = _ebss;
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} >DTCMRAM
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} >RAM_D1
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/* User_heap_stack section, used to check that there is enough RAM left */
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._user_heap_stack :
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@ -175,9 +175,7 @@ SECTIONS
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. = . + _Min_Heap_Size;
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. = . + _Min_Stack_Size;
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. = ALIGN(8);
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} >DTCMRAM
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|
||||
} >RAM_D1
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
|
|
|
@ -20,7 +20,7 @@ PC10.Locked=true
|
|||
PC10.Signal=QUADSPI_BK1_IO1
|
||||
PB14.GPIO_Label=SPI2_DC
|
||||
PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_QUADSPI_Init-QUADSPI-false-HAL-true,5-MX_SPI2_Init-SPI2-false-HAL-true,6-MX_RTC_Init-RTC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_QUADSPI_Init-QUADSPI-false-HAL-true,5-MX_SPI2_Init-SPI2-false-HAL-true,6-MX_RTC_Init-RTC-false-HAL-true,7-MX_USART1_UART_Init-USART1-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
|
||||
PD8.Locked=true
|
||||
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
|
||||
RCC.RTCFreq_Value=32768
|
||||
|
@ -43,6 +43,7 @@ RCC.AHB4Freq_Value=120000000
|
|||
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
|
||||
Dma.SPI2_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
|
||||
RCC.VCOInput3Freq_Value=250000
|
||||
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_SHAREABLE
|
||||
RCC.LPTIM1Freq_Value=120000000
|
||||
Mcu.IP4=NVIC
|
||||
Mcu.IP5=QUADSPI
|
||||
|
@ -69,7 +70,7 @@ Mcu.IPNb=11
|
|||
ProjectManager.PreviousToolchain=
|
||||
RCC.SPDIFRXFreq_Value=60000000
|
||||
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_TEX_LEVEL1
|
||||
PD8.GPIOParameters=GPIO_Label,GPIO_ModeDefaultOutputPP,PinState,GPIO_PuPd
|
||||
PD8.GPIOParameters=PinState,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
|
||||
RCC.DIVQ3Freq_Value=16125000
|
||||
Mcu.Pin6=PB2
|
||||
PD8.Signal=GPIO_Output
|
||||
|
@ -105,7 +106,7 @@ ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.8.0
|
|||
MxDb.Version=DB.6.0.10
|
||||
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_CACHEABLE
|
||||
RCC.DIVP1Freq_Value=240000000
|
||||
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_TEX_LEVEL1
|
||||
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_TEX_LEVEL0
|
||||
ProjectManager.BackupPrevious=false
|
||||
RCC.FMCFreq_Value=120000000
|
||||
PC11.GPIO_Label=LED1
|
||||
|
@ -154,6 +155,7 @@ RCC.LPUART1Freq_Value=120000000
|
|||
NVIC.DMA1_Stream0_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true
|
||||
SPI2.Direction=SPI_DIRECTION_2LINES_TXONLY
|
||||
PB13.Mode=TX_Only_Simplex_Unidirect_Master
|
||||
NVIC.USART1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
|
||||
Dma.Request0=SPI2_TX
|
||||
PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
|
||||
NVIC.TIM7_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
|
||||
|
@ -182,9 +184,10 @@ Mcu.PinsNb=24
|
|||
ProjectManager.NoMain=false
|
||||
PC11.Locked=true
|
||||
NVIC.SavedSvcallIrqHandlerGenerated=true
|
||||
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_ACCESS_NOT_SHAREABLE
|
||||
PC11.Signal=GPIO_Output
|
||||
VP_SYS_VS_tim7.Mode=TIM7
|
||||
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_BUFFERABLE
|
||||
CORTEX_M7.IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_ACCESS_NOT_BUFFERABLE
|
||||
RCC.SWPMI1Freq_Value=120000000
|
||||
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_NOT_CACHEABLE
|
||||
RCC.SAI4BFreq_Value=60000000
|
||||
|
@ -204,7 +207,7 @@ PD8.GPIO_Label=SPI2_RES
|
|||
RCC.SPI6Freq_Value=120000000
|
||||
RCC.D1CPREFreq_Value=240000000
|
||||
USART1.VirtualMode-Asynchronous=VM_ASYNC
|
||||
CORTEX_M7.MPU_Control=MPU_PRIVILEGED_DEFAULT
|
||||
CORTEX_M7.MPU_Control=MPU_HFNMI_PRIVDEF_NONE
|
||||
RCC.USART234578Freq_Value=120000000
|
||||
PA9.Mode=Asynchronous
|
||||
RCC.SPI45Freq_Value=120000000
|
||||
|
@ -260,7 +263,7 @@ NVIC.SavedPendsvIrqHandlerGenerated=true
|
|||
CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_FULL_ACCESS
|
||||
ProjectManager.UnderRoot=false
|
||||
CORTEX_M7.IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_ACCESS_CACHEABLE
|
||||
CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region0_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region2_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings,Size-Cortex_Memory_Protection_Unit_Region2_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings,Enable-Cortex_Memory_Protection_Unit_Region3_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings,Size-Cortex_Memory_Protection_Unit_Region3_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings
|
||||
CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region0_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region0_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region0_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region0_Settings,Enable-Cortex_Memory_Protection_Unit_Region1_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings,Size-Cortex_Memory_Protection_Unit_Region1_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region1_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region1_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region1_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings,Enable-Cortex_Memory_Protection_Unit_Region2_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings,Size-Cortex_Memory_Protection_Unit_Region2_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region2_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region2_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region2_Settings,Enable-Cortex_Memory_Protection_Unit_Region3_Settings,BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings,Size-Cortex_Memory_Protection_Unit_Region3_Settings,TypeExtField-Cortex_Memory_Protection_Unit_Region3_Settings,AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region3_Settings,IsCacheable-Cortex_Memory_Protection_Unit_Region3_Settings,IsBufferable-Cortex_Memory_Protection_Unit_Region3_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region2_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region3_Settings
|
||||
Mcu.IP8=SPI2
|
||||
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
|
||||
Mcu.IP9=SYS
|
||||
|
|
|
@ -0,0 +1,7 @@
|
|||
source /home/imi415/Documents/Conf/OpenOCD/interface/ft232-swd.cfg
|
||||
|
||||
source [find target/stm32h7x.cfg]
|
||||
|
||||
reset_config none
|
||||
cortex_m reset_config sysresetreq
|
||||
gdb_breakpoint_override hw
|
Loading…
Reference in New Issue