Added printf, enabled UART, added SDRAM tests.

.drone.yml

@@ -0,0 +1,20 @@
+kind: pipeline
+type: kubernetes
+name: default
+
+steps:
+- name: submodules
+  image: alpine/git
+  commands:
+  - git submodule update --recursive --init
+
+- name: build
+  image: registry.aws.minori.work/imi415/arm-none-toolchain:latest
+  commands:
+    - mkdir build
+    - cd build
+    - cmake -DCMAKE_TOOLCHAIN_FILE=arm-none-eabi.cmake ..
+    - make
+
+image_pull_secrets:
+- pull-secret

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "Middlewares/Third_Party/printf"]
+	path = Middlewares/Third_Party/printf
+	url = https://github.com/mpaland/printf.git

CMakeLists.txt

@@ -23,6 +23,10 @@ set(C_SOURCES
     "Core/Src/stm32h7xx_it.c"
     "Core/Src/stm32h7xx_hal_msp.c"
     "Core/Src/stm32h7xx_hal_timebase_tim.c"
+    "Core/Src/user_tasks.c"
+    "Core/Src/tasks/sdram_task.c"
+    "Core/Src/printf_impl.c"
+    "Middlewares/Third_Party/printf/printf.c"
     "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c"
     "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c"
     "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c"
@@ -81,6 +85,7 @@ include_directories(
     "Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"
     "Drivers/CMSIS/Device/ST/STM32H7xx/Include"
     "Drivers/CMSIS/Include"
+    "Middlewares/Third_Party/printf"
 )
 
 # Final compiler flags

Core/Inc/user_tasks.h

@@ -0,0 +1,12 @@
+#ifndef __USER_TASKS_H
+#define __USER_TASKS_H
+
+#include "cmsis_os2.h"
+
+void user_tasks_init(void);
+
+extern osThreadId_t g_sdram_task_handle;
+extern osThreadAttr_t g_sdram_task_attributes;
+void sdram_task(void * argument);
+
+#endif

Core/Src/main.c

@@ -24,6 +24,8 @@
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
 
+#include "user_tasks.h"
+
 /* USER CODE END Includes */
 
 /* Private typedef -----------------------------------------------------------*/
@@ -584,6 +586,9 @@ static void MX_GPIO_Init(void)
 void StartDefaultTask(void *argument)
 {
   /* USER CODE BEGIN 5 */
+
+  user_tasks_init();
+
   HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_3);
   HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_4);
   HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4);

Core/Src/printf_impl.c

@@ -0,0 +1,9 @@
+#include <stdint.h>
+
+#include "stm32h7xx_hal.h"
+
+extern UART_HandleTypeDef huart1;
+
+void _putchar(char character) {
+    HAL_UART_Transmit(&huart1, (uint8_t *)&character, 0x01, 1000);
+}

Core/Src/tasks/sdram_task.c

@@ -0,0 +1,41 @@
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+
+#include "printf.h"
+
+#include "user_tasks.h"
+
+// SDRAM BANK 2, default mapping
+#define SDRAM_START 0xD0000000
+#define SDRAM_END   0xD4000000
+
+osThreadId_t g_sdram_task_handle;
+osThreadAttr_t g_sdram_task_attributes = {
+    .name = "SDRAMT",
+    .stack_size = 256 * 4,
+    .priority = (osPriority_t) osPriorityNormal,
+};
+
+void sdram_task(void * argument) {
+    printf("SDRAM test started...\r\n");
+    
+    for(uint32_t i = SDRAM_START; i < SDRAM_END; i += 4) {
+        *(uint32_t *)i = i;
+        if(i % 0x10000 == 0) {
+            printf("Write: 0x%08lx\r\n", i);
+        }
+    }
+    for(uint32_t i = SDRAM_START; i < SDRAM_END; i += 4) {
+        if(*(uint32_t *)i != i) {
+            printf("Verify err: 0x%08lx\r\n", i);
+            break;
+        }
+        if(i % 0x10000 == 0) {
+            printf("Verify: 0x%08lx\r\n", i);
+        }
+    }
+    printf("SDRAM test completed.\r\n");
+
+    osThreadExit();
+}

Core/Src/user_tasks.c

@@ -0,0 +1,5 @@
+#include "user_tasks.h"
+
+void user_tasks_init(void) {
+    g_sdram_task_handle = osThreadNew(sdram_task, NULL, &g_sdram_task_attributes);
+}

Middlewares/Third_Party/printf

@@ -0,0 +1 @@
+Subproject commit d3b984684bb8a8bdc48cc7a1abecb93ce59bbe3e