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u-boot/drivers/clk/sunxi/Kconfig

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clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
config CLK_SUNXI
bool "Clock support for Allwinner SoCs"
depends on CLK && ARCH_SUNXI
reset: Add Allwinner RESET driver Add common reset driver for all Allwinner SoC's. Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver. Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 16:48:13 +00:00
select DM_RESET
clk: sunxi: Extend DM_RESET selection to SPL The sunxi clock driver exposes a reset controller, so it selects the reset controller framework. Ensure that dependency is also satisfied when building the driver for the SPL. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-11 19:45:31 +00:00
select SPL_DM_RESET if SPL_CLK
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
default y
help
This enables support for common clock driver API on Allwinner
SoCs.
if CLK_SUNXI
clk: sunxi: implement clock driver for suniv f1c100s The f1c100s has a clock tree similar to those of other sunxi parts. Add support for it. Signed-off-by: George Hilliard <thirtythreeforty@gmail.com> Signed-off-by: Yifan Gu <me@yifangu.com> Acked-by: Sean Anderson <seanga2@gmail.com> [Andre: add PIO and I2C] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-25 23:16:23 +00:00
config CLK_SUNIV_F1C100S
bool "Clock driver for Allwinner F1C100s"
default MACH_SUNIV
help
This enables common clock driver support for platforms based
on Allwinner F1C100s SoC.
clk: sunxi: Add Allwinner A10/A20 CLK driver Add initial clock driver for Allwinner A10/A20. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 11:22:37 +00:00
config CLK_SUN4I_A10
bool "Clock driver for Allwinner A10/A20"
default MACH_SUN4I || MACH_SUN7I
help
This enables common clock driver support for platforms based
on Allwinner A10/A20 SoC.
clk: sunxi: Add Allwinner A10s/A13 CLK driver Add initial clock driver for Allwinner A10s/A13. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10s/A13, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10s/A13, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 14:24:26 +00:00
config CLK_SUN5I_A10S
bool "Clock driver for Allwinner A10s/A13"
default MACH_SUN5I
help
This enables common clock driver support for platforms based
on Allwinner A10s/A13 SoC.
clk: sunxi: Add Allwinner A31 CLK driver Add initial clock driver for Allwinner A31. - Implement USB ahb1 and USB clocks via ccu_clk_gate table for A31, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB ahb1 and USB resets via ccu_reset table for A31, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 17:45:34 +00:00
config CLK_SUN6I_A31
bool "Clock driver for Allwinner A31/A31s"
default MACH_SUN6I
help
This enables common clock driver support for platforms based
on Allwinner A31/A31s SoC.
clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Add a driver so the clocks/resets for these peripherals (especially I2C, RSB, and UART) can be enabled using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-12 14:47:25 +00:00
config CLK_SUN6I_A31_R
bool "Clock driver for Allwinner A31 generation PRCM"
default SUNXI_GEN_SUN6I
help
This enables common clock driver support for the PRCM
in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
clk: sunxi: Add Allwinner A23/A33 CLK driver Add initial clock driver for Allwinner A23/A33. - Implement USB bus and USB clocks via ccu_clk_gate table for A23/A33, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A23/A33, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 17:55:03 +00:00
config CLK_SUN8I_A23
bool "Clock driver for Allwinner A23/A33"
default MACH_SUN8I_A23 || MACH_SUN8I_A33
help
This enables common clock driver support for platforms based
on Allwinner A23/A33 SoC.
clk: sunxi: Add Allwinner A83T CLK driver Add initial clock driver for Allwinner A83T. - Implement USB bus and USB clocks via ccu_clk_gate table for A83T, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A83T, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 18:03:55 +00:00
config CLK_SUN8I_A83T
bool "Clock driver for Allwinner A83T"
default MACH_SUN8I_A83T
help
This enables common clock driver support for platforms based
on Allwinner A83T SoC.
clk: sunxi: Add Allwinner R40 CLK driver Add initial clock driver for Allwinner R40. - Implement USB bus and USB clocks via ccu_clk_gate for R40, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for R40, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-05 05:46:33 +00:00
config CLK_SUN8I_R40
bool "Clock driver for Allwinner R40"
default MACH_SUN8I_R40
help
This enables common clock driver support for platforms based
on Allwinner R40 SoC.
clk: sunxi: Add Allwinner V3S CLK driver Add initial clock driver for Allwinner V3S. - Implement USB bus and USB clocks via ccu_clk_gate table for V3S, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for V3S, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-05 09:01:54 +00:00
config CLK_SUN8I_V3S
bool "Clock driver for Allwinner V3S"
default MACH_SUN8I_V3S
help
This enables common clock driver support for platforms based
on Allwinner V3S SoC.
clk: sunxi: Add Allwinner A80 CLK driver Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-01-11 10:11:46 +00:00
config CLK_SUN9I_A80
bool "Clock driver for Allwinner A80"
default MACH_SUN9I
help
This enables common clock driver support for platforms based
on Allwinner A80 SoC.
clk: sunxi: Add Allwinner H3/H5 CLK driver Add initial clock driver for Allwinner H3/H5. - Implement USB bus and USB clocks via ccu_clk_gate table for H3/H5, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for H3/H5, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-08-02 10:13:02 +00:00
config CLK_SUN8I_H3
bool "Clock driver for Allwinner H3/H5"
default MACH_SUNXI_H3_H5
help
This enables common clock driver support for platforms based
on Allwinner H3/H5 SoC.
clk: sunxi: Add support for the D1 CCU Since the D1 CCU binding is defined, we can add support for its gates/resets, following the pattern of the existing drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-01 03:38:37 +00:00
config CLK_SUN20I_D1
bool "Clock driver for Allwinner D1"
sunxi: add Allwinner R528/T113 SoC support This adds the remaining code bits to teach U-Boot about Allwinner's newest SoC generation. This was introduced with the RISC-V based Allwinner D1 SoC, which actually shares a die with the ARM cores versions called R528 (BGA, without DRAM) and T113s (QFP, with embedded DRAM). This adds the new Kconfig stanza, using the two newly introduced symbols for the new SoC generation and pincontroller. It also adds the new symbols to the relavent code places, to set all the hardcoded bits directly. We need one DT override: The ARM core version of the DT specifies the CPUX watchdog as "reserved", which means it won't be recognised by U-Boot. Override this in our generic sunxi-u-boot.dtsi, to let U-Boot pick up this watchdog, so that the generic reset driver will work. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-09-06 14:59:57 +00:00
default MACH_SUN8I_R528
clk: sunxi: Add support for the D1 CCU Since the D1 CCU binding is defined, we can add support for its gates/resets, following the pattern of the existing drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-01 03:38:37 +00:00
help
This enables common clock driver support for platforms based
on Allwinner D1 SoC.
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2018-12-31 10:05:01 +00:00
config CLK_SUN50I_H6
bool "Clock driver for Allwinner H6"
default MACH_SUN50I_H6
help
This enables common clock driver support for platforms based
on Allwinner H6 SoC.
clk: sunxi: Add drivers for A31 and H6 PRCM CCUs Add a driver so the clocks/resets for these peripherals (especially I2C, RSB, and UART) can be enabled using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-12 14:47:25 +00:00
config CLK_SUN50I_H6_R
bool "Clock driver for Allwinner H6 generation PRCM"
default SUN50I_GEN_H6
help
This enables common clock driver support for the PRCM
in Allwinner H6/H616 SoCs.
clk: sunxi: Add support for H616 clocks This commit introduces DM H616 clock driver. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-11 20:11:52 +00:00
config CLK_SUN50I_H616
bool "Clock driver for Allwinner H616"
default MACH_SUN50I_H616
help
This enables common clock driver support for platforms based
on Allwinner H616 SoC.
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-22 16:02:49 +00:00
config CLK_SUN50I_A64
bool "Clock driver for Allwinner A64"
default MACH_SUN50I
help
This enables common clock driver support for platforms based
on Allwinner A64 SoC.
endif # CLK_SUNXI
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