rockchip: Add common default bss and stack addresses

On Rockchip the typical aarch64 boot steps are as follows:
- BROM load TPL to SRAM
- TPL init full DRAM
  - use stack in SRAM at TPL_STACK addr
  - use malloc heap on stack, size is TPL_SYS_MALLOC_F_LEN
- TPL jump back to BROM
- BROM load SPL to beginning of DRAM
- SPL init storage devices
  - use bss in DRAM at SPL_BSS_START_ADDR, size is SPL_BSS_MAX_SIZE
  - use stack in DRAM at SPL_STACK addr (or CUSTOM_SYS_INIT_SP_ADDR)
  - use malloc heap on stack, size is SPL_SYS_MALLOC_F_LEN
- SPL load FIT images from storage to DRAM
  - use stack in DRAM at SPL_STACK_R_ADDR
  - use new malloc heap on stack, size is SPL_STACK_R_MALLOC_SIMPLE_LEN
- SPL jump to TF-A at 0x40000
- (optional) TF-A load OPTEE
- TF-A jump to U-Boot proper at TEXT_BASE
- U-Boot proper init pre-reloc devices
  - use stack in DRAM at CUSTOM_SYS_INIT_SP_ADDR
  - use malloc heap on stack, size is SYS_MALLOC_F_LEN
- U-Boot proper relocate to end of usable DRAM
- U-Boot proper init devices and complete boot

SPL have access to full DRAM, however, current configuration for text
base, stack addr and malloc heap size used at the different boot steps
are at risk of overlapping, e.g. when U-Boot proper + FDT grows close
to 1 MiB on RK3328/RK3399 or when pre-reloc and reloc stack and malloc
heap overlap on ROCK 5A.

Fix this by defining safe defaults for bss, stack and malloc size and
addresses. A range at around [60 MiB, 64 MiB) was chosen to be used for
bss and stack until U-Boot proper have been relocated to end of usable
DRAM. The range was primarily chosen to be able to accommodate SoCs with
a small amount of embedded DRAM, e.g. RK3308G has 64 MiB DRAM.

Overiew of the new common memory layout:
[    0,   2M) - SPL / TF-A / reserved
[   2M,   +X) - U-Boot proper pre-reloc
[   -X,  64M) - bss, stack and malloc heap

During SPL pre-reloc phase:
[    0,	256K) - SPL binary is loaded by BROM to beginning of DRAM
[   -X,	 63M) - SPL pre-reloc stack
[ -32K,	 63M)   - SPL pre-reloc malloc heap
[63.5M,	+32K) - SPL bss

After SPL reloc phase:
[    0,	256K) - SPL binary
[ 256K,	  +X) - TF-A image is loaded by SPL
[   2M,	  +X) - U-Boot proper + FDT image is loaded by SPL
[   -X,	 62M) - SPL reloc stack
[  60M,	 62M)   - SPL reloc malloc heap
[ -32K,	 63M) - SPL init malloc heap, memory allocated during SPL
                pre-reloc phase is still in use at reloc phase
[63.5M,	+32K) - SPL bss

During U-Boot proper pre-reloc phase:
[    0,   2M) - TF-A / reserved
[   2M,   +X) - U-Boot proper + FDT
[   -X,  63M) - U-Boot proper pre-reloc stack (shared addr with SPL)
[ -64K,  63M)   - U-Boot proper pre-reloc malloc heap

After U-Boot proper has relocated to top of memory we should be able to
use 2M+ for loading kernel, initrd, scripts etc.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

arch/arm/mach-rockchip/Kconfig

@@ -558,6 +558,21 @@ config ROCKCHIP_SPI_IMAGE
 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
 	default TEXT_BASE
 
+config ROCKCHIP_COMMON_STACK_ADDR
+	bool
+	depends on SPL_SHARES_INIT_SP_ADDR
+	select HAS_CUSTOM_SYS_INIT_SP_ADDR
+	imply SPL_LIBCOMMON_SUPPORT if SPL
+	imply SPL_LIBGENERIC_SUPPORT if SPL
+	imply SPL_ROCKCHIP_COMMON_BOARD if SPL
+	imply SPL_SYS_MALLOC_F if SPL
+	imply SPL_SYS_MALLOC_SIMPLE if SPL
+	imply TPL_LIBCOMMON_SUPPORT if TPL
+	imply TPL_LIBGENERIC_SUPPORT if TPL
+	imply TPL_ROCKCHIP_COMMON_BOARD if TPL
+	imply TPL_SYS_MALLOC_F if TPL
+	imply TPL_SYS_MALLOC_SIMPLE if TPL
+
 source "arch/arm/mach-rockchip/px30/Kconfig"
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 source "arch/arm/mach-rockchip/rk3066/Kconfig"
@@ -573,4 +588,44 @@ source "arch/arm/mach-rockchip/rk3568/Kconfig"
 source "arch/arm/mach-rockchip/rk3588/Kconfig"
 source "arch/arm/mach-rockchip/rv1108/Kconfig"
 source "arch/arm/mach-rockchip/rv1126/Kconfig"
+
+if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
+
+config CUSTOM_SYS_INIT_SP_ADDR
+	default 0x3f00000
+
+config SYS_MALLOC_F_LEN
+	default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+
+config SPL_SYS_MALLOC_F_LEN
+	default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+
+config TPL_SYS_MALLOC_F_LEN
+	default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+
+config TEXT_BASE
+	default 0x00200000 if ARM64
+
+config SPL_TEXT_BASE
+	default 0x0 if ARM64
+
+config SPL_HAS_BSS_LINKER_SECTION
+	default y if ARM64
+
+config SPL_BSS_START_ADDR
+	default 0x3f80000
+
+config SPL_BSS_MAX_SIZE
+	default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
+
+config SPL_STACK_R
+	default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+
+config SPL_STACK_R_ADDR
+	default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+
+config SPL_STACK_R_MALLOC_SIMPLE_LEN
+	default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
+
+endif
 endif