Embedded_Projects
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Arch: RISCV: Chip-specific header. 

Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
Yilin Sun 2023-09-07 01:30:46 +08:00
parent 8b381fa4f0
commit 636e87e455
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
3 changed files with 12 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/riscv/cpu/start.S
View File

@ -39,11 +39,17 @@ secondary_harts_relocation_error:
.section .text
.globl _start
#if defined(CONFIG_ENABLE_RISCV_SOC_BOOT0_HOOK)
#include <asm/arch/boot0.h>
#else
_start:
#if defined(CONFIG_ENABLE_RISCV_SOC_BOOT0_HOOK)
/*
* Various SoCs need something special and SoC-specific up front in
* order to boot, allow them to set that in their boot0.h file and then
* use it here.
*/
#include <asm/arch/boot0.h>
#endif
#if CONFIG_IS_ENABLED(RISCV_MMODE)
csrr a0, CSR_MHARTID
#endif

1
arch/riscv/include/asm/arch-cv1800b/boot0.h
View File

@ -6,7 +6,6 @@
#ifndef __BOOT0_H__
#define __BOOT0_H__
_start:
/* BOOT0 header information */
j boot0_time_recode
.balign 4

5
board/milkv/cv1800b_milkv_duo/Kconfig
View File

@ -20,10 +20,11 @@ config BOARD_SPECIFIC_OPTIONS
select CVITEK_CV1800B
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if RISCV_SMODE
imply CMD_CPU
imply SUPPORT_OF_CONTROL
imply PINCTRL_CV1800B
imply OF_CONTROL
imply OF_REAL
imply PINCTRL_CV1800B
imply DM_I2C
imply SYS_I2C_DW
endif