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global: Move remaining CONFIG_SYS_* to CFG_SYS_* 

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini 2022-11-16 13:10:41 -05:00
parent a322afc9f9
commit 65cc0e2a65
744 changed files with 5915 additions and 5914 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.checkpatch.conf
View File

@ -4,7 +4,7 @@
# Temporary for false positive in checkpatch
--ignore COMPLEX_MACRO
# For CONFIG_SYS_I2C_NOPROBES
# For CFG_SYS_I2C_NOPROBES
--ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
# For simple_strtoul

6
Kconfig
View File

@ -264,8 +264,8 @@ config HAS_CUSTOM_SYS_INIT_SP_ADDR
default y if TFABOOT
help
Typically, we use an initial stack pointer address that is calculated
by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the
statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the
by taking the statically defined CFG_SYS_INIT_RAM_ADDR, adding the
statically defined CFG_SYS_INIT_RAM_SIZE and then subtracting the
build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different
but statica calculation is performed. However, some platforms will
take a different approach. Say Y here to define the address statically
@ -333,7 +333,7 @@ config SPL_SYS_MALLOC_F_LEN
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new
It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new
malloc() region in SDRAM once it is inited.
config TPL_SYS_MALLOC_F_LEN

16
Makefile
View File

@ -1138,10 +1138,10 @@ endif
$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
@# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which
@# CFG_SYS_TIMER_RATE has brackets in it for some boards which
@# confuses this rule. Use if() to send just a single character which
@# is enable to tell 'deprecated' that one of these symbols exists
$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x))
$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x))
$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
@# Check that this build does not use CONFIG options that we do not
@ -1361,8 +1361,8 @@ u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
# U-Boot entry point, needed for booting of full-blown U-Boot
# from the SPL U-Boot version.
#
ifndef CONFIG_SYS_UBOOT_START
CONFIG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
ifndef CFG_SYS_UBOOT_START
CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE)
endif
# Boards with more complex image requirements can provide an .its source file
@ -1387,7 +1387,7 @@ endif
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
@ -1395,10 +1395,10 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
else
MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log
endif
@ -1429,7 +1429,7 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
UBOOT_BIN := u-boot.bin
MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board"
u-boot.bin.lzma: u-boot.bin FORCE

66
README
View File

@ -341,7 +341,7 @@ The following options need to be configured:
CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
Physical address from the view of DDR controllers. It is the
same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
same as CFG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
- MIPS CPU options:
@ -352,7 +352,7 @@ The following options need to be configured:
be swapped if a flash programmer is used.
- ARM options:
CONFIG_SYS_EXCEPTION_VECTORS_HIGH
CFG_SYS_EXCEPTION_VECTORS_HIGH
Select high exception vectors of the ARM core, e.g., do not
clear the V bit of the c1 register of CP15.
@ -415,7 +415,7 @@ The following options need to be configured:
the defaults discussed just above.
- Cache Configuration for ARM:
CONFIG_SYS_PL310_BASE - Physical base address of PL310
CFG_SYS_PL310_BASE - Physical base address of PL310
controller register space
- Serial Ports:
@ -485,7 +485,7 @@ The following options need to be configured:
- GPIO Support:
CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO
The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of
The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of
chip-ngpio pairs that tell the PCA953X driver the number of
pins supported by a particular chip.
@ -927,21 +927,21 @@ The following options need to be configured:
CONFIG_SYS_I2C_DIRECT_BUS
define this, if you don't use i2c muxes on your hardware.
if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
omit this define.
CONFIG_SYS_I2C_MAX_HOPS
CFG_SYS_I2C_MAX_HOPS
define how many muxes are maximal consecutively connected
on one i2c bus. If you not use i2c muxes, omit this
define.
CONFIG_SYS_I2C_BUSES
CFG_SYS_I2C_BUSES
hold a list of buses you want to use, only used if
CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example
a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and
a board with CFG_SYS_I2C_MAX_HOPS = 1 and
CFG_SYS_NUM_I2C_BUSES = 9:
CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \
@ -1044,7 +1044,7 @@ The following options need to be configured:
active. To switch to a different bus, use the 'i2c dev' command.
Note that bus numbering is zero-based.
CONFIG_SYS_I2C_NOPROBES
CFG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped
when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS
@ -1053,16 +1053,16 @@ The following options need to be configured:
e.g.
#undef CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_NOPROBES {0x50,0x68}
#define CFG_SYS_I2C_NOPROBES {0x50,0x68}
will skip addresses 0x50 and 0x68 on a board with one I2C bus
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
#define CFG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}}
will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
CONFIG_SYS_RTC_BUS_NUM
CFG_SYS_RTC_BUS_NUM
If defined, then this indicates the I2C bus number for the RTC.
If not defined, then U-Boot assumes that RTC is on I2C bus 0.
@ -1120,19 +1120,19 @@ The following options need to be configured:
configuration if the INIT_B line goes low (which
indicated a CRC error).
CONFIG_SYS_FPGA_WAIT_INIT
CFG_SYS_FPGA_WAIT_INIT
Maximum time to wait for the INIT_B line to de-assert
after PROB_B has been de-asserted during a Virtex II
FPGA configuration sequence. The default time is 500
ms.
CONFIG_SYS_FPGA_WAIT_BUSY
CFG_SYS_FPGA_WAIT_BUSY
Maximum time to wait for BUSY to de-assert during
Virtex II FPGA configuration. The default is 5 ms.
CONFIG_SYS_FPGA_WAIT_CONFIG
CFG_SYS_FPGA_WAIT_CONFIG
Time to wait after FPGA configuration. The default is
200 ms.
@ -1429,12 +1429,12 @@ Configuration Settings:
- CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to
prompt for user input.
- CONFIG_SYS_BAUDRATE_TABLE:
- CFG_SYS_BAUDRATE_TABLE:
List of legal baudrate settings for this board.
- CONFIG_SYS_MEM_RESERVE_SECURE
- CFG_SYS_MEM_RESERVE_SECURE
Only implemented for ARMv8 for now.
If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory
If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory
is substracted from total RAM and won't be reported to OS.
This memory can be used as secure memory. A variable
gd->arch.secure_ram is used to track the location. In systems
@ -1444,7 +1444,7 @@ Configuration Settings:
- CFG_SYS_SDRAM_BASE:
Physical start address of SDRAM. _Must_ be 0 here.
- CONFIG_SYS_FLASH_BASE:
- CFG_SYS_FLASH_BASE:
Physical start address of Flash memory.
- CONFIG_SYS_MALLOC_LEN:
@ -1468,16 +1468,16 @@ Configuration Settings:
boards which do not use the full malloc in SPL (which is
enabled with CONFIG_SYS_SPL_MALLOC).
- CONFIG_SYS_BOOTMAPSZ:
- CFG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
the Linux kernel (bd_info, boot arguments, FDT blob if
used) must be put below this limit, unless "bootm_low"
environment variable is defined and non-zero. In such case
all data for the Linux kernel must be between "bootm_low"
and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment
and "bootm_low" + CFG_SYS_BOOTMAPSZ. The environment
variable "bootm_mapsize" will override the value of
CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined,
CFG_SYS_BOOTMAPSZ. If CFG_SYS_BOOTMAPSZ is undefined,
then the value in "bootm_size" will be used instead.
- CONFIG_SYS_BOOT_GET_CMDLINE:
@ -1638,11 +1638,11 @@ Low Level (hardware related) configuration options:
Default (power-on reset) physical address of CCSR on Freescale
PowerPC SOCs.
- CONFIG_SYS_CCSRBAR:
- CFG_SYS_CCSRBAR:
Virtual address of CCSR. On a 32-bit build, this is typically
the same value as CONFIG_SYS_CCSRBAR_DEFAULT.
- CONFIG_SYS_CCSRBAR_PHYS:
- CFG_SYS_CCSRBAR_PHYS:
Physical address of CCSR. CCSR can be relocated to a new
physical address, if desired. In this case, this macro should
be set to that address. Otherwise, it should be set to the
@ -1650,17 +1650,17 @@ Low Level (hardware related) configuration options:
is typically relocated on 36-bit builds. It is recommended
that this macro be defined via the _HIGH and _LOW macros:
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH
* 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW)
#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH
* 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW)
- CONFIG_SYS_CCSRBAR_PHYS_HIGH:
Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically
- CFG_SYS_CCSRBAR_PHYS_HIGH:
Bits 33-36 of CFG_SYS_CCSRBAR_PHYS. This value is typically
either 0 (32-bit build) or 0xF (36-bit build). This macro is
used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL").
- CONFIG_SYS_CCSRBAR_PHYS_LOW:
Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is
- CFG_SYS_CCSRBAR_PHYS_LOW:
Lower 32-bits of CFG_SYS_CCSRBAR_PHYS. This macro is
used in assembly code, so it must not contain typecasts or
integer size suffixes (e.g. "ULL").
@ -1668,7 +1668,7 @@ Low Level (hardware related) configuration options:
DO NOT CHANGE unless you know exactly what you're
doing! (11-4) [MPC8xx systems only]
- CONFIG_SYS_INIT_RAM_ADDR:
- CFG_SYS_INIT_RAM_ADDR:
Start address of memory area that can be used for
initial data and stack; please note that this must be
@ -2737,7 +2737,7 @@ locked as (mis-) used as memory, etc.
cause you grief during the initial boot! It is frequently not
used.
CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere
with your processor/board/system design. The default value
you will find in any recent u-boot distribution in
walnut.h should work for you. I'd set it to a value larger

2
arch/arm/cpu/arm1176/start.S
View File

@ -18,7 +18,7 @@
#include <linux/linkage.h>
#ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CFG_SYS_UBOOT_BASE
#endif
/*

2
arch/arm/cpu/arm926ejs/start.S
View File

@ -95,7 +95,7 @@ flush_dcache:
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH
orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
#else
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */

6
arch/arm/cpu/armv7/arch_timer.c
View File

@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_HZ_CLOCK
#ifndef CFG_SYS_HZ_CLOCK
static inline u32 read_cntfrq(void)
{
u32 frq;
@ -29,8 +29,8 @@ int timer_init(void)
gd->arch.tbl = 0;
gd->arch.tbu = 0;
#ifdef CONFIG_SYS_HZ_CLOCK
gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
#ifdef CFG_SYS_HZ_CLOCK
gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
#else
gd->arch.timer_rate_hz = read_cntfrq();
#endif

4
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@ -313,9 +313,9 @@ int cpu_eth_init(struct bd_info *bis)
int arch_cpu_init(void)
{
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
(void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
u32 state;

2
arch/arm/cpu/armv7/ls102xa/fdt.c
View File

@ -183,7 +183,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
CONFIG_SYS_IFC_ADDR);
CFG_SYS_IFC_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#else
off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,

4
arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
View File

@ -42,7 +42,7 @@ static void __secure ls1_save_ddr_head(void)
static void __secure ls1_fsm_setup(void)
{
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR;
out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001);
@ -118,7 +118,7 @@ static void __secure ls1_delay(unsigned int loop)
static void __secure ls1_start_fsm(void)
{
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;

4
arch/arm/cpu/armv7/stv0991/timer.c
View File

@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
(struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
@ -67,7 +67,7 @@ void __udelay(unsigned long usec)
{
ulong tmo;
ulong start = get_timer_masked();
ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
ulong rndoff;
rndoff = (usec % 10) ? 1 : 0;

8
arch/arm/cpu/armv7m/systick-timer.c
View File

@ -18,7 +18,7 @@
* The number of reference clock ticks that correspond to 10ms is normally
* defined in the SysTick Calibration register's TENMS field. However, on some
* devices this is wrong, so this driver allows the clock rate to be defined
* using CONFIG_SYS_HZ_CLOCK.
* using CFG_SYS_HZ_CLOCK.
*/
#include <common.h>
@ -76,10 +76,10 @@ int timer_init(void)
/*
* If the TENMS field is inexact or wrong, specify the clock rate using
* CONFIG_SYS_HZ_CLOCK.
* CFG_SYS_HZ_CLOCK.
*/
#if defined(CONFIG_SYS_HZ_CLOCK)
gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
#if defined(CFG_SYS_HZ_CLOCK)
gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK;
#else
gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
#endif

54
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -114,7 +114,7 @@ static struct mm_region early_map[] = {
CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
{ CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
CONFIG_SYS_FSL_IFC_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
@ -130,9 +130,9 @@ static struct mm_region early_map[] = {
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#ifdef CONFIG_FSL_IFC
/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
/* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
@ -391,7 +391,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
{}, /* space holder for secure mem */
#endif
{},
@ -445,7 +445,7 @@ static inline void early_mmu_setup(void)
if (el == 3)
gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
else
gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
@ -568,7 +568,7 @@ static inline void final_mmu_setup(void)
}
}
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
if (el == 3) {
/*
@ -580,7 +580,7 @@ static inline void final_mmu_setup(void)
gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
final_map[index].virt = gd->arch.secure_ram & ~0x3;
final_map[index].phys = final_map[index].virt;
final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE;
final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
tlb_addr_save = gd->arch.tlb_addr;
@ -1323,10 +1323,10 @@ phys_size_t get_effective_memsize(void)
ea_size = gd->ram_size;
}
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
/* Check if we have enough space for secure memory */
if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
if (ea_size > CFG_SYS_MEM_RESERVE_SECURE)
ea_size -= CFG_SYS_MEM_RESERVE_SECURE;
else
printf("Error: No enough space for secure memory.\n");
#endif
@ -1433,7 +1433,7 @@ int dram_init_banksize(void)
* gd->arch.secure_ram should be done to avoid running it repeatedly.
*/
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
debug("No need to run again, skip %s\n", __func__);
@ -1442,11 +1442,11 @@ int dram_init_banksize(void)
#endif
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE;
gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE;
CFG_SYS_DDR_BLOCK1_SIZE;
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
@ -1458,17 +1458,17 @@ int dram_init_banksize(void)
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
}
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->bd->bi_dram[0].size >
CONFIG_SYS_MEM_RESERVE_SECURE) {
CFG_SYS_MEM_RESERVE_SECURE) {
gd->bd->bi_dram[0].size -=
CONFIG_SYS_MEM_RESERVE_SECURE;
CFG_SYS_MEM_RESERVE_SECURE;
gd->arch.secure_ram = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size;
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE;
}
#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
#endif /* CFG_SYS_MEM_RESERVE_SECURE */
#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
/* Assign memory for MC */
@ -1520,7 +1520,7 @@ int dram_init_banksize(void)
}
#endif
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
debug("%s is called. gd->ram_size is reduced to %lu\n",
__func__, (ulong)gd->ram_size);
#endif
@ -1580,7 +1580,7 @@ void update_early_mmu_table(void)
} else {
mmu_change_region_attr(
CFG_SYS_SDRAM_BASE,
CONFIG_SYS_DDR_BLOCK1_SIZE,
CFG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
@ -1589,10 +1589,10 @@ void update_early_mmu_table(void)
#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
#endif
if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE >
CONFIG_SYS_DDR_BLOCK2_SIZE) {
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK2_BASE,
CFG_SYS_DDR_BLOCK2_BASE,
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
@ -1601,7 +1601,7 @@ void update_early_mmu_table(void)
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK3_BASE,
gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE -
CFG_SYS_DDR_BLOCK1_SIZE -
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
@ -1611,9 +1611,9 @@ void update_early_mmu_table(void)
#endif
{
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK2_BASE,
CFG_SYS_DDR_BLOCK2_BASE,
gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE,
CFG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |

4
arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
View File

@ -116,10 +116,10 @@ Flash Layout
Environment Variables
=====================
mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
mcinitcmd: This environment variable is defined to initiate MC and DPL deployment
from the location where it is stored(NOR, NAND, SD, SATA, USB)during

2
arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
View File

@ -10,7 +10,7 @@
#include <fsl_sec.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),

2
arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
View File

@ -9,7 +9,7 @@
#include <asm/arch-fsl-layerscape/fsl_portals.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),

6
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -531,7 +531,7 @@ static void erratum_a010539(void)
porsr1 = in_be32(&gur->porsr1);
porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
porsr1);
out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
#endif
@ -643,8 +643,8 @@ void init_pfe_scfg_dcfg_regs(void)
out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
| SCFG_RD_QOS1_PFE2_QOS));
ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
ecccr2 | (unsigned int)DISABLE_PFE_ECC);
}
#endif

2
arch/arm/cpu/armv8/fsl-layerscape/spl.c
View File

@ -116,7 +116,7 @@ void board_init_f(ulong dummy)
#endif
dram_init();
#ifdef CONFIG_SPL_FSL_LS_PPA
#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
#ifndef CFG_SYS_MEM_RESERVE_SECURE
#error Need secure RAM for PPA
#endif
/*

4
arch/arm/cpu/armv8/sec_firmware.c
View File

@ -198,7 +198,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img,
goto out;
}
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
/*
* The SEC Firmware must be stored in secure memory.
* Append SEC Firmware to secure mmu table.
@ -211,7 +211,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img,
sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) +
gd->arch.tlb_size;
#else
#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support"
#endif
/* Align SEC Firmware base address to 4K */

36
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -20,13 +20,13 @@
* Reserve secure memory
* To be aligned with MMU block size
*/
#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
#define CFG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CFG_SYS_PAGE_SIZE 0x10000
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
@ -37,8 +37,8 @@
#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
@ -96,7 +96,7 @@
#elif defined(CONFIG_ARCH_LS1088A)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CFG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
#define SRDS_BITS_PER_LANE 4
@ -122,8 +122,8 @@
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
@ -141,15 +141,15 @@
#endif
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CFG_SYS_PAGE_SIZE 0x10000
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
@ -192,8 +192,8 @@
#define SMMU_BASE 0x05000000 /* GR0 Base */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SEC */
@ -212,8 +212,8 @@
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 7
#define CFG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
@ -251,15 +251,15 @@
#elif defined(CONFIG_ARCH_LS1012A)
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#elif defined(CONFIG_ARCH_LS1046A)
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SMMU Defintions */
#define SMMU_BASE 0x09000000

4
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
View File

@ -75,7 +75,7 @@ void fdt_fixup_icid(void *blob);
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
CFG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(compat, streamid) \
SET_SCFG_ICID(compat, streamid, sata_icid,\
@ -142,7 +142,7 @@ extern int fman_icid_tbl_sz;
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
CFG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(sata_num, compat, streamid) \
SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \

78
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -11,11 +11,11 @@
#include <linux/bitops.h>
#endif
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
#define CFG_SYS_DCSRBAR 0x20000000
#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00140000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
@ -30,37 +30,37 @@
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
#define CFG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000
#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
CONFIG_SYS_BMAN_MEM_BASE)
#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
#define CFG_SYS_BMAN_NUM_PORTALS 10
#define CFG_SYS_BMAN_MEM_BASE 0x508000000
#define CFG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
CFG_SYS_BMAN_MEM_BASE)
#define CFG_SYS_BMAN_MEM_SIZE 0x08000000
#define CFG_SYS_BMAN_SP_CENA_SIZE 0x10000
#define CFG_SYS_BMAN_SP_CINH_SIZE 0x10000
#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
CFG_SYS_BMAN_CENA_SIZE)
#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_SWP_ISDR_REG 0x3E80
#define CFG_SYS_QMAN_NUM_PORTALS 10
#define CFG_SYS_QMAN_MEM_BASE 0x500000000
#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
#define CFG_SYS_QMAN_MEM_SIZE 0x08000000
#define CFG_SYS_QMAN_SP_CINH_SIZE 0x10000
#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
CFG_SYS_QMAN_CENA_SIZE)
#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_SWP_ISDR_REG 0x3680
#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000
@ -134,20 +134,20 @@
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
#define TP_INIT_PER_CLUSTER 4
#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR 0x01000000
#ifndef CFG_SYS_CCSRBAR
#define CFG_SYS_CCSRBAR 0x01000000
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000
#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
#define CFG_SYS_CCSRBAR_PHYS_LOW 0x01000000
#endif
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CONFIG_SYS_CCSRBAR_PHYS_LOW)
#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CFG_SYS_CCSRBAR_PHYS_LOW)
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];

10
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -33,7 +33,7 @@
#define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR
#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#endif
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
@ -67,8 +67,8 @@
#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
@ -105,7 +105,7 @@
#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000)
/* SFP */
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
#define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull
@ -173,7 +173,7 @@
#endif
/* Security Monitor */
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
/* MMU 500 */
#define SMMU_SCR0 (SMMU_BASE + 0x0)

4
arch/arm/include/asm/arch-lpc32xx/config.h
View File

@ -23,7 +23,7 @@
#define CFG_SYS_NS16550_CLK 13000000
#endif
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
/* NAND */
@ -49,7 +49,7 @@
/* USB OHCI */
#if defined(CONFIG_USB_OHCI_LPC32XX)
#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE
#define CFG_SYS_USB_OHCI_REGS_BASE USB_BASE
#endif
#endif /* _LPC32XX_CONFIG_H */

22
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -11,36 +11,36 @@
#define OCRAM_BASE_S_ADDR 0x10010000
#define OCRAM_S_SIZE 0x00010000
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CFG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00220000)
#define SYS_FSL_DCSR_RCPM_ADDR (CFG_SYS_DCSRBAR + 0x00222000)
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
#define CFG_SYS_FSL_JR0_OFFSET 0x00710000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
#define CFG_SYS_TSEC1_OFFSET 0x01d10000
#define CFG_SYS_MDIO1_OFFSET 0x01d24000
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)

18
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
View File

@ -42,24 +42,24 @@
#define DCFG_DCSR_PORCR1 0
#ifndef CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
#ifndef CFG_SYS_CCSRBAR
#define CFG_SYS_CCSRBAR CONFIG_SYS_IMMR
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf
#else
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
#endif
#endif
#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
#endif
#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CONFIG_SYS_CCSRBAR_PHYS_LOW)
#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
CFG_SYS_CCSRBAR_PHYS_LOW)
struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];

4
arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
View File

@ -12,14 +12,14 @@
{ .compat = name, \
.id = { idA }, .num_ids = 1, \
.reg_offset = off + CONFIG_SYS_IMMR, \
.compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
.compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
}
#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
{ .compat = name, \
.id = { idA, idB }, .num_ids = 2, \
.reg_offset = off + CONFIG_SYS_IMMR, \
.compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
.compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \
}
/*

4
arch/arm/include/asm/arch-mx31/imx-regs.h
View File

@ -899,9 +899,9 @@ struct esdc_regs {
* Generic timer support
*/
#ifdef CONFIG_MX31_CLK32
#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32
#define CFG_SYS_TIMER_RATE CONFIG_MX31_CLK32
#else
#define CONFIG_SYS_TIMER_RATE 32768
#define CFG_SYS_TIMER_RATE 32768
#endif
#endif /* __ASM_ARCH_MX31_IMX_REGS_H */

2
arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
View File

@ -36,6 +36,6 @@ struct gpt_regs *const gpt1_regs_ptr =
#define GPT_FREE_RUNNING 0xFFFF
/* Timer, HZ specific defines */
#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#define CFG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
#endif

2
arch/arm/include/asm/arch-sunxi/i2c.h
View File

@ -18,6 +18,6 @@
#endif
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
#define CONFIG_SYS_TCLK 24000000
#define CFG_SYS_TCLK 24000000
#endif

2
arch/arm/include/asm/global_data.h
View File

@ -54,7 +54,7 @@ struct arch_global_data {
unsigned long tlb_emerg;
#endif
#endif
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
#define MEM_RESERVE_SECURE_SECURED 0x1
#define MEM_RESERVE_SECURE_MAINTAINED 0x2
#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3)

2
arch/arm/lib/bdinfo.c
View File

@ -29,7 +29,7 @@ void arch_print_bdinfo(void)
struct bd_info *bd = gd->bd;
bdinfo_print_num_l("arch_number", bd->bi_arch_number);
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
bdinfo_print_num_ll("Secure ram",
gd->arch.secure_ram &

2
arch/arm/lib/cache-pl310.c
View File

@ -11,7 +11,7 @@
#include <config.h>
#include <common.h>
struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
static void pl310_cache_sync(void)
{

2
arch/arm/lib/cache.c
View File

@ -152,7 +152,7 @@ __weak int arm_reserve_mmu(void)
debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
#ifdef CFG_SYS_MEM_RESERVE_SECURE
/*
* Record allocated tlb_addr in case gd->tlb_addr to be overwritten
* with location within secure ram.

4
arch/arm/lib/vectors.S
View File

@ -83,8 +83,8 @@
*/
_start:
#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
.word CONFIG_SYS_DV_NOR_BOOT_CFG
#ifdef CFG_SYS_DV_NOR_BOOT_CFG
.word CFG_SYS_DV_NOR_BOOT_CFG
#endif
ARM_VECTORS
#endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */

6
arch/arm/mach-at91/arm920t/clock.c
View File

@ -26,7 +26,7 @@ static unsigned long at91_css_to_rate(unsigned long css)
{
switch (css) {
case AT91_PMC_MCKR_CSS_SLOW:
return CONFIG_SYS_AT91_SLOW_CLOCK;
return CFG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
@ -107,7 +107,7 @@ int at91_clock_init(unsigned long main_clock)
{
unsigned freq, mckr;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
#ifndef CFG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
@ -120,7 +120,7 @@ int at91_clock_init(unsigned long main_clock)
tmp = readl(&pmc->mcfr);
} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
tmp &= AT91_PMC_MCFR_MAINF_MASK;
main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
}
#endif
gd->arch.main_clk_rate_hz = main_clock;

6
arch/arm/mach-at91/arm920t/cpu.c
View File

@ -16,11 +16,11 @@
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
#define CONFIG_SYS_AT91_MAIN_CLOCK 0
#ifndef CFG_SYS_AT91_MAIN_CLOCK
#define CFG_SYS_AT91_MAIN_CLOCK 0
#endif
int arch_cpu_init(void)
{
return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
}

18
arch/arm/mach-at91/arm920t/lowlevel_init.S
View File

@ -94,11 +94,11 @@ SMRDATA:
.word AT91_ASM_MC_SMC_CSR0
.word CONFIG_SYS_SMC_CSR0_VAL
.word AT91_ASM_PMC_PLLAR
.word CONFIG_SYS_PLLAR_VAL
.word CFG_SYS_PLLAR_VAL
.word AT91_ASM_PMC_PLLBR
.word CONFIG_SYS_PLLBR_VAL
.word AT91_ASM_PMC_MCKR
.word CONFIG_SYS_MCKR_VAL
.word CFG_SYS_MCKR_VAL
SMRDATAE:
/* here there's a delay */
SMRDATA1:
@ -107,17 +107,17 @@ SMRDATA1:
.word AT91_ASM_PIOC_BSR
.word CONFIG_SYS_PIOC_BSR_VAL
.word AT91_ASM_PIOC_PDR
.word CONFIG_SYS_PIOC_PDR_VAL
.word CFG_SYS_PIOC_PDR_VAL
.word AT91_ASM_MC_EBI_CSA
.word CONFIG_SYS_EBI_CSA_VAL
.word AT91_ASM_MC_SDRAMC_CR
.word CONFIG_SYS_SDRC_CR_VAL
.word CFG_SYS_SDRC_CR_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL
.word CFG_SYS_SDRC_MR_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
.word CFG_SYS_SDRC_MR_VAL1
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word CFG_SYS_SDRAM
@ -135,15 +135,15 @@ SMRDATA1:
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
.word CFG_SYS_SDRC_MR_VAL2
.word CFG_SYS_SDRAM1
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL
.word CFG_SYS_SDRC_TR_VAL
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
.word AT91_ASM_MC_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
.word CFG_SYS_SDRC_MR_VAL3
.word CFG_SYS_SDRAM
.word CFG_SYS_SDRAM_VAL
SMRDATA1E:

4
arch/arm/mach-at91/arm920t/timer.c
View File

@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
/* the number of clocks per CONFIG_SYS_HZ */
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
#define TIMER_LOAD_VAL (CFG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
int timer_init(void)
{
@ -92,7 +92,7 @@ void __udelay(unsigned long usec)
u32 endtime;
signed long diff;
tmo = CONFIG_SYS_HZ_CLOCK / 1000;
tmo = CFG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= 1000;

6
arch/arm/mach-at91/arm926ejs/clock.c
View File

@ -26,7 +26,7 @@ static unsigned long at91_css_to_rate(unsigned long css)
{
switch (css) {
case AT91_PMC_MCKR_CSS_SLOW:
return CONFIG_SYS_AT91_SLOW_CLOCK;
return CFG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
@ -115,7 +115,7 @@ int at91_clock_init(unsigned long main_clock)
{
unsigned freq, mckr;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
#ifndef CFG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
@ -128,7 +128,7 @@ int at91_clock_init(unsigned long main_clock)
tmp = readl(&pmc->mcfr);
} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
tmp &= AT91_PMC_MCFR_MAINF_MASK;
main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
}
#endif
gd->arch.main_clk_rate_hz = main_clock;

6
arch/arm/mach-at91/arm926ejs/cpu.c
View File

@ -15,13 +15,13 @@
#include <asm/arch/at91_gpbr.h>
#include <asm/arch/clk.h>
#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
#define CONFIG_SYS_AT91_MAIN_CLOCK 0
#ifndef CFG_SYS_AT91_MAIN_CLOCK
#define CFG_SYS_AT91_MAIN_CLOCK 0
#endif
int arch_cpu_init(void)
{
return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
}
void arch_preboot_os(void)

54
arch/arm/mach-at91/arm926ejs/lowlevel_init.S
View File

@ -21,8 +21,8 @@
#ifdef CONFIG_ATMEL_LEGACY
#include <asm/arch/at91sam9_matrix.h>
#endif
#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
#ifndef CFG_SYS_MATRIX_EBICSA_VAL
#define CFG_SYS_MATRIX_EBICSA_VAL CFG_SYS_MATRIX_EBI0CSA_VAL
#endif
.globl lowlevel_init
@ -67,7 +67,7 @@ POS1:
ldr r1, =(AT91_ASM_PMC_MOR)
ldr r2, =(AT91_ASM_PMC_SR)
/* Main oscillator Enable register PMC_MOR: */
ldr r0, =CONFIG_SYS_MOR_VAL
ldr r0, =CFG_SYS_MOR_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Main Oscillator is enabled */
@ -85,7 +85,7 @@ MOSCS_Loop:
* ----------------------------------------------------------------------------
*/
ldr r1, =(AT91_ASM_PMC_PLLAR)
ldr r0, =CONFIG_SYS_PLLAR_VAL
ldr r0, =CFG_SYS_PLLAR_VAL
str r0, [r1]
/* Reading the PMC Status register to detect when the PLLA is locked */
@ -105,7 +105,7 @@ MOSCS_Loop1:
ldr r1, =(AT91_ASM_PMC_MCKR)
/* -Master Clock Controller register PMC_MCKR */
ldr r0, =CONFIG_SYS_MCKR1_VAL
ldr r0, =CFG_SYS_MCKR1_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
@ -116,7 +116,7 @@ MCKRDY_Loop:
cmp r3, #AT91_PMC_IXR_MCKRDY
bne MCKRDY_Loop
ldr r0, =CONFIG_SYS_MCKR2_VAL
ldr r0, =CFG_SYS_MCKR2_VAL
str r0, [r1]
/* Reading the PMC Status to detect when the Master clock is ready */
@ -158,53 +158,53 @@ SDRAM_setup_end:
SMRDATA:
.word AT91_ASM_WDT_MR
.word CONFIG_SYS_WDTC_WDMR_VAL
.word CFG_SYS_WDTC_WDMR_VAL
/* configure PIOx as EBI0 D[16-31] */
#if defined(CONFIG_AT91SAM9263)
.word AT91_ASM_PIOD_PDR
.word CONFIG_SYS_PIOD_PDR_VAL1
.word CFG_SYS_PIOD_PDR_VAL1
.word AT91_ASM_PIOD_PUDR
.word CONFIG_SYS_PIOD_PPUDR_VAL
.word CFG_SYS_PIOD_PPUDR_VAL
.word AT91_ASM_PIOD_ASR
.word CONFIG_SYS_PIOD_PPUDR_VAL
.word CFG_SYS_PIOD_PPUDR_VAL
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
|| defined(CONFIG_AT91SAM9G20)
.word AT91_ASM_PIOC_PDR
.word CONFIG_SYS_PIOC_PDR_VAL1
.word CFG_SYS_PIOC_PDR_VAL1
.word AT91_ASM_PIOC_PUDR
.word CONFIG_SYS_PIOC_PPUDR_VAL
.word CFG_SYS_PIOC_PPUDR_VAL
#endif
.word AT91_ASM_MATRIX_CSA0
.word CONFIG_SYS_MATRIX_EBICSA_VAL
.word CFG_SYS_MATRIX_EBICSA_VAL
/* flash */
.word AT91_ASM_SMC_MODE0
.word CONFIG_SYS_SMC0_MODE0_VAL
.word CFG_SYS_SMC0_MODE0_VAL
.word AT91_ASM_SMC_CYCLE0
.word CONFIG_SYS_SMC0_CYCLE0_VAL
.word CFG_SYS_SMC0_CYCLE0_VAL
.word AT91_ASM_SMC_PULSE0
.word CONFIG_SYS_SMC0_PULSE0_VAL
.word CFG_SYS_SMC0_PULSE0_VAL
.word AT91_ASM_SMC_SETUP0
.word CONFIG_SYS_SMC0_SETUP0_VAL
.word CFG_SYS_SMC0_SETUP0_VAL
SMRDATA1:
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL1
.word CFG_SYS_SDRC_MR_VAL1
.word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL1
.word CFG_SYS_SDRC_TR_VAL1
.word AT91_ASM_SDRAMC_CR
.word CONFIG_SYS_SDRC_CR_VAL
.word CFG_SYS_SDRC_CR_VAL
.word AT91_ASM_SDRAMC_MDR
.word CONFIG_SYS_SDRC_MDR_VAL
.word CFG_SYS_SDRC_MDR_VAL
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL2
.word CFG_SYS_SDRC_MR_VAL2
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL1
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL3
.word CFG_SYS_SDRC_MR_VAL3
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL2
.word CFG_SYS_SDRAM_BASE
@ -222,20 +222,20 @@ SMRDATA1:
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL9
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL4
.word CFG_SYS_SDRC_MR_VAL4
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL10
.word AT91_ASM_SDRAMC_MR
.word CONFIG_SYS_SDRC_MR_VAL5
.word CFG_SYS_SDRC_MR_VAL5
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL11
.word AT91_ASM_SDRAMC_TR
.word CONFIG_SYS_SDRC_TR_VAL2
.word CFG_SYS_SDRC_TR_VAL2
.word CFG_SYS_SDRAM_BASE
.word CFG_SYS_SDRAM_VAL12
/* User reset enable*/
.word AT91_ASM_RSTC_MR
.word CONFIG_SYS_RSTC_RMR_VAL
.word CFG_SYS_RSTC_RMR_VAL
#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
/* MATRIX_MCFG - REMAP all masters */
.word AT91_ASM_MATRIX_MCFG

8
arch/arm/mach-at91/armv7/clock.c
View File

@ -28,7 +28,7 @@ static unsigned long at91_css_to_rate(unsigned long css)
{
switch (css) {
case AT91_PMC_MCKR_CSS_SLOW:
return CONFIG_SYS_AT91_SLOW_CLOCK;
return CFG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
@ -58,7 +58,7 @@ int at91_clock_init(unsigned long main_clock)
{
unsigned freq, mckr;
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
#ifndef CFG_SYS_AT91_MAIN_CLOCK
unsigned tmp;
/*
* When the bootloader initialized the main oscillator correctly,
@ -71,7 +71,7 @@ int at91_clock_init(unsigned long main_clock)
tmp = readl(&pmc->mcfr);
} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
tmp &= AT91_PMC_MCFR_MAINF_MASK;
main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16);
}
#endif
gd->arch.main_clk_rate_hz = main_clock;
@ -271,7 +271,7 @@ u32 at91_get_periph_generated_clk(u32 id)
clk_source = regval & AT91_PMC_PCR_GCKCSS;
switch (clk_source) {
case AT91_PMC_PCR_GCKCSS_SLOW_CLK:
freq = CONFIG_SYS_AT91_SLOW_CLOCK;
freq = CFG_SYS_AT91_SLOW_CLOCK;
break;
case AT91_PMC_PCR_GCKCSS_MAIN_CLK:
freq = gd->arch.main_clk_rate_hz;

6
arch/arm/mach-at91/armv7/cpu.c
View File

@ -18,8 +18,8 @@
#include <asm/arch/at91_gpbr.h>
#include <asm/arch/clk.h>
#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
#define CONFIG_SYS_AT91_MAIN_CLOCK 0
#ifndef CFG_SYS_AT91_MAIN_CLOCK
#define CFG_SYS_AT91_MAIN_CLOCK 0
#endif
int arch_cpu_init(void)
@ -27,7 +27,7 @@ int arch_cpu_init(void)
#if defined(CONFIG_CLK_CCF)
return 0;
#else
return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
#endif
}

2
arch/arm/mach-at91/include/mach/at91sam9260.h
View File

@ -128,7 +128,7 @@
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines

2
arch/arm/mach-at91/include/mach/at91sam9261.h
View File

@ -112,7 +112,7 @@
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines

2
arch/arm/mach-at91/include/mach/at91sam9263.h
View File

@ -127,7 +127,7 @@
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines

2
arch/arm/mach-at91/include/mach/at91sam9g45.h
View File

@ -132,7 +132,7 @@
#define ATMEL_BASE_CS7 0x80000000
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines

2
arch/arm/mach-at91/include/mach/at91sam9rl.h
View File

@ -112,7 +112,7 @@
#define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
#define CFG_SYS_TIMER_COUNTER 0xfffffd3c
/*
* Other misc defines

2
arch/arm/mach-at91/include/mach/at91sam9x5.h
View File

@ -162,7 +162,7 @@
#endif
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c
#define CFG_SYS_TIMER_COUNTER 0xfffffe3c
/*
* Other misc defines

2
arch/arm/mach-at91/include/mach/sam9x60.h
View File

@ -140,7 +140,7 @@
#define ATMEL_CPU_NAME get_cpu_name()
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfffffe4c
#define CFG_SYS_TIMER_COUNTER 0xfffffe4c
/*
* Other misc defines

2
arch/arm/mach-at91/include/mach/sama5d2.h
View File

@ -238,7 +238,7 @@
#define cpu_is_sama5d2 _cpu_is_sama5d2
/* PIT Timer(PIT_PIIR) */
#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
#define CFG_SYS_TIMER_COUNTER 0xf804803c
#ifndef __ASSEMBLY__
unsigned int get_chip_id(void);

2
arch/arm/mach-at91/include/mach/sama5d3.h
View File

@ -185,7 +185,7 @@
#define CPU_HAS_PCR
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c
#define CFG_SYS_TIMER_COUNTER 0xfffffe3c
/*
* PMECC table in ROM

2
arch/arm/mach-at91/include/mach/sama5d4.h
View File

@ -217,7 +217,7 @@
(get_extension_chip_id() == ARCH_EXID_SAMA5D44))
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
#define CFG_SYS_TIMER_COUNTER 0xfc06863c
/*
* No PMECC Galois table in ROM

12
arch/arm/mach-at91/spl_at91.c
View File

@ -101,17 +101,17 @@ void board_init_f(ulong dummy)
at91_pllicpr_init(0x00);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
at91_plla_init(CONFIG_SYS_AT91_PLLA);
at91_plla_init(CFG_SYS_AT91_PLLA);
/* PCK = PLLA = 2 * MCK */
at91_mck_init(CONFIG_SYS_MCKR);
at91_mck_init(CFG_SYS_MCKR);
/* Switch MCK on PLLA output */
at91_mck_init(CONFIG_SYS_MCKR_CSS);
at91_mck_init(CFG_SYS_MCKR_CSS);
#if defined(CONFIG_SYS_AT91_PLLB)
#if defined(CFG_SYS_AT91_PLLB)
/* Configure PLLB */
at91_pllb_init(CONFIG_SYS_AT91_PLLB);
at91_pllb_init(CFG_SYS_AT91_PLLB);
#endif
/* Enable External Reset */
@ -120,7 +120,7 @@ void board_init_f(ulong dummy)
/* Initialize matrix */
matrix_init();
gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
gd->arch.mck_rate_hz = CFG_SYS_MASTER_CLOCK;
/*
* init timer long enough for using in spl.
*/

2
arch/arm/mach-at91/spl_atmel.c
View File

@ -124,7 +124,7 @@ void board_init_f(ulong dummy)
/* PMC configuration */
at91_pmc_init();
at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK);
matrix_init();

2
arch/arm/mach-davinci/cpu.c
View File

@ -42,7 +42,7 @@ int clk_get(enum davinci_clk_ids id)
int pll_out;
unsigned int pll_base;
pll_out = CONFIG_SYS_OSCIN_FREQ;
pll_out = CFG_SYS_OSCIN_FREQ;
if (id == DAVINCI_AUXCLK_CLKID)
goto out;

24
arch/arm/mach-davinci/da850_lowlevel.c
View File

@ -185,9 +185,9 @@ static int da850_ddr_setup(void)
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
}
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
writel(CFG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
if (CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
/* DDR2 */
clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
(1 << DDR_SLEW_DDR_PDENA_BIT) |
@ -211,19 +211,19 @@ static int da850_ddr_setup(void)
* At the same time, set the TIMUNLOCK bit to allow changing
* the timing registers
*/
tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
tmp = CFG_SYS_DA850_DDR2_SDBCR;
tmp &= ~DV_DDR_BOOTUNLOCK;
tmp |= DV_DDR_TIMUNLOCK;
writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
/* write memory configuration and timing */
if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
if (!(CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
/* MOBILE DDR only*/
writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
writel(CFG_SYS_DA850_DDR2_SDBCR2,
&dv_ddr2_regs_ctrl->sdbcr2);
}
writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
writel(CFG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
writel(CFG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
/* clear the TIMUNLOCK bit and write the value of the CL field */
tmp &= ~DV_DDR_TIMUNLOCK;
@ -233,7 +233,7 @@ static int da850_ddr_setup(void)
* LPMODEN and MCLKSTOPEN must be set!
* Without this bits set, PSC don;t switch states !!
*/
writel(CONFIG_SYS_DA850_DDR2_SDRCR |
writel(CFG_SYS_DA850_DDR2_SDRCR |
(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
&dv_ddr2_regs_ctrl->sdrcr);
@ -246,7 +246,7 @@ static int da850_ddr_setup(void)
/* disable self refresh */
clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
writel(CFG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
return 0;
}
@ -265,7 +265,7 @@ int arch_cpu_init(void)
writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
dv_maskbits(&davinci_syscfg_regs->suspsrc,
CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
CFG_SYS_DA850_SYSCFG_SUSPSRC);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
@ -273,8 +273,8 @@ int arch_cpu_init(void)
#if defined(CONFIG_SYS_DA850_PLL_INIT)
/* PLL setup */
da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
da850_pll_init(davinci_pllc0_regs, CFG_SYS_DA850_PLL0_PLLM);
da850_pll_init(davinci_pllc1_regs, CFG_SYS_DA850_PLL1_PLLM);
#endif
/* setup CSn config */
#if defined(CONFIG_SYS_DA850_CS2CFG)

4
arch/arm/mach-davinci/timer.c
View File

@ -32,7 +32,7 @@
DECLARE_GLOBAL_DATA_PTR;
static struct davinci_timer * const timer =
(struct davinci_timer *)CONFIG_SYS_TIMERBASE;
(struct davinci_timer *)CFG_SYS_TIMERBASE;
#define TIMER_LOAD_VAL 0xffffffff
@ -47,7 +47,7 @@ int timer_init(void)
writel(0x0, &timer->tim34);
writel(TIMER_LOAD_VAL, &timer->prd34);
writel(2 << 22, &timer->tcr);
gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK / TIM_CLK_DIV;
gd->arch.timer_reset_value = 0;
return(0);

2
arch/arm/mach-exynos/spl_boot.c
View File

@ -141,7 +141,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
{
int upto, todo;
int i, timeout = 100;
struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
struct exynos_spi *regs = (struct exynos_spi *)CFG_SYS_SPI_BASE;
set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
/* set the spi1 GPIO */

8
arch/arm/mach-imx/image-container.c
View File

@ -248,13 +248,13 @@ unsigned long spl_nor_get_uboot_base(void)
int end;
/* Calculate the image set end,
* if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000),
* we use CONFIG_SYS_UBOOT_BASE
* if it is less than CFG_SYS_UBOOT_BASE(0x8281000),
* we use CFG_SYS_UBOOT_BASE
* Otherwise, use the calculated address
*/
end = get_imageset_end((void *)NULL, QSPI_NOR_DEV);
if (end <= CONFIG_SYS_UBOOT_BASE)
end = CONFIG_SYS_UBOOT_BASE;
if (end <= CFG_SYS_UBOOT_BASE)
end = CFG_SYS_UBOOT_BASE;
else
end = ROUND(end, SZ_1K);

10
arch/arm/mach-imx/mx5/lowlevel_init.S
View File

@ -205,7 +205,7 @@ setup_pll_func:
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
ldr r1, =0x000010C0 | CFG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
@ -215,7 +215,7 @@ setup_pll_func:
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
ldr r1, =0x000020C0 | CFG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
setup_pll PLL3_BASE_ADDR, 216
@ -240,10 +240,10 @@ setup_pll_func:
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
ldr r1, =0x000020C2 | CFG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
ldr r1, =CFG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
/* Restore the default values in the Gate registers */
@ -378,7 +378,7 @@ ENTRY(lowlevel_init)
mov r10, lr
mov r4, #0 /* Fix R4 to 0 */
#if defined(CONFIG_SYS_MAIN_PWR_ON)
#if defined(CFG_SYS_MAIN_PWR_ON)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
orr r1, r1, #1 << 23

2
arch/arm/mach-k3/config_secure.mk
View File

@ -30,7 +30,7 @@ tispl.bin_HS: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$(
$(call if_changed,mkfitimage)
MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))

2
arch/arm/mach-keystone/cmd_mon.c
View File

@ -23,7 +23,7 @@ static int do_mon_install(struct cmd_tbl *cmdtp, int flag, int argc,
if (argc < 2)
return CMD_RET_USAGE;
freq = CONFIG_SYS_HZ_CLOCK;
freq = CFG_SYS_HZ_CLOCK;
addr = hextoul(argv[1], NULL);

2
arch/arm/mach-keystone/include/mach/hardware.h
View File

@ -263,7 +263,7 @@ typedef volatile unsigned int *dv_reg_p;
/* MSMC segment size shift bits */
#define KS2_MSMC_SEG_SIZE_SHIFT 12
#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \
#define KS2_MSMC_DST_SEG_BASE (CFG_SYS_LPAE_SDRAM_BASE >> \
KS2_MSMC_SEG_SIZE_SHIFT)
/* Device speed */

4
arch/arm/mach-kirkwood/include/mach/config.h
View File

@ -52,8 +52,8 @@
/* Use common timer */
#ifndef CONFIG_TIMER
#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
#define CFG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
#define CFG_SYS_TIMER_RATE CFG_SYS_TCLK
#endif
#endif /* _KW_CONFIG_H */

2
arch/arm/mach-kirkwood/include/mach/kw88f6192.h
View File

@ -15,6 +15,6 @@
#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE
/* TCLK Core Clock defination */
#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
#define CFG_SYS_TCLK 166000000 /* 166MHz */
#endif /* _CONFIG_KW88F6192_H */

2
arch/arm/mach-kirkwood/include/mach/kw88f6281.h
View File

@ -15,7 +15,7 @@
#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
/* TCLK Core Clock definition */
#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \
#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \
166666667 : 200000000)
#endif /* _ASM_ARCH_KW88F6281_H */

4
arch/arm/mach-mvebu/cpu.c
View File

@ -659,7 +659,7 @@ void enable_caches(void)
void v7_outer_cache_enable(void)
{
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
(struct pl310_regs *)CFG_SYS_PL310_BASE;
/* The L2 cache is already disabled at this point */
@ -691,7 +691,7 @@ void v7_outer_cache_enable(void)
void v7_outer_cache_disable(void)
{
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
(struct pl310_regs *)CFG_SYS_PL310_BASE;
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}

10
arch/arm/mach-mvebu/include/mach/soc.h
View File

@ -54,7 +54,7 @@
#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
#define CFG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
#define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100))
#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
@ -146,7 +146,7 @@
#define BOOT_FROM_UART 0x30
#define BOOT_FROM_SPI 0x38
#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
200000000 : 166000000)
#elif defined(CONFIG_ARMADA_38X)
/* SAR values for Armada 38x */
@ -169,7 +169,7 @@
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31
#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
200000000 : 250000000)
#elif defined(CONFIG_ARMADA_MSYS)
/* SAR values for MSYS */
@ -188,7 +188,7 @@
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
#define CFG_SYS_TCLK 200000000 /* 200MHz */
#elif defined(CONFIG_ARMADA_XP)
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
@ -209,7 +209,7 @@
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#define CFG_SYS_TCLK 250000000 /* 250MHz */
#endif
#endif /* _MVEBU_SOC_H */

4
arch/arm/mach-mvebu/lowlevel.S
View File

@ -35,10 +35,10 @@ ENTRY(arch_very_early_init)
* Disable L2 cache
*
* NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG
* but CONFIG_SYS_PL310_BASE is already calculated from base
* but CFG_SYS_PL310_BASE is already calculated from base
* address SOC_REGS_PHY_BASE.
*/
ldr r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
ldr r1, =(CFG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG)
ldr r0, [r1, #L2X0_CTRL_OFF]
bic r0, #L2X0_CTRL_EN
str r0, [r1, #L2X0_CTRL_OFF]

2
arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c
View File

@ -11,7 +11,7 @@ void l2_pl310_init(void);
void set_pl310_ctrl(u32 enable)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
writel(enable, &pl310->pl310_ctrl);
}

2
arch/arm/mach-omap2/config_secure.mk
View File

@ -102,7 +102,7 @@ u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin FORCE
ifdef CONFIG_SPL_LOAD_FIT
MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST)))

12
arch/arm/mach-omap2/mem-common.c
View File

@ -124,11 +124,11 @@ void set_gpmc_cs0(int flash_type)
#if defined(CONFIG_NOR)
case MTD_DEV_TYPE_NOR:
gpmc_regs = gpmc_regs_nor;
base = CONFIG_SYS_FLASH_BASE;
size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
base = CFG_SYS_FLASH_BASE;
size = (CFG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
((CFG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
((CFG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
((CFG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
GPMC_SIZE_16M)));
break;
#endif
@ -142,7 +142,7 @@ void set_gpmc_cs0(int flash_type)
#if defined(CONFIG_CMD_ONENAND)
case MTD_DEV_TYPE_ONENAND:
gpmc_regs = gpmc_regs_onenand;
base = CONFIG_SYS_ONENAND_BASE;
base = CFG_SYS_ONENAND_BASE;
size = GPMC_SIZE_128M;
break;
#endif

2
arch/arm/mach-omap2/timer.c
View File

@ -27,7 +27,7 @@
DECLARE_GLOBAL_DATA_PTR;
static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
static struct gptimer *timer_base = (struct gptimer *)CFG_SYS_TIMERBASE;
static ulong get_timer_masked(void);
/*

2
arch/arm/mach-orion5x/include/mach/mv88f5182.h
View File

@ -18,6 +18,6 @@
#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE
/* TCLK Core Clock defination */
#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
#define CFG_SYS_TCLK 166000000 /* 166MHz */
#endif /* _CONFIG_88F5182_H */

6
arch/arm/mach-orion5x/timer.c
View File

@ -74,7 +74,7 @@ struct orion5x_tmr_registers *orion5x_tmr_regs =
static inline ulong read_timer(void)
{
return readl(CNTMR_VAL_REG(UBOOT_CNTR))
/ (CONFIG_SYS_TCLK / 1000);
/ (CFG_SYS_TCLK / 1000);
}
DECLARE_GLOBAL_DATA_PTR;
@ -92,7 +92,7 @@ static ulong get_timer_masked(void)
} else {
/* we have an overflow ... */
timestamp += lastdec +
(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
(TIMER_LOAD_VAL / (CFG_SYS_TCLK / 1000)) - now;
}
lastdec = now;
@ -115,7 +115,7 @@ void __udelay(unsigned long usec)
ulong delayticks;
current = uboot_cntr_val();
delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
delayticks = (usec * (CFG_SYS_TCLK / 1000000));
if (current < delayticks) {
delayticks -= current;

2
arch/arm/mach-rmobile/include/mach/r8a7790.h
View File

@ -24,7 +24,7 @@
#define MSTP11_BITS 0x00000000
/* SDHI */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
#define CFG_SYS_SH_SDHI_NR_CHANNEL 4
#define R8A7790_CUT_ES2X 2
#define IS_R8A7790_ES2() \

2
arch/arm/mach-rmobile/include/mach/r8a7791.h
View File

@ -14,7 +14,7 @@
*/
/* SDHI */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100

2
arch/arm/mach-rmobile/include/mach/r8a7792.h
View File

@ -24,6 +24,6 @@
#define MSTP11_BITS 0x00000008
/* SDHI */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
#define CFG_SYS_SH_SDHI_NR_CHANNEL 1
#endif /* __ASM_ARCH_R8A7792_H */

2
arch/arm/mach-rmobile/include/mach/r8a7793.h
View File

@ -15,7 +15,7 @@
*/
/* SDHI */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100

2
arch/arm/mach-rmobile/include/mach/r8a7794.h
View File

@ -24,7 +24,7 @@
#define MSTP11_BITS 0x000001C0
/* SDHI */
#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
#define R8A7794_CUT_ES2 2
#define IS_R8A7794_ES2() \

8
arch/arm/mach-rmobile/timer.c
View File

@ -40,8 +40,8 @@ static u64 get_time_us(void)
{
u64 timer = get_cpu_global_timer();
timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK));
timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1));
do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK));
return timer;
}
@ -65,7 +65,7 @@ void __udelay(unsigned long usec)
u64 wait;
start = get_cpu_global_timer();
wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2);
wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2);
do {
current = get_cpu_global_timer();
} while ((current - start) < wait);
@ -83,5 +83,5 @@ unsigned long long get_ticks(void)
ulong get_tbclk(void)
{
return (ulong)(CONFIG_SYS_CPU_CLK >> 2);
return (ulong)(CFG_SYS_CPU_CLK >> 2);
}

2
arch/arm/mach-socfpga/misc.c
View File

@ -34,7 +34,7 @@ phys_addr_t socfpga_sysmgr_base __section(".data");
#ifdef CONFIG_SYS_L2_PL310
static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
(struct pl310_regs *)CFG_SYS_PL310_BASE;
#endif
struct bsel bsel_str[] = {

4
arch/arm/mach-socfpga/misc_arria10.c
View File

@ -60,7 +60,7 @@ static Altera_desc altera_fpga[] = {
#if defined(CONFIG_SPL_BUILD)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
(struct pl310_regs *)CFG_SYS_PL310_BASE;
static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
@ -256,7 +256,7 @@ void dram_bank_mmu_setup(int bank)
/* If we're still in OCRAM, don't set the XN bit on it */
if (!(gd->flags & GD_FLG_RELOC)) {
set_section_dcache(
CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
DCACHE_WRITETHROUGH);
}

2
arch/arm/mach-socfpga/misc_gen5.c
View File

@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
(struct pl310_regs *)CFG_SYS_PL310_BASE;
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static struct scu_registers *scu_regs =

2
arch/arm/mach-socfpga/spl_a10.c
View File

@ -41,7 +41,7 @@
DECLARE_GLOBAL_DATA_PTR;
#define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */
#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
#define BOOTROM_SHARED_MEM_ADDR (CFG_SYS_INIT_RAM_ADDR + \
SOCFPGA_PHYS_OCRAM_SIZE - \
BOOTROM_SHARED_MEM_SIZE)
#define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438)

2
arch/arm/mach-socfpga/timer.c
View File

@ -10,7 +10,7 @@
#define TIMER_LOAD_VAL 0xFFFFFFFF
static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE;
static const struct socfpga_timer *timer_base = (void *)CFG_SYS_TIMERBASE;
/*
* Timer initialization

2
arch/arm/mach-u8500/cache.c
View File

@ -22,7 +22,7 @@ void enable_caches(void)
#ifdef CONFIG_SYS_L2_PL310
void v7_outer_cache_disable(void)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE;
/*
* Linux expects the L2 cache to be turned off by the bootloader.

2
arch/arm/mach-uniphier/arm32/timer.c
View File

@ -10,7 +10,7 @@
#include "arm-mpcore.h"
#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
#define PRESCALER ((PERIPHCLK) / (CFG_SYS_TIMER_RATE) - 1)
static void *get_global_timer_base(void)
{

8
arch/arm/mach-versatile/timer.c
View File

@ -36,9 +36,9 @@ int timer_init (void)
ulong tmr_ctrl_val;
/* 1st disable the Timer */
tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~TIMER_ENABLE;
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
*(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
/*
* The Timer Control Register has one Undefined/Shouldn't Use Bit
@ -52,11 +52,11 @@ int timer_init (void)
* Tmr Siz : 16 Bit Counter
* Tmr in Wrapping Mode
*/
tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
*(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
return 0;
}

2
arch/m68k/cpu/mcf523x/cpu.c
View File

@ -92,7 +92,7 @@ int watchdog_init(void)
u32 wdog_module = 0;
/* set timeout and enable watchdog */
wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
wdog_module |= (wdog_module / 8192);
out_be16(&wdp->mr, wdog_module);

38
arch/m68k/cpu/mcf523x/cpu_init.c
View File

@ -47,36 +47,36 @@ void cpu_init_f(void)
out_be16(&wdog->cr, 0);
#endif
out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
out_be32(&scm->rambar, CFG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
/* Port configuration */
out_8(&gpio->par_cs, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
out_be_fbcs_reg(&fbcs->csar0, CFG_SYS_CS0_BASE);
out_be_fbcs_reg(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
out_be_fbcs_reg(&fbcs->csar1, CFG_SYS_CS1_BASE);
out_be_fbcs_reg(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
out_be_fbcs_reg(&fbcs->csar2, CFG_SYS_CS2_BASE);
out_be_fbcs_reg(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
out_be_fbcs_reg(&fbcs->csar3, CFG_SYS_CS3_BASE);
out_be_fbcs_reg(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
@ -108,8 +108,8 @@ void cpu_init_f(void)
#endif
#ifdef CONFIG_SYS_I2C_FSL
CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#endif
icache_enable();

2
arch/m68k/cpu/mcf523x/speed.c
View File

@ -29,7 +29,7 @@ int get_clocks(void)
while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
;
gd->bus_clk = CONFIG_SYS_CLK;
gd->bus_clk = CFG_SYS_CLK;
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_SYS_I2C_FSL

6
arch/m68k/cpu/mcf523x/start.S
View File

@ -91,10 +91,10 @@ _start:
move.w #0x2700,%sr /* Mask off Interrupt */
/* Set vector base register at the beginning of the Flash */
move.l #CONFIG_SYS_FLASH_BASE, %d0
move.l #CFG_SYS_FLASH_BASE, %d0
movec %d0, %VBR
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
@ -116,7 +116,7 @@ _start:
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,

10
arch/m68k/cpu/mcf52x2/cpu.c
View File

@ -132,11 +132,11 @@ int print_cpuinfo(void)
if (cpu_model)
printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
cpu_model, prn, strmhz(buf, CFG_SYS_CLK));
else
printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
pin, prn, strmhz(buf, CONFIG_SYS_CLK));
pin, prn, strmhz(buf, CFG_SYS_CLK));
return 0;
}
@ -284,7 +284,7 @@ int print_cpuinfo(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
strmhz(buf, CONFIG_SYS_CLK));
strmhz(buf, CFG_SYS_CLK));
return 0;
};
#endif /* CONFIG_DISPLAY_CPUINFO */
@ -370,7 +370,7 @@ int print_cpuinfo(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
strmhz(buf, CONFIG_SYS_CLK));
strmhz(buf, CFG_SYS_CLK));
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
@ -394,7 +394,7 @@ int print_cpuinfo(void)
unsigned char resetsource = mbar_readLong(SIM_RSR);
printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
strmhz(buf, CONFIG_SYS_CLK));
strmhz(buf, CFG_SYS_CLK));
if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
printf("Reset:%s%s\n",

110
arch/m68k/cpu/mcf52x2/cpu_init.c
View File

@ -36,31 +36,31 @@ void init_fbcs(void)
{
fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
&& defined(CONFIG_SYS_CS0_CTRL))
out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \
&& defined(CFG_SYS_CS0_CTRL))
out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
#else
#warning "Chip Select 0 are not initialized/used"
#endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
&& defined(CONFIG_SYS_CS1_CTRL))
out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \
&& defined(CFG_SYS_CS1_CTRL))
out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE);
out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
&& defined(CONFIG_SYS_CS2_CTRL))
out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \
&& defined(CFG_SYS_CS2_CTRL))
out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE);
out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
&& defined(CONFIG_SYS_CS3_CTRL))
out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \
&& defined(CFG_SYS_CS3_CTRL))
out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE);
out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
#endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
&& defined(CONFIG_SYS_CS4_CTRL))
@ -214,9 +214,9 @@ void cpu_init_f(void)
init_fbcs();
#ifdef CONFIG_SYS_I2C_FSL
CONFIG_SYS_I2C_PINMUX_REG =
CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
CFG_SYS_I2C_PINMUX_REG =
CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR;
CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#ifdef CONFIG_SYS_I2C2_OFFSET
CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
@ -335,21 +335,21 @@ void cpu_init_f(void)
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR);
gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
out_be16(&sysctrl->sc_scr, CFG_SYS_SCR);
out_be16(&sysctrl->sc_spr, CFG_SYS_SPR);
/* Setup Ports: */
out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT);
out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR);
out_be16(&gpio->gpio_padat, CFG_SYS_PADAT);
out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT);
out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR);
out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT);
out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT);
/* Memory Controller: */
out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
@ -472,8 +472,8 @@ void cpu_init_f(void)
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_SYS_I2C_FSL
CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
#endif
/* enable instruction cache now */
@ -560,8 +560,8 @@ void cpu_init_f(void)
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR =
MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) |
MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
@ -573,17 +573,17 @@ void cpu_init_f(void)
#ifdef CONFIG_SYS_PFPAR
MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
#endif
#ifdef CONFIG_SYS_PJPAR
MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
#ifdef CFG_SYS_PJPAR
MCFGPIO_PJPAR = CFG_SYS_PJPAR;
#endif
#ifdef CONFIG_SYS_PSDPAR
MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
#endif
#ifdef CONFIG_SYS_PASPAR
MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
#ifdef CFG_SYS_PASPAR
MCFGPIO_PASPAR = CFG_SYS_PASPAR;
#endif
#ifdef CONFIG_SYS_PEHLPAR
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
#ifdef CFG_SYS_PEHLPAR
MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
#endif
#ifdef CONFIG_SYS_PQSPAR
MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
@ -600,15 +600,15 @@ void cpu_init_f(void)
#ifdef CONFIG_SYS_PTDPAR
MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
#endif
#ifdef CONFIG_SYS_PUAPAR
MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
#ifdef CFG_SYS_PUAPAR
MCFGPIO_PUAPAR = CFG_SYS_PUAPAR;
#endif
#if defined(CONFIG_SYS_DDRD)
MCFGPIO_DDRD = CONFIG_SYS_DDRD;
#endif
#ifdef CONFIG_SYS_DDRUA
MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
#ifdef CFG_SYS_DDRUA
MCFGPIO_DDRUA = CFG_SYS_DDRUA;
#endif
/* FlexBus Chipselect */
@ -652,10 +652,10 @@ int fecpin_setclear(fec_info_t *info, int setclear)
{
if (setclear) {
MCFGPIO_PASPAR |= 0x0F00;
MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR;
} else {
MCFGPIO_PASPAR &= 0xF0FF;
MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR;
}
return 0;
}
@ -678,12 +678,12 @@ void cpu_init_f(void)
* which is their primary function.
* ~Jeremy
*/
mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC);
mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC);
mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN);
mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN);
mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT);
mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT);
/*
* dBug Compliance:

14
arch/m68k/cpu/mcf52x2/speed.c
View File

@ -23,19 +23,19 @@ int get_clocks(void)
#if defined(CONFIG_M5208)
pll_t *pll = (pll_t *) MMAP_PLL;
out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
out_8(&pll->odr, CFG_SYS_PLL_ODR);
out_8(&pll->fdr, CFG_SYS_PLL_FDR);
#endif
#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
#ifndef CONFIG_SYS_PLL_BYPASS
#ifndef CFG_SYS_PLL_BYPASS
#ifdef CONFIG_M5249
/* Setup the PLL to run at the specified speed */
#ifdef CONFIG_SYS_FAST_CLK
#ifdef CFG_SYS_FAST_CLK
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
@ -43,7 +43,7 @@ int get_clocks(void)
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
pllcr = CONFIG_SYS_PLLCR;
pllcr = CFG_SYS_PLLCR;
#endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@ -52,7 +52,7 @@ int get_clocks(void)
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
#endif /* #ifndef CFG_SYS_PLL_BYPASS */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
@ -68,7 +68,7 @@ int get_clocks(void)
;
#endif
gd->cpu_clk = CONFIG_SYS_CLK;
gd->cpu_clk = CFG_SYS_CLK;
#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
defined(CONFIG_M5271) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;

48
arch/m68k/cpu/mcf52x2/start.S
View File

@ -35,7 +35,7 @@
*/
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long _start - CONFIG_TEXT_BASE
#else
.long _START
@ -81,9 +81,9 @@ _vectors:
.text
#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
#if defined(CFG_SYS_INT_FLASH_BASE) && \
(defined(CONFIG_M5282) || defined(CONFIG_M5281))
#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
.long 0xFFFFFFFF /* all sectors protected */
.long 0x00000000 /* supervisor/User restriction */
@ -100,53 +100,53 @@ _start:
#if defined(CONFIG_M5208)
/* Initialize RAMBAR: locate SRAM and validate it */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
/* set MBAR address + valid flag */
move.l #(CONFIG_SYS_MBAR + 1), %d0
move.l #(CFG_SYS_MBAR + 1), %d0
move.c %d0, %MBAR
/*** The 5249 has MBAR2 as well ***/
#ifdef CONFIG_SYS_MBAR2
#ifdef CFG_SYS_MBAR2
/* Get MBAR2 address */
move.l #(CONFIG_SYS_MBAR2 + 1), %d0
move.l #(CFG_SYS_MBAR2 + 1), %d0
/* Set MBAR2 */
movec %d0, #0xc0e
#endif
move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0
movec %d0, %RAMBAR0
#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* set MBAR address + valid flag */
move.l #(CONFIG_SYS_MBAR + 1), %d0
move.l #(CFG_SYS_MBAR + 1), %d0
move.l %d0, 0x40000000
/* Initialize RAMBAR1: locate SRAM and validate it */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#if defined(CONFIG_M5282)
#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
/*
* Setup code in SRAM to initialize FLASHBAR,
* if start from internal Flash
*/
move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
move.l #(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0
move.l #(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1
move.l #(CFG_SYS_INIT_RAM_ADDR), %a2
_copy_flash:
move.l (%a0)+, (%a2)+
cmp.l %a0, %a1
bgt.s _copy_flash
jmp CONFIG_SYS_INIT_RAM_ADDR
jmp CFG_SYS_INIT_RAM_ADDR
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
@ -154,9 +154,9 @@ _flashbar_setup_end:
_after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
#endif /* (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */
#endif
#endif
@ -165,22 +165,22 @@ _after_flashbar_copy:
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
move.l #CONFIG_SYS_INT_FLASH_BASE, %d0
#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE)
move.l #CFG_SYS_INT_FLASH_BASE, %d0
#else
move.l #CONFIG_SYS_FLASH_BASE, %d0
move.l #CFG_SYS_FLASH_BASE, %d0
#endif
movec %d0, %VBR
#endif
#ifdef CONFIG_M5275
/* set MBAR address + valid flag */
move.l #(CONFIG_SYS_MBAR + 1), %d0
move.l #(CFG_SYS_MBAR + 1), %d0
move.l %d0, 0x40000000
/* movec %d0, %MBAR */
/* Initialize RAMBAR: locate SRAM and validate it */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#endif
@ -195,7 +195,7 @@ _after_flashbar_copy:
move.l #__got_start, %a5
/* setup stack initially on top of internal static ram */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp
/*
* if configured, malloc_f arena will be reserved first,

2
arch/m68k/cpu/mcf530x/cpu.c
View File

@ -33,7 +33,7 @@ int print_cpuinfo(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n",
strmhz(buf, CONFIG_SYS_CPU_CLK));
strmhz(buf, CFG_SYS_CPU_CLK));
return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

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