65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
132 lines
3.0 KiB
C
132 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2003
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* Texas Instruments <www.ti.com>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* (C) Copyright 2002-2004
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* (C) Copyright 2004
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* Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*/
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#include <common.h>
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#include <init.h>
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#include <time.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/timer_defs.h>
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#include <div64.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct davinci_timer * const timer =
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(struct davinci_timer *)CFG_SYS_TIMERBASE;
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#define TIMER_LOAD_VAL 0xffffffff
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#define TIM_CLK_DIV 16
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int timer_init(void)
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{
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/* We are using timer34 in unchained 32-bit mode, full speed */
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writel(0x0, &timer->tcr);
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writel(0x0, &timer->tgcr);
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writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
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writel(0x0, &timer->tim34);
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writel(TIMER_LOAD_VAL, &timer->prd34);
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writel(2 << 22, &timer->tcr);
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gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK / TIM_CLK_DIV;
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gd->arch.timer_reset_value = 0;
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return(0);
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}
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/*
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* Get the current 64 bit timer tick count
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*/
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unsigned long long get_ticks(void)
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{
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unsigned long now = readl(&timer->tim34);
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/* increment tbu if tbl has rolled over */
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if (now < gd->arch.tbl)
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gd->arch.tbu++;
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gd->arch.tbl = now;
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return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
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}
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ulong get_timer(ulong base)
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{
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unsigned long long timer_diff;
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timer_diff = get_ticks() - gd->arch.timer_reset_value;
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return lldiv(timer_diff,
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(gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
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}
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void __udelay(unsigned long usec)
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{
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unsigned long long endtime;
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endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
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1000000UL);
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endtime += get_ticks();
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while (get_ticks() < endtime)
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;
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return gd->arch.timer_rate_hz;
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}
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#ifdef CONFIG_HW_WATCHDOG
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static struct davinci_timer * const wdttimer =
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(struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
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/*
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* See prufw2.pdf for using Timer as a WDT
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*/
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void davinci_hw_watchdog_enable(void)
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{
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writel(0x0, &wdttimer->tcr);
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writel(0x0, &wdttimer->tgcr);
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/* TIMMODE = 2h */
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writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
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writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
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writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
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writel(2 << 22, &wdttimer->tcr);
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writel(0x0, &wdttimer->tim12);
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writel(0x0, &wdttimer->tim34);
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/* set WDEN bit, WDKEY 0xa5c6 */
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writel(0xa5c64000, &wdttimer->wdtcr);
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/* clear counter register */
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writel(0xda7e4000, &wdttimer->wdtcr);
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}
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void davinci_hw_watchdog_reset(void)
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{
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writel(0xa5c64000, &wdttimer->wdtcr);
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writel(0xda7e4000, &wdttimer->wdtcr);
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}
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#endif
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