CV1800B: Added CVITEK-SPIF driver.
Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
parent
636e87e455
commit
a63830773f
GPG Key ID:
17F01E106F9F5E0A
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@ -34,6 +34,31 @@
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i2c1_pins: i2c1 {
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pinmux = <PINMUX(PAD_MIPIRX0N, IIC1_SCL)>, <PINMUX(PAD_MIPIRX1P, IIC1_SDA)>;
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};
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spif_pins: spif {
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pinmux = <PINMUX(SPINOR_SCK, SPINOR_SCK)>, <PINMUX(SPINOR_MOSI, SPINOR_MOSI)>,
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<PINMUX(SPINOR_MISO, SPINOR_MISO)>, <PINMUX(SPINOR_CS_X, SPINOR_CS_X)>,
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<PINMUX(SPINOR_HOLD_X, SPINOR_HOLD_X)>, <PINMUX(SPINOR_WP_X, SPINOR_WP_X)>;
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};
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};
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&spif {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&spif_pins>;
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pinctrl-names = "default";
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spi-max-frequency = <30000000>;
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status = "okay";
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nor-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg=<0>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <30000000>;
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};
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};
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&uart0 {
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@ -45,6 +45,13 @@
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#clock-cells = <0>;
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};
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hsp_clk: hs-peri-clock {
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compatible = "fixed-clock";
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clock-output-names = "hsp_clk";
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clock-frequency = <150000000>;
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#clock-cells = <0>;
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};
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apb_clk: apb-clk-clock {
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compatible = "fixed-clock";
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clock-output-names = "apb_clk";
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@ -81,6 +88,14 @@
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pins = <75>;
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};
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spif: spi@10000000 {
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compatible = "cvitek,cv1800b-spif", "cvitek,cvitek-spif";
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reg = <0x0 0x10000000 0x0 0x10000000>;
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interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&hsp_clk>;
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status = "disabled";
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};
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uart0: serial@04140000 {
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compatible = "cvitek,cv1800b-uart", "snps,dw-apb-uart";
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reg = <0x0 0x04140000 0x0 0x1000>;
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@ -6,6 +6,7 @@
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/pinctrl.h>
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#include <dt-bindings/pinctrl/cv1800b-pinctrl.h>
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#include <mapmem.h>
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@ -34,7 +35,7 @@ static int cv1800b_pc_get_pins_count(struct udevice *dev)
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{
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struct cv1800b_pc_priv *priv = dev_get_priv(dev);
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debug("%s: pin count: %d", __func__, priv->num_pins);
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dev_dbg(dev, "pin count: %d", priv->num_pins);
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return priv->num_pins;
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}
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@ -48,7 +49,7 @@ static int cv1800b_pc_pinmux_set(struct udevice *dev, u32 pinmux_group)
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priv->pinmux->ctrl[pin] = (priv->pinmux->ctrl[pin] & ~(CV1800B_PC_FUNC)) | func;
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debug("%s: pin %d, func: %d\n", __func__, pin, func);
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dev_dbg(dev, "pin %d, func: %d\n", pin, func);
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return 0;
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}
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@ -76,7 +77,7 @@ static int cv1800b_pc_probe(struct udevice *dev)
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if(dev_read_u32(dev, "pins", &priv->num_pins) < 0)
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return -EINVAL;
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debug("%s: pinctrl@%p, %d pins\n", __func__, priv->pinmux, priv->num_pins);
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dev_dbg(dev, "pinctrl@%p, %d pins\n", priv->pinmux, priv->num_pins);
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return 0;
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}
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@ -168,6 +168,12 @@ config CF_SPI
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Enable the ColdFire SPI driver. This driver can be used on
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some m68k SoCs.
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config CVITEK_SPIF
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bool "Cvitek SPIF controller driver"
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help
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Enable the Cvitek SPIF controller driver, which (almost always)
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connects to an SPI NOR flash device.
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config DAVINCI_SPI
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bool "Davinci & Keystone SPI driver"
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depends on ARCH_DAVINCI || ARCH_KEYSTONE
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@ -30,6 +30,7 @@ obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
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obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o
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obj-$(CONFIG_CF_SPI) += cf_spi.o
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obj-$(CONFIG_CORTINA_SFLASH) += ca_sflash.o
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obj-$(CONFIG_CVITEK_SPIF) += cvitek-spif.o
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obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
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obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
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obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
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@ -0,0 +1,499 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2023 Yilin Sun <imi415@imi.moe>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/sizes.h>
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#define CVI_SPIF_BUS_WIDTH_1 0x00
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#define CVI_SPIF_BUS_WIDTH_2 0x01
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#define CVI_SPIF_BUS_WIDTH_4 0x02
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#define CVI_SPIF_FIFO_DEPTH 8U
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/**
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* SPIF SPI_CTRL register
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*
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*/
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#define CVI_SPIF_SPI_CTRL_SCK_DIV_SHIFT 0
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#define CVI_SPIF_SPI_CTRL_SCK_DIV_MASK GENMASK(10, 0) /* Clock divider, assume F/(x+1) */
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#define CVI_SPIF_SPI_CTRL_CPHA_SHIFT 12
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#define CVI_SPIF_SPI_CTRL_CPHA_MASK BIT(12) /* Clock phase */
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#define CVI_SPIF_SPI_CTRL_CPOL_SHIFT 13
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#define CVI_SPIF_SPI_CTRL_CPOL_MASK BIT(13) /* Clock polarity */
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#define CVI_SPIF_SPI_CTRL_HOLD_OL_MASK BIT(14) /* HOLD output low?*/
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#define CVI_SPIF_SPI_CTRL_WP_OL_MASK BIT(15) /* WP output low? */
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#define CVI_SPIF_SPI_CTRL_FRAME_LEN_MASK BIT(16) /* Frame length */
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#define CVI_SPIF_SPI_CTRL_LSB_FIRST_MASK BIT(20) /* LSB first SPI */
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#define CVI_SPIF_SPI_CTRL_SRST_MASK BIT(21) /* Software Reset? */
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/**
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* SPIF CE_CTRL register
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*
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*/
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#define CVI_SPIF_CE_CTRL_CEMANUAL_MASK BIT(0) /* Manual CE control value */
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#define CVI_SPIF_CE_CTRL_CEMANUAL_EN_MASK BIT(1) /* Manual CE control enable */
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/**
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* SPIF DLY_CTRL register
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*
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*/
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#define CVI_SPIF_DLY_CTRL_CET_MASK GENMASK(9, 8)
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#define CVI_SPIF_DLY_CTRL_NEG_SAMPLE_MASK BIT(14)
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/**
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* SPIF DMMR register
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*
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*/
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#define CVI_SPIF_DMMR_EN_MASK BIT(0) /* Direct memory-mapped mode enable */
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/**
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* SPIF TRANS_CSR register
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*
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*/
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#define CVI_SPIF_TRANS_CSR_MODE_SHIFT 0
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#define CVI_SPIF_TRANS_CSR_MODE_MASK GENMASK(1, 0) /* Mode, 01: Read, 10: Write */
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#define CVI_SPIF_TRANS_CSR_MODE(x) \
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((x << CVI_SPIF_TRANS_CSR_MODE_SHIFT) & CVI_SPIF_TRANS_CSR_MODE_MASK)
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#define CVI_SPIF_TRANS_CSR_CONT_READ_MASK BIT(2) /* Continous mode read? */
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#define CVI_SPIF_TRANS_CSR_FAST_MODE_MASK BIT(3) /* Fast mode (which)? */
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#define CVI_SPIF_TRANS_CSR_BUS_WIDTH_SHIFT 4
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#define CVI_SPIF_TRANS_CSR_BUS_WIDTH_MASK GENMASK(5, 4) /* Bus width, 2^x bits */
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#define CVI_SPIF_TRANS_CSR_BUS_WIDTH(x) \
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((x << CVI_SPIF_TRANS_CSR_BUS_WIDTH_SHIFT) & CVI_SPIF_TRANS_CSR_BUS_WIDTH_MASK)
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#define CVI_SPIF_TRANS_CSR_DMA_EN_MASK BIT(6) /* DMA request enable? */
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#define CVI_SPIF_TRANS_CSR_MISO_LVL_MASK BIT(7) /* Read MISO level? */
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#define CVI_SPIF_TRANS_CSR_ADDR_BYTES_MASK GENMASK(10, 8) /* Address bytes? */
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#define CVI_SPIF_TRANS_CSR_WITH_CMD_MASK BIT(11) /* ??? */
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#define CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL_SHIFT 12
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#define CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL_MASK GENMASK(13, 12) /* FIFO (IRQ?) trigger level, 2^x bytes */
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#define CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL(x) \
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((x << CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL_SHIFT) & CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL_MASK)
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#define CVI_SPIF_TRANS_CSR_GO_BUSY_MASK BIT(15) /* Write 1 to GO? Self-cleared bit? */
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#define CVI_SPIF_TRANS_CSR_DUMMY_MASK GENMASK(19, 16) /* Dummy count? */
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#define CVI_SPIF_TRANS_CSR_4B_ADDR_MASK BIT(20) /* 4 bytes address */
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#define CVI_SPIF_TRANS_CSR_4B_CMD_MASK BIT(21) /* 4 bytes command */
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/**
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* SPIF INT_STS register
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*
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*/
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#define CVI_SPIF_INT_STS_TRANS_DONE_MASK BIT(0)
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#define CVI_SPIF_INT_STS_RD_FIFO_MASK BIT(2)
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/*
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* Note: All registers are mapped into the XIP space:
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* Read access:
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* - If DMMR_EN = 1: Memory contents
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* - If DMMR_EN = 0: Register contents
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* Write access: Register contents (DMMR_EN ignored)
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*
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*/
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struct cvitek_spif_regs {
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u32 spi_ctrl; /* Offset: 0x00 */
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u32 ce_ctrl; /* Offset: 0x04 */
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u32 dly_ctrl; /* Offset: 0x08 */
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u32 dmmr; /* Offset: 0x0C */
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u32 trans_csr; /* Offset: 0x10 */
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u32 trans_num; /* Offset: 0x14 */
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u32 ff_port; /* Offset: 0x18 */
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u32 reserved0; /* Offset: 0x1C */
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u32 ff_pt; /* Offset: 0x20 */
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u32 reserved1; /* Offset: 0x24 */
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u32 int_sts; /* Offset: 0x28 */
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u32 int_en; /* Offset: 0x2C */
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};
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struct cvitek_spif_xfer {
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u8 width; /* Bus width, 0: 1bit, 1: 2bits, 2: 4bits */
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union {
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u8 *in;
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const u8 *out;
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} data;
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u32 length; /* Length in bytes */
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};
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struct cvitek_spif_priv {
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struct cvitek_spif_regs *regs;
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u32 clk_rate;
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unsigned int cs;
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};
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static int cvitek_spif_claim_bus(struct udevice *dev)
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{
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struct cvitek_spif_priv *priv = dev_get_priv(dev->parent);
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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priv->cs = slave_plat->cs;
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if(priv->cs > 0)
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return -ENODEV;
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clrbits_le32(&priv->regs->ce_ctrl, CVI_SPIF_CE_CTRL_CEMANUAL_EN_MASK);
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dev_dbg(dev, "claim_bus cs: %d\n", priv->cs);
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return 0;
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}
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static int cvitek_spif_release_bus(struct udevice *dev)
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{
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struct cvitek_spif_priv *priv = dev_get_priv(dev->parent);
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clrbits_le32(&priv->regs->ce_ctrl, CVI_SPIF_CE_CTRL_CEMANUAL_EN_MASK);
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dev_dbg(dev, "release_bus cs: %d\n", priv->cs);
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return 0;
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}
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static int cvitek_spif_set_speed(struct udevice *bus, uint speed)
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{
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struct cvitek_spif_priv *priv = dev_get_priv(bus);
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u8 div_val = DIV_ROUND_UP(priv->clk_rate, speed) - 1;
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u32 dly_ctrl = CVI_SPIF_DLY_CTRL_CET_MASK;
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clrsetbits_le32(&priv->regs->spi_ctrl,
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CVI_SPIF_SPI_CTRL_SCK_DIV_MASK,
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(div_val << CVI_SPIF_SPI_CTRL_SCK_DIV_SHIFT));
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if(speed > 30000000)
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dly_ctrl |= CVI_SPIF_DLY_CTRL_NEG_SAMPLE_MASK;
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writel(dly_ctrl, &priv->regs->dly_ctrl);
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dev_dbg(bus, "set_speed to %dHz, div: %d\n", speed, div_val);
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return 0;
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}
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static int cvitek_spif_set_mode(struct udevice *bus, uint mode)
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{
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struct cvitek_spif_priv *priv = dev_get_priv(bus);
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u32 mode_mask = 0U;
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if(mode & SPI_CPHA)
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mode_mask |= CVI_SPIF_SPI_CTRL_CPHA_MASK;
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if(mode & SPI_CPOL)
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mode_mask |= CVI_SPIF_SPI_CTRL_CPOL_MASK;
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clrsetbits_le32(&priv->regs->spi_ctrl,
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(CVI_SPIF_SPI_CTRL_CPOL_MASK | CVI_SPIF_SPI_CTRL_CPHA_MASK),
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mode_mask);
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dev_dbg(bus, "set_mode to %d\n", mode);
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return 0;
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}
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static int cvitek_spif_read(struct cvitek_spif_priv *priv, struct cvitek_spif_xfer *xfer)
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{
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u32 trans_ctrl;
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u32 i;
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u8 width;
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switch(xfer->width)
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{
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case 1:
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width = CVI_SPIF_BUS_WIDTH_1;
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break;
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case 2:
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width = CVI_SPIF_BUS_WIDTH_2;
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break;
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case 4:
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width = CVI_SPIF_BUS_WIDTH_4;
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break;
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default:
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return -EINVAL;
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}
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trans_ctrl |= CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL(3);
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trans_ctrl |= CVI_SPIF_TRANS_CSR_BUS_WIDTH(width);
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trans_ctrl |= CVI_SPIF_TRANS_CSR_MODE(1); /* RX mode */
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/* Set up transfer mode */
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writel(trans_ctrl, &priv->regs->trans_csr);
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/* Write transfer length in bytes */
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writel(xfer->length, &priv->regs->trans_num);
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/* Reset FIFO pointer */
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writel(0U, &priv->regs->ff_pt);
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/* Start transfer */
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setbits_le32(&priv->regs->trans_csr, CVI_SPIF_TRANS_CSR_GO_BUSY_MASK);
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for(i = 0; i < xfer->length; i++)
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{
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/* Wait for FIFO not empty */
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while((readl(&priv->regs->ff_pt) & 0x0F) == 0U)
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;
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xfer->data.in[i] = readb(&priv->regs->ff_port);
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}
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while((readl(&priv->regs->int_sts) & CVI_SPIF_INT_STS_TRANS_DONE_MASK) == 0U)
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;
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/* Clear interrupt status */
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writeb(0U, &priv->regs->int_sts);
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return 0;
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}
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static int cvitek_spif_write(struct cvitek_spif_priv *priv, struct cvitek_spif_xfer *xfer)
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{
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u32 trans_ctrl;
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u32 i;
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u8 width;
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switch(xfer->width)
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{
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case 1:
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width = CVI_SPIF_BUS_WIDTH_1;
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break;
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case 2:
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width = CVI_SPIF_BUS_WIDTH_2;
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break;
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case 4:
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width = CVI_SPIF_BUS_WIDTH_4;
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break;
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default:
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return -EINVAL;
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}
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trans_ctrl |= CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL(3);
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trans_ctrl |= CVI_SPIF_TRANS_CSR_BUS_WIDTH(width);
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trans_ctrl |= CVI_SPIF_TRANS_CSR_MODE(2); /* TX mode */
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/* Set up transfer mode */
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writel(trans_ctrl, &priv->regs->trans_csr);
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/* Write transfer length in bytes */
|
||||
writel(xfer->length, &priv->regs->trans_num);
|
||||
|
||||
/* Reset FIFO pointer */
|
||||
writel(0U, &priv->regs->ff_pt);
|
||||
|
||||
/* Start transfer */
|
||||
setbits_le32(&priv->regs->trans_csr, CVI_SPIF_TRANS_CSR_GO_BUSY_MASK);
|
||||
|
||||
for(i = 0; i < xfer->length; i++)
|
||||
{
|
||||
/* Wait for FIFO not full */
|
||||
while((readl(&priv->regs->ff_pt) & 0x0F) >= CVI_SPIF_FIFO_DEPTH)
|
||||
;
|
||||
|
||||
writeb(xfer->data.out[i], &priv->regs->ff_port);
|
||||
}
|
||||
|
||||
|
||||
while((readl(&priv->regs->int_sts) & CVI_SPIF_INT_STS_TRANS_DONE_MASK) == 0U)
|
||||
;
|
||||
|
||||
/* Clear interrupt status */
|
||||
writeb(0U, &priv->regs->int_sts);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cvitek_spif_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
|
||||
{
|
||||
struct cvitek_spif_priv *priv = dev_get_priv(slave->dev->parent);
|
||||
struct cvitek_spif_xfer xfer;
|
||||
u8 buf[4];
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
/* Use manual CE control mode */
|
||||
writel((CVI_SPIF_CE_CTRL_CEMANUAL_MASK | CVI_SPIF_CE_CTRL_CEMANUAL_EN_MASK), &priv->regs->ce_ctrl);
|
||||
|
||||
|
||||
clrbits_le32(&priv->regs->ce_ctrl, CVI_SPIF_CE_CTRL_CEMANUAL_MASK);
|
||||
if(op->cmd.nbytes)
|
||||
{
|
||||
|
||||
if(op->cmd.nbytes == 1U)
|
||||
buf[0] = op->cmd.opcode & 0xFFU;
|
||||
else
|
||||
{
|
||||
buf[0] = (op->cmd.opcode >> 8U) & 0xFFU;
|
||||
buf[1] = op->cmd.opcode & 0xFFU;
|
||||
}
|
||||
|
||||
xfer.data.out = buf;
|
||||
xfer.length = op->cmd.nbytes;
|
||||
xfer.width = op->cmd.buswidth;
|
||||
|
||||
ret = cvitek_spif_write(priv, &xfer);
|
||||
if(ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if(op->addr.nbytes)
|
||||
{
|
||||
if(op->addr.nbytes == 3U)
|
||||
{
|
||||
buf[0] = (op->addr.val >> 16U) & 0xFFU;
|
||||
buf[1] = (op->addr.val >> 8U) & 0xFFU;
|
||||
buf[2] = op->addr.val & 0xFFU;
|
||||
}
|
||||
else if(op->addr.nbytes == 4U)
|
||||
{
|
||||
buf[0] = (op->addr.val >> 24U) & 0xFFU;
|
||||
buf[1] = (op->addr.val >> 16U) & 0xFFU;
|
||||
buf[2] = (op->addr.val >> 8U) & 0xFFU;
|
||||
buf[3] = op->addr.val & 0xFFU;
|
||||
}
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
xfer.data.out = buf;
|
||||
xfer.length = op->addr.nbytes;
|
||||
xfer.width = op->addr.buswidth;
|
||||
|
||||
ret = cvitek_spif_write(priv, &xfer);
|
||||
if(ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if(op->dummy.nbytes)
|
||||
{
|
||||
xfer.data.in = buf;
|
||||
xfer.length = 1;
|
||||
xfer.width = op->dummy.buswidth;
|
||||
|
||||
for(i = 0; i < op->dummy.nbytes; i++)
|
||||
{
|
||||
ret = cvitek_spif_write(priv, &xfer);
|
||||
if(ret < 0)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if(op->data.nbytes && (op->data.dir != SPI_MEM_NO_DATA))
|
||||
{
|
||||
xfer.length = op->data.nbytes;
|
||||
xfer.width = op->data.buswidth;
|
||||
|
||||
if(op->data.dir == SPI_MEM_DATA_IN)
|
||||
{
|
||||
xfer.data.in = op->data.buf.in;
|
||||
ret = cvitek_spif_read(priv, &xfer);
|
||||
}
|
||||
|
||||
if(op->data.dir == SPI_MEM_DATA_OUT)
|
||||
{
|
||||
xfer.data.out = op->data.buf.out;
|
||||
ret = cvitek_spif_write(priv, &xfer);
|
||||
}
|
||||
|
||||
if(ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
setbits_le32(&priv->regs->ce_ctrl, CVI_SPIF_CE_CTRL_CEMANUAL_MASK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cvitek_spif_probe(struct udevice *bus)
|
||||
{
|
||||
int ret;
|
||||
struct clk clk;
|
||||
struct cvitek_spif_priv *priv = dev_get_priv(bus);
|
||||
|
||||
priv->regs = dev_read_addr_ptr(bus);
|
||||
if(!priv->regs)
|
||||
return -EINVAL;
|
||||
|
||||
ret = clk_get_by_index(bus, 0, &clk);
|
||||
if(ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = clk_enable(&clk);
|
||||
if(ret)
|
||||
{
|
||||
dev_err(bus, "failed to enable clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
priv->clk_rate = clk_get_rate(&clk);
|
||||
if(!priv->clk_rate)
|
||||
{
|
||||
dev_err(bus, "failed to get clock rate\n");
|
||||
clk_disable(&clk);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Disable direct memory-mapped mode */
|
||||
writeb(0U, &priv->regs->dmmr);
|
||||
|
||||
dev_dbg(bus, "cvitek-spi probed on addr %p\r\n", priv->regs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct spi_controller_mem_ops cvitek_spif_mem_ops = {
|
||||
.exec_op = cvitek_spif_exec_op,
|
||||
};
|
||||
|
||||
static const struct dm_spi_ops cvitek_spif_ops = {
|
||||
.claim_bus = cvitek_spif_claim_bus,
|
||||
.release_bus = cvitek_spif_release_bus,
|
||||
.set_speed = cvitek_spif_set_speed,
|
||||
.set_mode = cvitek_spif_set_mode,
|
||||
.mem_ops = &cvitek_spif_mem_ops,
|
||||
};
|
||||
|
||||
static const struct udevice_id cvitek_spif_ids[] = {
|
||||
{ .compatible = "cvitek,cvitek-spif" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(cvitek_spif) = {
|
||||
.name = "cvitek_spif",
|
||||
.id = UCLASS_SPI,
|
||||
.of_match = cvitek_spif_ids,
|
||||
.ops = &cvitek_spif_ops,
|
||||
.priv_auto = sizeof(struct cvitek_spif_priv),
|
||||
.probe = cvitek_spif_probe,
|
||||
};
|
||||
Loading…
Reference in New Issue