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Subtree merge tag 'v6.8-dts' of devicetree-rebasing repo [1] into dts/upstream 

[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/
This commit is contained in:
Tom Rini 2024-04-01 09:08:13 -04:00
parent 27795dd717 93743d241c
commit bc39e06778
1311 changed files with 67710 additions and 8579 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
dts/upstream/Bindings/Makefile
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@ -28,7 +28,10 @@ $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name 'processed-schema*' \)
find_cmd = $(find_all_cmd) | grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))"
find_cmd = $(find_all_cmd) | \
sed 's|^$(srctree)/||' | \
grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))" | \
sed 's|^|$(srctree)/|'
CHK_DT_DOCS := $(shell $(find_cmd))
quiet_cmd_yamllint = LINT $(src)

2
dts/upstream/Bindings/arm/calxeda/l2ecc.yaml
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@ -16,7 +16,7 @@ maintainers:
properties:
compatible:
const: "calxeda,hb-sregs-l2-ecc"
const: calxeda,hb-sregs-l2-ecc
reg:
maxItems: 1

1
dts/upstream/Bindings/arm/cpus.yaml
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@ -198,6 +198,7 @@ properties:
- qcom,kryo660
- qcom,kryo685
- qcom,kryo780
- qcom,oryon
- qcom,scorpion
enable-method:

22
dts/upstream/Bindings/arm/fsl.yaml
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@ -967,6 +967,7 @@ properties:
- menlo,mx8menlo # Verdin iMX8M Mini Module on i.MX8MM Menlo board
- toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
- toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board
- toradex,verdin-imx8mm-nonwifi-mallow # Verdin iMX8M Mini Module on Mallow
- toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia
- const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
@ -977,6 +978,7 @@ properties:
- enum:
- toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
- toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
- toradex,verdin-imx8mm-wifi-mallow # Verdin iMX8M Mini Wi-Fi / BT Module on Mallow
- toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia
- const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
@ -1022,7 +1024,10 @@ properties:
- description: Variscite VAR-SOM-MX8MN based boards
items:
- const: variscite,var-som-mx8mn-symphony
- enum:
- dimonoff,gateway-evk # i.MX8MN Dimonoff Gateway EVK Board
- rve,rve-gateway # i.MX8MN RVE Gateway Board
- variscite,var-som-mx8mn-symphony
- const: variscite,var-som-mx8mn
- const: fsl,imx8mn
@ -1048,6 +1053,9 @@ properties:
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
@ -1100,6 +1108,7 @@ properties:
- enum:
- toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
- toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board
- toradex,verdin-imx8mp-nonwifi-mallow # Verdin iMX8M Plus Module on Mallow
- toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia
- const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
@ -1110,6 +1119,7 @@ properties:
- enum:
- toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
- toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
- toradex,verdin-imx8mp-wifi-mallow # Verdin iMX8M Plus Wi-Fi / BT Module on Mallow
- toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia
- const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
@ -1476,6 +1486,16 @@ properties:
- const: solidrun,lx2162a-som
- const: fsl,lx2160a
- description:
TQ-Systems TQMLX2160A is a series of socketable SOM featuring
LX2160A system-on-chip variants. MBLX2160A mainboard can be used a
starterkit.
items:
- enum:
- tq,lx2160a-tqmlx2160a-mblx2160a
- const: tq,lx2160a-tqmlx2160a
- const: fsl,lx2160a
- description: S32G2 based Boards
items:
- enum:

53
dts/upstream/Bindings/arm/google.yaml Normal file
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@ -0,0 +1,53 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/google.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Google Tensor platforms
maintainers:
- Peter Griffin <peter.griffin@linaro.org>
description: |
ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
devices.
Currently upstream this is devices using "gs101" SoC which is found in Pixel
6, Pixel 6 Pro and Pixel 6a.
Google have a few different names for the SoC:
- Marketing name ("Tensor")
- Codename ("Whitechapel")
- SoC ID ("gs101")
- Die ID ("S5P9845")
Likewise there are a couple of names for the actual device
- Marketing name ("Pixel 6")
- Codename ("Oriole")
Devicetrees should use the lowercased SoC ID and lowercased board codename,
e.g. gs101 and gs101-oriole.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Google Pixel 6 / Oriole
items:
- enum:
- google,gs101-oriole
- const: google,gs101
# Bootloader requires empty ect node to be present
ect:
type: object
additionalProperties: false
required:
- ect
additionalProperties: true
...

17
dts/upstream/Bindings/arm/hisilicon/controller/sysctrl.yaml
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@ -82,6 +82,23 @@ properties:
ranges: true
patternProperties:
'^clock@':
type: object
additionalProperties: false
properties:
compatible:
enum:
- hisilicon,hi3620-clock
- hisilicon,hi3620-mmc-clock
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg

22
dts/upstream/Bindings/arm/marvell/armada-7k-8k.yaml
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@ -60,4 +60,26 @@ properties:
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807
- description:
Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
Armada CN9130 COM Express CPU module
items:
- const: marvell,cn9130-ac5x-carrier
- const: marvell,rd-ac5x-carrier
- const: marvell,cn9130-cpu-module
- const: marvell,cn9130
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807
- description:
Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
Armada CN9131 COM Express CPU module
items:
- const: marvell,cn9131-ac5x-carrier
- const: marvell,rd-ac5x-carrier
- const: marvell,cn9131-cpu-module
- const: marvell,cn9131
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807
additionalProperties: true

25
dts/upstream/Bindings/arm/mediatek.yaml
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@ -174,6 +174,10 @@ properties:
- enum:
- mediatek,mt8186-evb
- const: mediatek,mt8186
- items:
- enum:
- mediatek,mt8188-evb
- const: mediatek,mt8188
- items:
- enum:
- mediatek,mt8192-evb
@ -235,6 +239,13 @@ properties:
items:
- const: google,kappa
- const: mediatek,mt8183
- description: Google Katsu (ASUS Chromebook Detachable CZ1)
items:
- enum:
- google,katsu-sku32
- google,katsu-sku38
- const: google,katsu
- const: mediatek,mt8183
- description: Google Kodama (Lenovo 10e Chromebook Tablet)
items:
- enum:
@ -244,6 +255,20 @@ properties:
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
- description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2)
items:
- enum:
- google,makomo-sku0
- google,makomo-sku1
- const: google,makomo
- const: mediatek,mt8183
- description: Google Pico (Acer Chromebook Spin 311)
items:
- enum:
- google,pico-sku1
- google,pico-sku2
- const: google,pico
- const: mediatek,mt8183
- description: Google Willow (Acer Chromebook 311 C722/C722T)
items:
- enum:

39
dts/upstream/Bindings/arm/mediatek/mediatek,audsys.txt
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@ -1,39 +0,0 @@
MediaTek AUDSYS controller
============================
The MediaTek AUDSYS controller provides various clocks to the system.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt6765-audsys", "syscon"
- "mediatek,mt6779-audio", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt8167-audiosys", "syscon"
- "mediatek,mt8183-audiosys", "syscon"
- "mediatek,mt8192-audsys", "syscon"
- "mediatek,mt8516-audsys", "syscon"
- #clock-cells: Must be 1
The AUDSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Required sub-nodes:
-------
For common binding part and usage, refer to
../sonud/mt2701-afe-pcm.txt.
Example:
audsys: clock-controller@11220000 {
compatible = "mediatek,mt7622-audsys", "syscon";
reg = <0 0x11220000 0 0x2000>;
#clock-cells = <1>;
afe: audio-controller {
...
};
};

153
dts/upstream/Bindings/arm/mediatek/mediatek,audsys.yaml Normal file
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@ -0,0 +1,153 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek AUDSYS controller
maintainers:
- Eugen Hristev <eugen.hristev@collabora.com>
description:
The MediaTek AUDSYS controller provides various clocks to the system.
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-audsys
- mediatek,mt6765-audsys
- mediatek,mt6779-audsys
- mediatek,mt7622-audsys
- mediatek,mt8167-audsys
- mediatek,mt8173-audsys
- mediatek,mt8183-audsys
- mediatek,mt8186-audsys
- mediatek,mt8192-audsys
- mediatek,mt8516-audsys
- const: syscon
- items:
# Special case for mt7623 for backward compatibility
- const: mediatek,mt7623-audsys
- const: mediatek,mt2701-audsys
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
audio-controller:
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
type: object
required:
- compatible
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/clock/mt2701-clk.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
audsys: clock-controller@11220000 {
compatible = "mediatek,mt7622-audsys", "syscon";
reg = <0 0x11220000 0 0x2000>;
#clock-cells = <1>;
afe: audio-controller {
compatible = "mediatek,mt2701-audio";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&audsys CLK_AUD_I2SO1>,
<&audsys CLK_AUD_I2SO2>,
<&audsys CLK_AUD_I2SO3>,
<&audsys CLK_AUD_I2SO4>,
<&audsys CLK_AUD_I2SIN1>,
<&audsys CLK_AUD_I2SIN2>,
<&audsys CLK_AUD_I2SIN3>,
<&audsys CLK_AUD_I2SIN4>,
<&audsys CLK_AUD_ASRCO1>,
<&audsys CLK_AUD_ASRCO2>,
<&audsys CLK_AUD_ASRCO3>,
<&audsys CLK_AUD_ASRCO4>,
<&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_AFE_CONN>,
<&audsys CLK_AUD_A1SYS>,
<&audsys CLK_AUD_A2SYS>,
<&audsys CLK_AUD_AFE_MRGIF>;
clock-names = "infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
"top_audio_a1sys_hp",
"top_audio_a2sys_hp",
"i2s0_src_sel",
"i2s1_src_sel",
"i2s2_src_sel",
"i2s3_src_sel",
"i2s0_src_div",
"i2s1_src_div",
"i2s2_src_div",
"i2s3_src_div",
"i2s0_mclk_en",
"i2s1_mclk_en",
"i2s2_mclk_en",
"i2s3_mclk_en",
"i2so0_hop_ck",
"i2so1_hop_ck",
"i2so2_hop_ck",
"i2so3_hop_ck",
"i2si0_hop_ck",
"i2si1_hop_ck",
"i2si2_hop_ck",
"i2si3_hop_ck",
"asrc0_out_ck",
"asrc1_out_ck",
"asrc2_out_ck",
"asrc3_out_ck",
"audio_afe_pd",
"audio_afe_conn_pd",
"audio_a1sys_pd",
"audio_a2sys_pd",
"audio_mrgif_pd";
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>;
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
<&topckgen CLK_TOP_AUD2PLL_90M>;
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
};
};
};

29
dts/upstream/Bindings/arm/mediatek/mediatek,ethsys.txt
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@ -1,29 +0,0 @@
Mediatek ethsys controller
============================
The Mediatek ethsys controller provides various clocks to the system.
Required Properties:
- compatible: Should be:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7629-ethsys", "syscon"
- "mediatek,mt7981-ethsys", "syscon"
- "mediatek,mt7986-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

1
dts/upstream/Bindings/arm/mediatek/mediatek,infracfg.yaml
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@ -30,6 +30,7 @@ properties:
- mediatek,mt7629-infracfg
- mediatek,mt7981-infracfg
- mediatek,mt7986-infracfg
- mediatek,mt7988-infracfg
- mediatek,mt8135-infracfg
- mediatek,mt8167-infracfg
- mediatek,mt8173-infracfg

3
dts/upstream/Bindings/arm/mediatek/mediatek,mmsys.yaml
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@ -32,6 +32,9 @@ properties:
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8188-vdosys0
- mediatek,mt8188-vdosys1
- mediatek,mt8188-vppsys0
- mediatek,mt8188-vppsys1
- mediatek,mt8192-mmsys
- mediatek,mt8195-vdosys1
- mediatek,mt8195-vppsys0

1
dts/upstream/Bindings/arm/mediatek/mediatek,pericfg.yaml
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@ -28,6 +28,7 @@ properties:
- mediatek,mt8173-pericfg
- mediatek,mt8183-pericfg
- mediatek,mt8186-pericfg
- mediatek,mt8188-pericfg
- mediatek,mt8195-pericfg
- mediatek,mt8516-pericfg
- const: syscon

84
dts/upstream/Bindings/arm/msm/qcom,idle-state.txt
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@ -1,84 +0,0 @@
QCOM Idle States for cpuidle driver
ARM provides idle-state node to define the cpuidle states, as defined in [1].
cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
states. Idle states have different enter/exit latency and residency values.
The idle states supported by the QCOM SoC are defined as -
* Standby
* Retention
* Standalone Power Collapse (Standalone PC or SPC)
* Power Collapse (PC)
Standby: Standby does a little more in addition to architectural clock gating.
When the WFI instruction is executed the ARM core would gate its internal
clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
trigger to execute the SPM state machine. The SPM state machine waits for the
interrupt to trigger the core back in to active. This triggers the cache
hierarchy to enter standby states, when all cpus are idle. An interrupt brings
the SPM state machine out of its wait, the next step is to ensure that the
cache hierarchy is also out of standby, and then the cpu is allowed to resume
execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
driver and is not defined in the DT. The SPM state machine should be
configured to execute this state by default and after executing every other
state below.
Retention: Retention is a low power state where the core is clock gated and
the memory and the registers associated with the core are retained. The
voltage may be reduced to the minimum value needed to keep the processor
registers active. The SPM should be configured to execute the retention
sequence and would wait for interrupt, before restoring the cpu to execution
state. Retention may have a slightly higher latency than Standby.
Standalone PC: A cpu can power down and warmboot if there is a sufficient time
between the time it enters idle and the next known wake up. SPC mode is used
to indicate a core entering a power down state without consulting any other
cpu or the system resources. This helps save power only on that core. The SPM
sequence for this idle state is programmed to power down the supply to the
core, wait for the interrupt, restore power to the core, and ensure the
system state including cache hierarchy is ready before allowing core to
resume. Applying power and resetting the core causes the core to warmboot
back into Elevation Level (EL) which trampolines the control back to the
kernel. Entering a power down state for the cpu, needs to be done by trapping
into a EL. Failing to do so, would result in a crash enforced by the warm boot
code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
be flushed in s/w, before powering down the core.
Power Collapse: This state is similar to the SPC mode, but distinguishes
itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
modes. In a hierarchical power domain SoC, this means L2 and other caches can
be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
voltages reduced, provided all cpus enter this state. Since the span of low
power modes possible at this state is vast, the exit latency and the residency
of this low power mode would be considered high even though at a cpu level,
this essentially is cpu power down. The SPM in this state also may handshake
with the Resource power manager (RPM) processor in the SoC to indicate a
complete application processor subsystem shut down.
The idle-state for QCOM SoCs are distinguished by the compatible property of
the idle-states device node.
The devicetree representation of the idle state should be -
Required properties:
- compatible: Must be one of -
"qcom,idle-state-ret",
"qcom,idle-state-spc",
"qcom,idle-state-pc",
and "arm,idle-state".
Other required and optional properties are specified in [1].
Example:
idle-states {
CPU_SPC: spc {
compatible = "qcom,idle-state-spc", "arm,idle-state";
entry-latency-us = <150>;
exit-latency-us = <200>;
min-residency-us = <2000>;
};
};
[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml

51
dts/upstream/Bindings/arm/qcom,coresight-remote-etm.yaml Normal file
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@ -0,0 +1,51 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/qcom,coresight-remote-etm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
maintainers:
- Jinlong Mao <quic_jinlmao@quicinc.com>
- Tao Zhang <quic_taozha@quicinc.com>
description:
Support for ETM trace collection on remote processor using coresight
framework. Enabling this will allow turning on ETM tracing on remote
processor like modem processor via sysfs and collecting the trace
via coresight TMC sinks.
properties:
compatible:
const: qcom,coresight-remote-etm
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- out-ports
additionalProperties: false
examples:
- |
etm {
compatible = "qcom,coresight-remote-etm";
out-ports {
port {
modem_etm0_out_funnel_modem: endpoint {
remote-endpoint = <&funnel_modem_in_modem_etm0>;
};
};
};
};
...

20
dts/upstream/Bindings/arm/qcom,coresight-tpdm.yaml
View File

@ -44,6 +44,23 @@ properties:
minItems: 1
maxItems: 2
qcom,dsb-element-size:
description:
Specifies the DSB(Discrete Single Bit) element size supported by
the monitor. The associated aggregator will read this size before it
is enabled. DSB element size currently only supports 32-bit and 64-bit.
$ref: /schemas/types.yaml#/definitions/uint8
enum: [32, 64]
qcom,dsb-msrs-num:
description:
Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
registers supported by the monitor. If this property is not configured
or set to 0, it means this DSB TPDM doesn't support MSR.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 32
clocks:
maxItems: 1
@ -77,6 +94,9 @@ examples:
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0684c000 0x1000>;
qcom,dsb-element-size = /bits/ 8 <32>;
qcom,dsb-msrs-num = <16>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";

16
dts/upstream/Bindings/arm/qcom-soc.yaml
View File

@ -23,7 +23,7 @@ description: |
select:
properties:
compatible:
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
required:
- compatible
@ -31,17 +31,17 @@ properties:
compatible:
oneOf:
# Preferred naming style for compatibles of SoC components:
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+(pro)?-.*$"
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
# Legacy namings - variations of existing patterns/compatibles are OK,
# but do not add completely new entries to these:
- pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
- pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
- enum:
- qcom,dsi-ctrl-6g-qcm2290
- qcom,gpucc-sdm630

47
dts/upstream/Bindings/arm/qcom.yaml
View File

@ -87,29 +87,18 @@ description: |
sm8350
sm8450
sm8550
sm8650
x1e80100
The 'board' element must be one of the following strings:
adp
ap-al02-c2
ap-al02-c6
ap-al02-c7
ap-al02-c8
ap-al02-c9
ap-mi01.2
ap-mi01.3
ap-mi01.6
ap-mi01.9
cdp
cp01-c1
dragonboard
hk01
hk10-c1
hk10-c2
idp
liquid
rdp432-c2
mtp
qcp
qrd
rb2
ride
@ -138,7 +127,7 @@ description: |
There are many devices in the list below that run the standard ChromeOS
bootloader setup and use the open source depthcharge bootloader to boot the
OS. These devices do not use the scheme described above. For details, see:
https://docs.kernel.org/arm/google/chromebook-boot-flow.html
https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html
properties:
$nodename:
@ -186,11 +175,24 @@ properties:
- items:
- enum:
- microsoft,dempsey
- microsoft,makepeace
- microsoft,moneypenny
- samsung,s3ve3g
- const: qcom,msm8226
- items:
- enum:
- htc,memul
- microsoft,superman-lte
- microsoft,tesla
- motorola,peregrine
- const: qcom,msm8926
- const: qcom,msm8226
- items:
- enum:
- huawei,kiwi
- longcheer,l9100
- samsung,a7
- sony,kanuti-tulip
@ -397,6 +399,8 @@ properties:
- items:
- enum:
- fairphone,fp5
- qcom,qcm6490-idp
- qcom,qcs6490-rb3gen2
- const: qcom,qcm6490
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
@ -1009,6 +1013,7 @@ properties:
- sony,pdx203-generic
- sony,pdx206-generic
- xiaomi,elish
- xiaomi,pipa
- const: qcom,sm8250
- items:
@ -1034,6 +1039,18 @@ properties:
- qcom,sm8550-qrd
- const: qcom,sm8550
- items:
- enum:
- qcom,sm8650-mtp
- qcom,sm8650-qrd
- const: qcom,sm8650
- items:
- enum:
- qcom,x1e80100-crd
- qcom,x1e80100-qcp
- const: qcom,x1e80100
# Board compatibles go above
qcom,msm-id:

56
dts/upstream/Bindings/arm/rockchip.yaml
View File

@ -30,9 +30,11 @@ properties:
- const: amarula,vyasa-rk3288
- const: rockchip,rk3288
- description: Anbernic RG351M
- description: Anbernic RK3326 Handheld Gaming Console
items:
- const: anbernic,rg351m
- enum:
- anbernic,rg351m
- anbernic,rg351v
- const: rockchip,rk3326
- description: Anbernic RG353P
@ -95,22 +97,30 @@ properties:
- const: chipspark,rayeager-px2
- const: rockchip,rk3066a
- description: Cool Pi Compute Module 5(CM5) EVB
items:
- enum:
- coolpi,pi-cm5-evb
- const: coolpi,pi-cm5
- const: rockchip,rk3588
- description: Cool Pi 4 Model B
items:
- const: coolpi,pi-4b
- const: rockchip,rk3588s
- description: Edgeble Neural Compute Module 2(Neu2) SoM based boards
items:
- const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board
- const: edgeble,neural-compute-module-2 # Edgeble Neural Compute Module 2 SoM
- const: rockchip,rv1126
- description: Edgeble Neural Compute Module 6(Neu6) Model A SoM based boards
- description: Edgeble Neural Compute Module 6(Neu6) SoM based boards
items:
- const: edgeble,neural-compute-module-6a-io # Edgeble Neural Compute Module 6A IO Board
- const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM
- const: rockchip,rk3588
- description: Edgeble Neural Compute Module 6(Neu6) Model B SoM based boards
items:
- const: edgeble,neural-compute-module-6b-io # Edgeble Neural Compute Module 6B IO Board
- const: edgeble,neural-compute-module-6b # Edgeble Neural Compute Module 6B SoM
- const: edgeble,neural-compute-module-6a-io # Edgeble NCM6A-IO Board
- enum:
- edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM
- edgeble,neural-compute-module-6b # Edgeble Neural Compute Module 6B SoM
- const: rockchip,rk3588
- description: Elgin RV1108 R1
@ -237,6 +247,11 @@ properties:
- const: geekbuying,geekbox
- const: rockchip,rk3368
- description: Geniatech XPI-3128
items:
- const: geniatech,xpi-3128
- const: rockchip,rk3128
- description: Google Bob (Asus Chromebook Flip C101PA)
items:
- const: google,bob-rev13
@ -674,9 +689,12 @@ properties:
- const: pine64,soquartz
- const: rockchip,rk3566
- description: Powkiddy RGB30
- description: Powkiddy RK3566 Handheld Gaming Console
items:
- const: powkiddy,rgb30
- enum:
- powkiddy,rgb30
- powkiddy,rk2023
- powkiddy,x55
- const: rockchip,rk3566
- description: Radxa Compute Module 3(CM3)
@ -875,6 +893,11 @@ properties:
- const: tsd,rk3399-puma-haikou
- const: rockchip,rk3399
- description: Theobroma Systems RK3588-SBC Jaguar
items:
- const: tsd,rk3588-jaguar
- const: rockchip,rk3588
- description: Tronsmart Orion R68 Meta
items:
- const: tronsmart,orion-r68-meta
@ -922,6 +945,13 @@ properties:
- const: rockchip,rk3568-bpi-r2pro
- const: rockchip,rk3568
- description: Sonoff iHost Smart Home Hub
items:
- const: itead,sonoff-ihost
- enum:
- rockchip,rv1126
- rockchip,rv1109
additionalProperties: true
...

6
dts/upstream/Bindings/arm/samsung/samsung-boards.yaml
View File

@ -230,6 +230,12 @@ properties:
- samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK
- const: samsung,exynosautov9
- description: Exynos Auto v920 based boards
items:
- enum:
- samsung,exynosautov920-sadk # Samsung Exynos Auto v920 SADK
- const: samsung,exynosautov920
required:
- compatible

5
dts/upstream/Bindings/arm/sprd/sprd.yaml
View File

@ -35,6 +35,11 @@ properties:
- sprd,ums512-1h10
- const: sprd,ums512
- items:
- enum:
- sprd,ums9620-2h10
- const: sprd,ums9620
additionalProperties: true
...

16
dts/upstream/Bindings/arm/stm32/stm32.yaml
View File

@ -82,29 +82,19 @@ properties:
- shiratech,stm32mp157a-iot-box # IoT Box
- shiratech,stm32mp157a-stinger96 # Stinger96
- st,stm32mp157c-ed1
- st,stm32mp157c-ed1-scmi
- st,stm32mp157a-dk1
- st,stm32mp157a-dk1-scmi
- st,stm32mp157c-dk2
- st,stm32mp157c-dk2-scmi
- const: st,stm32mp157
- items:
- const: st,stm32mp157a-dk1-scmi
- const: st,stm32mp157a-dk1
- const: st,stm32mp157
- items:
- const: st,stm32mp157c-dk2-scmi
- const: st,stm32mp157c-dk2
- const: st,stm32mp157
- items:
- const: st,stm32mp157c-ed1-scmi
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
- items:
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
- items:
- const: st,stm32mp157c-ev1-scmi
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157

10
dts/upstream/Bindings/arm/sunxi.yaml
View File

@ -868,6 +868,11 @@ properties:
- const: topwise,a721
- const: allwinner,sun4i-a10
- description: Transpeed 8K618-T
items:
- const: transpeed,8k618-t
- const: allwinner,sun50i-h618
- description: Utoo P66
items:
- const: utoo,p66
@ -1013,6 +1018,11 @@ properties:
- const: xunlong,orangepi-zero2
- const: allwinner,sun50i-h616
- description: Xunlong OrangePi Zero 2W
items:
- const: xunlong,orangepi-zero2w
- const: allwinner,sun50i-h618
- description: Xunlong OrangePi Zero 3
items:
- const: xunlong,orangepi-zero3

2
dts/upstream/Bindings/arm/ti/k3.yaml
View File

@ -50,6 +50,7 @@ properties:
- enum:
- toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia
- toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board
- toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow
- toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia
- const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT
- const: toradex,verdin-am62 # Verdin AM62 Module
@ -60,6 +61,7 @@ properties:
- enum:
- toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia
- toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B.
- toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow
- toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia
- const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module
- const: toradex,verdin-am62 # Verdin AM62 Module

2
dts/upstream/Bindings/arm/ti/omap.yaml
View File

@ -134,6 +134,8 @@ properties:
- amazon,omap4-kc1 # Amazon Kindle Fire (first generation)
- motorola,droid4 # Motorola Droid 4 XT894
- motorola,droid-bionic # Motorola Droid Bionic XT875
- motorola,xyboard-mz609
- motorola,xyboard-mz617
- ti,omap4-panda
- ti,omap4-sdp
- const: ti,omap4430

3
dts/upstream/Bindings/ata/ceva,ahci-1v84.yaml
View File

@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ceva AHCI SATA Controller
maintainers:
- Piyush Mehta <piyush.mehta@amd.com>
- Mubin Sayyed <mubin.sayyed@amd.com>
- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
description: |
The Ceva SATA controller mostly conforms to the AHCI interface with some

2
dts/upstream/Bindings/auxdisplay/hit,hd44780.yaml
View File

@ -113,7 +113,7 @@ examples:
hd44780 {
compatible = "hit,hd44780";
display-height-chars = <2>;
display-width-chars = <16>;
display-width-chars = <16>;
data-gpios = <&pcf8574 4 0>,
<&pcf8574 5 0>,
<&pcf8574 6 0>,

5
dts/upstream/Bindings/cache/qcom,llcc.yaml vendored
View File

@ -33,6 +33,8 @@ properties:
- qcom,sm8350-llcc
- qcom,sm8450-llcc
- qcom,sm8550-llcc
- qcom,sm8650-llcc
- qcom,x1e80100-llcc
reg:
minItems: 2
@ -64,6 +66,7 @@ allOf:
compatible:
contains:
enum:
- qcom,qdu1000-llcc
- qcom,sc7180-llcc
- qcom,sm6350-llcc
then:
@ -101,9 +104,9 @@ allOf:
compatible:
contains:
enum:
- qcom,qdu1000-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
- qcom,x1e80100-llcc
then:
properties:
reg:

6
dts/upstream/Bindings/cache/sifive,ccache0.yaml vendored
View File

@ -38,7 +38,9 @@ properties:
- sifive,fu740-c000-ccache
- const: cache
- items:
- const: starfive,jh7110-ccache
- enum:
- starfive,jh7100-ccache
- starfive,jh7110-ccache
- const: sifive,ccache0
- const: cache
- items:
@ -88,6 +90,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
- starfive,jh7100-ccache
- starfive,jh7110-ccache
- microchip,mpfs-ccache
@ -111,6 +114,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
- starfive,jh7100-ccache
- starfive,jh7110-ccache
then:

2
dts/upstream/Bindings/clock/baikal,bt1-ccu-pll.yaml
View File

@ -125,7 +125,7 @@ examples:
clk25m: clock-oscillator-25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-frequency = <25000000>;
clock-output-names = "clk25m";
};
...

138
dts/upstream/Bindings/clock/brcm,kona-ccu.txt
View File

@ -1,138 +0,0 @@
Broadcom Kona Family Clocks
This binding is associated with Broadcom SoCs having "Kona" style
clock control units (CCUs). A CCU is a clock provider that manages
a set of clock signals. Each CCU is represented by a node in the
device tree.
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible
Shall have a value of the form "brcm,<model>-<which>-ccu",
where <model> is a Broadcom SoC model number and <which> is
the name of a defined CCU. For example:
"brcm,bcm11351-root-ccu"
The compatible strings used for each supported SoC family
are defined below.
- reg
Shall define the base and range of the address space
containing clock control registers
- #clock-cells
Shall have value <1>. The permitted clock-specifier values
are defined below.
- clock-output-names
Shall be an ordered list of strings defining the names of
the clocks provided by the CCU.
Device tree example:
slave_ccu: slave_ccu {
compatible = "brcm,bcm11351-slave-ccu";
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "uartb",
"uartb2",
"uartb3",
"uartb4";
};
ref_crystal_clk: ref_crystal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <26000000>;
};
uart@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
reg = <0x3e002000 0x1000>;
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
BCM281XX family
---------------
CCU compatible string values for SoCs in the BCM281XX family are:
"brcm,bcm11351-root-ccu"
"brcm,bcm11351-aon-ccu"
"brcm,bcm11351-hub-ccu"
"brcm,bcm11351-master-ccu"
"brcm,bcm11351-slave-ccu"
The following table defines the set of CCUs and clock specifiers for
BCM281XX family clocks. When a clock consumer references a clocks,
its symbolic specifier (rather than its numeric index value) should
be used. These specifiers are defined in:
"include/dt-bindings/clock/bcm281xx.h"
CCU Clock Type Index Specifier
--- ----- ---- ----- ---------
root frac_1m peri 0 BCM281XX_ROOT_CCU_FRAC_1M
aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER
aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC
aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR
hub tmon_1m peri 0 BCM281XX_HUB_CCU_TMON_1M
master sdio1 peri 0 BCM281XX_MASTER_CCU_SDIO1
master sdio2 peri 1 BCM281XX_MASTER_CCU_SDIO2
master sdio3 peri 2 BCM281XX_MASTER_CCU_SDIO3
master sdio4 peri 3 BCM281XX_MASTER_CCU_SDIO4
master dmac peri 4 BCM281XX_MASTER_CCU_DMAC
master usb_ic peri 5 BCM281XX_MASTER_CCU_USB_IC
master hsic2_48m peri 6 BCM281XX_MASTER_CCU_HSIC_48M
master hsic2_12m peri 7 BCM281XX_MASTER_CCU_HSIC_12M
slave uartb peri 0 BCM281XX_SLAVE_CCU_UARTB
slave uartb2 peri 1 BCM281XX_SLAVE_CCU_UARTB2
slave uartb3 peri 2 BCM281XX_SLAVE_CCU_UARTB3
slave uartb4 peri 3 BCM281XX_SLAVE_CCU_UARTB4
slave ssp0 peri 4 BCM281XX_SLAVE_CCU_SSP0
slave ssp2 peri 5 BCM281XX_SLAVE_CCU_SSP2
slave bsc1 peri 6 BCM281XX_SLAVE_CCU_BSC1
slave bsc2 peri 7 BCM281XX_SLAVE_CCU_BSC2
slave bsc3 peri 8 BCM281XX_SLAVE_CCU_BSC3
slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM
BCM21664 family
---------------
CCU compatible string values for SoCs in the BCM21664 family are:
"brcm,bcm21664-root-ccu"
"brcm,bcm21664-aon-ccu"
"brcm,bcm21664-master-ccu"
"brcm,bcm21664-slave-ccu"
The following table defines the set of CCUs and clock specifiers for
BCM21664 family clocks. When a clock consumer references a clocks,
its symbolic specifier (rather than its numeric index value) should
be used. These specifiers are defined in:
"include/dt-bindings/clock/bcm21664.h"
CCU Clock Type Index Specifier
--- ----- ---- ----- ---------
root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M
aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1
master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2
master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3
master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4
master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP
master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP
master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP
master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP
slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB
slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2
slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3
slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4
slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1
slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2
slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3
slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4

181
dts/upstream/Bindings/clock/brcm,kona-ccu.yaml Normal file
View File

@ -0,0 +1,181 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,kona-ccu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Kona family clock control units (CCU)
maintainers:
- Florian Fainelli <florian.fainelli@broadcom.com>
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
description: |
Broadcom "Kona" style clock control unit (CCU) is a clock provider that
manages a set of clock signals.
All available clock IDs are defined in
- include/dt-bindings/clock/bcm281xx.h for BCM281XX family
- include/dt-bindings/clock/bcm21664.h for BCM21664 family
properties:
compatible:
enum:
- brcm,bcm11351-aon-ccu
- brcm,bcm11351-hub-ccu
- brcm,bcm11351-master-ccu
- brcm,bcm11351-root-ccu
- brcm,bcm11351-slave-ccu
- brcm,bcm21664-aon-ccu
- brcm,bcm21664-master-ccu
- brcm,bcm21664-root-ccu
- brcm,bcm21664-slave-ccu
reg:
maxItems: 1
'#clock-cells':
const: 1
clock-output-names:
minItems: 1
maxItems: 10
required:
- compatible
- reg
- '#clock-cells'
- clock-output-names
allOf:
- if:
properties:
compatible:
contains:
const: brcm,bcm11351-aon-ccu
then:
properties:
clock-output-names:
items:
- const: hub_timer
- const: pmu_bsc
- const: pmu_bsc_var
- if:
properties:
compatible:
contains:
const: brcm,bcm11351-hub-ccu
then:
properties:
clock-output-names:
const: tmon_1m
- if:
properties:
compatible:
contains:
const: brcm,bcm11351-master-ccu
then:
properties:
clock-output-names:
items:
- const: sdio1
- const: sdio2
- const: sdio3
- const: sdio4
- const: usb_ic
- const: hsic2_48m
- const: hsic2_12m
- if:
properties:
compatible:
contains:
enum:
- brcm,bcm11351-root-ccu
- brcm,bcm21664-root-ccu
then:
properties:
clock-output-names:
const: frac_1m
- if:
properties:
compatible:
contains:
const: brcm,bcm11351-slave-ccu
then:
properties:
clock-output-names:
items:
- const: uartb
- const: uartb2
- const: uartb3
- const: uartb4
- const: ssp0
- const: ssp2
- const: bsc1
- const: bsc2
- const: bsc3
- const: pwm
- if:
properties:
compatible:
contains:
const: brcm,bcm21664-aon-ccu
then:
properties:
clock-output-names:
const: hub_timer
- if:
properties:
compatible:
contains:
const: brcm,bcm21664-master-ccu
then:
properties:
clock-output-names:
items:
- const: sdio1
- const: sdio2
- const: sdio3
- const: sdio4
- const: sdio1_sleep
- const: sdio2_sleep
- const: sdio3_sleep
- const: sdio4_sleep
- if:
properties:
compatible:
contains:
const: brcm,bcm21664-slave-ccu
then:
properties:
clock-output-names:
items:
- const: uartb
- const: uartb2
- const: uartb3
- const: bsc1
- const: bsc2
- const: bsc3
- const: bsc4
additionalProperties: false
examples:
- |
clock-controller@3e011000 {
compatible = "brcm,bcm11351-slave-ccu";
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "uartb",
"uartb2",
"uartb3",
"uartb4",
"ssp0",
"ssp2",
"bsc1",
"bsc2",
"bsc3",
"pwm";
};
...

42
dts/upstream/Bindings/clock/fsl,imx93-anatop.yaml Normal file
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@ -0,0 +1,42 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,imx93-anatop.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX93 ANATOP Clock Module
maintainers:
- Peng Fan <peng.fan@nxp.com>
description: |
NXP i.MX93 ANATOP module which contains PLL and OSC to Clock Controller
Module.
properties:
compatible:
items:
- const: fsl,imx93-anatop
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@44480000 {
compatible = "fsl,imx93-anatop";
reg = <0x44480000 0x2000>;
#clock-cells = <1>;
};
...

106
dts/upstream/Bindings/clock/google,gs101-clock.yaml Normal file
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@ -0,0 +1,106 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Google GS101 SoC clock controller
maintainers:
- Peter Griffin <peter.griffin@linaro.org>
description: |
Google GS101 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. The root clock in that clock tree
is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
clock in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'dt-bindings/clock/gs101.h' header.
properties:
compatible:
enum:
- google,gs101-cmu-top
- google,gs101-cmu-apm
- google,gs101-cmu-misc
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
"#clock-cells":
const: 1
reg:
maxItems: 1
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- google,gs101-cmu-top
- google,gs101-cmu-apm
then:
properties:
clocks:
items:
- description: External reference clock (24.576 MHz)
clock-names:
items:
- const: oscclk
- if:
properties:
compatible:
contains:
const: google,gs101-cmu-misc
then:
properties:
clocks:
items:
- description: Misc bus clock (from CMU_TOP)
- description: Misc sss clock (from CMU_TOP)
clock-names:
items:
- const: bus
- const: sss
additionalProperties: false
examples:
# Clock controller node for CMU_TOP
- |
#include <dt-bindings/clock/google,gs101.h>
cmu_top: clock-controller@1e080000 {
compatible = "google,gs101-cmu-top";
reg = <0x1e080000 0x8000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>;
clock-names = "oscclk";
};
...

20
dts/upstream/Bindings/clock/hi3620-clock.txt
View File

@ -1,20 +0,0 @@
* Hisilicon Hi3620 Clock Controller
The Hi3620 clock controller generates and supplies clock to various
controllers within the Hi3620 SoC.
Required Properties:
- compatible: should be one of the following.
- "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
- "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hi3620-clock.h>.

1
dts/upstream/Bindings/clock/mediatek,apmixedsys.yaml
View File

@ -22,6 +22,7 @@ properties:
- mediatek,mt7622-apmixedsys
- mediatek,mt7981-apmixedsys
- mediatek,mt7986-apmixedsys
- mediatek,mt7988-apmixedsys
- mediatek,mt8135-apmixedsys
- mediatek,mt8173-apmixedsys
- mediatek,mt8516-apmixedsys

55
dts/upstream/Bindings/clock/mediatek,ethsys.yaml Normal file
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@ -0,0 +1,55 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek ethsys controller
description:
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
maintainers:
- James Liao <jamesjj.liao@mediatek.com>
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-ethsys
- mediatek,mt7622-ethsys
- mediatek,mt7629-ethsys
- mediatek,mt7981-ethsys
- mediatek,mt7986-ethsys
- mediatek,mt7988-ethsys
- const: syscon
- items:
- const: mediatek,mt7623-ethsys
- const: mediatek,mt2701-ethsys
- const: syscon
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
required:
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
clock-controller@1b000000 {
compatible = "mediatek,mt2701-ethsys", "syscon";
reg = <0x1b000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

52
dts/upstream/Bindings/clock/mediatek,mt7988-ethwarp.yaml Normal file
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@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT7988 ethwarp Controller
maintainers:
- Daniel Golle <daniel@makrotopia.org>
description:
The Mediatek MT7988 ethwarp controller provides clocks and resets for the
Ethernet related subsystems found the MT7988 SoC.
The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
properties:
compatible:
items:
- const: mediatek,mt7988-ethwarp
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/reset/ti-syscon.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@15031000 {
compatible = "mediatek,mt7988-ethwarp";
reg = <0 0x15031000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};

48
dts/upstream/Bindings/clock/mediatek,mt7988-xfi-pll.yaml Normal file
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@ -0,0 +1,48 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT7988 XFI PLL Clock Controller
maintainers:
- Daniel Golle <daniel@makrotopia.org>
description:
The MediaTek XFI PLL controller provides the 156.25MHz clock for the
Ethernet SerDes PHY from the 40MHz top_xtal clock.
properties:
compatible:
const: mediatek,mt7988-xfi-pll
reg:
maxItems: 1
resets:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- resets
- '#clock-cells'
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
resets = <&watchdog 16>;
#clock-cells = <1>;
};
};

2
dts/upstream/Bindings/clock/mediatek,mt8188-clock.yaml
View File

@ -43,8 +43,6 @@ properties:
- mediatek,mt8188-vdecsys
- mediatek,mt8188-vdecsys-soc
- mediatek,mt8188-vencsys
- mediatek,mt8188-vppsys0
- mediatek,mt8188-vppsys1
- mediatek,mt8188-wpesys
- mediatek,mt8188-wpesys-vpp0

2
dts/upstream/Bindings/clock/mediatek,topckgen.yaml
View File

@ -37,6 +37,8 @@ properties:
- mediatek,mt7629-topckgen
- mediatek,mt7981-topckgen
- mediatek,mt7986-topckgen
- mediatek,mt7988-mcusys
- mediatek,mt7988-topckgen
- mediatek,mt8167-topckgen
- mediatek,mt8183-topckgen
- const: syscon

1
dts/upstream/Bindings/clock/qcom,a53pll.yaml
View File

@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
- qcom,ipq5018-a53pll
- qcom,ipq5332-a53pll
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll

18
dts/upstream/Bindings/clock/qcom,camcc-sm8250.yaml
View File

@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sm8250-camcc
@ -33,15 +36,6 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
power-domains:
items:
- description: MMCX power domain
@ -56,14 +50,10 @@ properties:
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

57
dts/upstream/Bindings/clock/qcom,gcc-ipq6018.yaml Normal file
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@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq6018.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ6018
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
- Robert Marko <robimarko@gmail.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ6018.
See also::
include/dt-bindings/clock/qcom,gcc-ipq6018.h
include/dt-bindings/reset/qcom,gcc-ipq6018.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,gcc-ipq6018
clocks:
items:
- description: board XO clock
- description: sleep clock
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,gcc-ipq6018";
reg = <0x01800000 0x80000>;
clocks = <&xo>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...

4
dts/upstream/Bindings/clock/qcom,gcc-ipq8074.yaml
View File

@ -27,11 +27,15 @@ properties:
items:
- description: board XO clock
- description: sleep clock
- description: Gen3 QMP PCIe PHY PIPE clock
- description: Gen2 QMP PCIe PHY PIPE clock
clock-names:
items:
- const: xo
- const: sleep_clk
- const: pcie0_pipe
- const: pcie1_pipe
required:
- compatible

3
dts/upstream/Bindings/clock/qcom,gcc-other.yaml
View File

@ -15,8 +15,6 @@ description: |
domains.
See also::
include/dt-bindings/clock/qcom,gcc-ipq6018.h
include/dt-bindings/reset/qcom,gcc-ipq6018.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
include/dt-bindings/clock/qcom,gcc-mdm9607.h
@ -26,7 +24,6 @@ allOf:
properties:
compatible:
enum:
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
required:

68
dts/upstream/Bindings/clock/qcom,qdu1000-ecpricc.yaml Normal file
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@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
- Imran Shaik <quic_imrashai@quicinc.com>
description: |
Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control
module which supports the clocks, resets on QDU1000 and QRU1000
See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
properties:
compatible:
enum:
- qcom,qdu1000-ecpricc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: GPLL0 source from GCC
- description: GPLL1 source from GCC
- description: GPLL2 source from GCC
- description: GPLL3 source from GCC
- description: GPLL4 source from GCC
- description: GPLL5 source from GCC
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,qdu1000-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@280000 {
compatible = "qcom,qdu1000-ecpricc";
reg = <0x00280000 0x31c00>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
<&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
};

2
dts/upstream/Bindings/clock/qcom,rpmhcc.yaml
View File

@ -35,6 +35,8 @@ properties:
- qcom,sm8350-rpmh-clk
- qcom,sm8450-rpmh-clk
- qcom,sm8550-rpmh-clk
- qcom,sm8650-rpmh-clk
- qcom,x1e80100-rpmh-clk
clocks:
maxItems: 1

18
dts/upstream/Bindings/clock/qcom,sc7180-camcc.yaml
View File

@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sc7180-camcc
@ -31,28 +34,15 @@ properties:
- const: iface
- const: xo
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

18
dts/upstream/Bindings/clock/qcom,sc7280-camcc.yaml
View File

@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sc7280-camcc
@ -31,28 +34,15 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

18
dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml
View File

@ -15,6 +15,9 @@ description: |
See also:: include/dt-bindings/clock/qcom,camcc-sm845.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sdm845-camcc
@ -27,28 +30,15 @@ properties:
items:
- const: bi_tcxo
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

20
dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
View File

@ -16,10 +16,15 @@ description: |
See also::
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
enum:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
@ -40,29 +45,16 @@ properties:
description:
A phandle to an OPP node describing required MMCX performance point.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- power-domains
- required-opps
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

2
dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
View File

@ -17,12 +17,14 @@ description: |
include/dt-bindings/clock/qcom,sm8450-gpucc.h
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
include/dt-bindings/reset/qcom,sm8650-gpucc.h
properties:
compatible:
enum:
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
clocks:
items:

8
dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml
View File

@ -13,12 +13,16 @@ description: |
Qualcomm TCSR clock control module provides the clocks, resets and
power domains on SM8550
See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
See also:
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
properties:
compatible:
items:
- const: qcom,sm8550-tcsr
- enum:
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- const: syscon
clocks:

106
dts/upstream/Bindings/clock/qcom,sm8650-dispcc.yaml Normal file
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@ -0,0 +1,106 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller for SM8650
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8650.
See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
properties:
compatible:
enum:
- qcom,sm8650-dispcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Display's AHB clock
- description: sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
- description: Link clock from DP PHY1
- description: VCO DIV clock from DP PHY1
- description: Link clock from DP PHY2
- description: VCO DIV clock from DP PHY2
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8650-dispcc";
reg = <0x0af00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
<&dp0_phy 0>,
<&dp0_phy 1>,
<&dp1_phy 0>,
<&dp1_phy 1>,
<&dp2_phy 0>,
<&dp2_phy 1>,
<&dp3_phy 0>,
<&dp3_phy 1>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

65
dts/upstream/Bindings/clock/qcom,sm8650-gcc.yaml Normal file
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@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM8650
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8650
See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h
properties:
compatible:
const: qcom,sm8650-gcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 1 Pipe clock source
- description: PCIE 1 Phy Auxiliary clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm8650-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&pcie0_phy>,
<&pcie1_phy>,
<&pcie_1_phy_aux_clk>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

72
dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml Normal file
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@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on X1E80100
maintainers:
- Rajendra Nayak <quic_rjendra@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on X1E80100
See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h
properties:
compatible:
const: qcom,x1e80100-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIe 3 pipe clock
- description: PCIe 4 pipe clock
- description: PCIe 5 pipe clock
- description: PCIe 6a pipe clock
- description: PCIe 6b pipe clock
- description: USB QMP Phy 0 clock source
- description: USB QMP Phy 1 clock source
- description: USB QMP Phy 2 clock source
power-domains:
description:
A phandle and PM domain specifier for the CX power domain.
maxItems: 1
required:
- compatible
- clocks
- power-domains
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,x1e80100-gcc";
reg = <0x00100000 0x200000>;
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
<&pcie3_phy>,
<&pcie4_phy>,
<&pcie5_phy>,
<&pcie6a_phy>,
<&pcie6b_phy>,
<&usb_1_ss0_qmpphy 0>,
<&usb_1_ss1_qmpphy 1>,
<&usb_1_ss2_qmpphy 2>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

10
dts/upstream/Bindings/clock/renesas,9series.yaml
View File

@ -21,6 +21,15 @@ description: |
1 -- DIF1
2 -- DIF2
3 -- DIF3
- 9FGV0841:
0 -- DIF0
1 -- DIF1
2 -- DIF2
3 -- DIF3
4 -- DIF4
5 -- DIF5
6 -- DIF6
7 -- DIF7
maintainers:
- Marek Vasut <marex@denx.de>
@ -30,6 +39,7 @@ properties:
enum:
- renesas,9fgv0241
- renesas,9fgv0441
- renesas,9fgv0841
reg:
description: I2C device address

126
dts/upstream/Bindings/clock/silabs,si5351.txt
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@ -1,126 +0,0 @@
Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
Reference
[1] Si5351A/B/C Data Sheet
https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
The Si5351a/b/c are programmable i2c clock generators with up to 8 output
clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
3 output clocks are accessible. The internal structure of the clock
generators can be found in [1].
==I2C device node==
Required properties:
- compatible: shall be one of the following:
"silabs,si5351a" - Si5351a, QFN20 package
"silabs,si5351a-msop" - Si5351a, MSOP10 package
"silabs,si5351b" - Si5351b, QFN20 package
"silabs,si5351c" - Si5351c, QFN20 package
- reg: i2c device address, shall be 0x60 or 0x61.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock
handles, shall be xtal reference clock or xtal and clkin for
si5351c only. Corresponding clock input names are "xtal" and
"clkin" respectively.
- #address-cells: shall be set to 1.
- #size-cells: shall be set to 0.
Optional properties:
- silabs,pll-source: pair of (number, source) for each pll. Allows
to overwrite clock source of pll A (number=0) or B (number=1).
==Child nodes==
Each of the clock outputs can be overwritten individually by
using a child node to the I2C device node. If a child node for a clock
output is not set, the eeprom configuration is not overwritten.
Required child node properties:
- reg: number of clock output.
Optional child node properties:
- silabs,clock-source: source clock of the output divider stage N, shall be
0 = multisynth N
1 = multisynth 0 for output clocks 0-3, else multisynth4
2 = xtal
3 = clkin (si5351c only)
- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
divider.
- silabs,pll-master: boolean, multisynth can change pll frequency.
- silabs,pll-reset: boolean, clock output can reset its pll.
- silabs,disable-state : clock output disable state, shall be
0 = clock output is driven LOW when disabled
1 = clock output is driven HIGH when disabled
2 = clock output is FLOATING (HIGH-Z) when disabled
3 = clock output is NEVER disabled
==Example==
/* 25MHz reference crystal */
ref25: ref25M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
i2c-master-node {
/* Si5351a msop10 i2c clock generator */
si5351a: clock-generator@60 {
compatible = "silabs,si5351a-msop";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
/* connect xtal input to 25MHz reference */
clocks = <&ref25>;
clock-names = "xtal";
/* connect xtal input as source of pll0 and pll1 */
silabs,pll-source = <0 0>, <1 0>;
/*
* overwrite clkout0 configuration with:
* - 8mA output drive strength
* - pll0 as clock source of multisynth0
* - multisynth0 as clock source of output divider
* - multisynth0 can change pll0
* - set initial clock frequency of 74.25MHz
*/
clkout0 {
reg = <0>;
silabs,drive-strength = <8>;
silabs,multisynth-source = <0>;
silabs,clock-source = <0>;
silabs,pll-master;
clock-frequency = <74250000>;
};
/*
* overwrite clkout1 configuration with:
* - 4mA output drive strength
* - pll1 as clock source of multisynth1
* - multisynth1 as clock source of output divider
* - multisynth1 can change pll1
*/
clkout1 {
reg = <1>;
silabs,drive-strength = <4>;
silabs,multisynth-source = <1>;
silabs,clock-source = <0>;
pll-master;
};
/*
* overwrite clkout2 configuration with:
* - xtal as clock source of output divider
*/
clkout2 {
reg = <2>;
silabs,clock-source = <2>;
};
};
};

265
dts/upstream/Bindings/clock/silabs,si5351.yaml Normal file
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@ -0,0 +1,265 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/silabs,si5351.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Silicon Labs Si5351A/B/C programmable I2C clock generators
description: |
The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to
8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
output clocks are accessible. The internal structure of the clock generators
can be found in [1].
[1] Si5351A/B/C Data Sheet
https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
maintainers:
- Alvin Šipraga <alsi@bang-olufsen.dk>
properties:
compatible:
enum:
- silabs,si5351a # Si5351A, 20-QFN package
- silabs,si5351a-msop # Si5351A, 10-MSOP package
- silabs,si5351b # Si5351B, 20-QFN package
- silabs,si5351c # Si5351C, 20-QFN package
reg:
enum:
- 0x60
- 0x61
"#address-cells":
const: 1
"#size-cells":
const: 0
"#clock-cells":
const: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: xtal
- const: clkin
silabs,pll-source:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description: |
A list of cell pairs containing a PLL index and its source. Allows to
overwrite clock source of the internal PLLs.
items:
items:
- description: PLL A (0) or PLL B (1)
enum: [ 0, 1 ]
- description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
enum: [ 0, 1 ]
silabs,pll-reset-mode:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 1
maxItems: 2
description: A list of cell pairs containing a PLL index and its reset mode.
items:
items:
- description: PLL A (0) or PLL B (1)
enum: [ 0, 1 ]
- description: |
Reset mode for the PLL. Mode can be one of:
0 - reset whenever PLL rate is adjusted (default mode)
1 - do not reset when PLL rate is adjusted
In mode 1, the PLL is only reset if the silabs,pll-reset is
specified in one of the clock output child nodes that also sources
the PLL. This mode may be preferable if output clocks are expected
to be adjusted without glitches.
enum: [ 0, 1 ]
patternProperties:
"^clkout@[0-7]$":
type: object
additionalProperties: false
properties:
reg:
description: Clock output number.
clock-frequency: true
silabs,clock-source:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Source clock of the this output's divider stage.
0 - use multisynth N for this output, where N is the output number
1 - use either multisynth 0 (if output number is 0-3) or multisynth 4
(otherwise) for this output
2 - use XTAL for this output
3 - use CLKIN for this output (Si5351C only)
silabs,drive-strength:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 2, 4, 6, 8 ]
description: Output drive strength in mA.
silabs,multisynth-source:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1 ]
description:
Source PLL A (0) or B (1) for the corresponding multisynth divider.
silabs,pll-master:
type: boolean
description: |
The frequency of the source PLL is allowed to be changed by the
multisynth when setting the rate of this clock output.
silabs,pll-reset:
type: boolean
description: Reset the source PLL when enabling this clock output.
silabs,disable-state:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1, 2, 3 ]
description: |
Clock output disable state. The state can be one of:
0 - clock output is driven LOW when disabled
1 - clock output is driven HIGH when disabled
2 - clock output is FLOATING (HIGH-Z) when disabled
3 - clock output is never disabled
allOf:
- if:
properties:
compatible:
contains:
const: silabs,si5351a-msop
then:
properties:
reg:
maximum: 2
else:
properties:
reg:
maximum: 7
- if:
properties:
compatible:
contains:
const: silabs,si5351c
then:
properties:
silabs,clock-source:
enum: [ 0, 1, 2, 3 ]
else:
properties:
silabs,clock-source:
enum: [ 0, 1, 2 ]
required:
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- silabs,si5351a
- silabs,si5351a-msop
- silabs,si5351b
then:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
required:
- reg
- "#address-cells"
- "#size-cells"
- "#clock-cells"
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
clock-generator@60 {
compatible = "silabs,si5351a-msop";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
/* Connect XTAL input to 25MHz reference */
clocks = <&ref25>;
clock-names = "xtal";
/* Use XTAL input as source of PLL0 and PLL1 */
silabs,pll-source = <0 0>, <1 0>;
/* Don't reset PLL1 on rate adjustment */
silabs,pll-reset-mode = <1 1>;
/*
* Overwrite CLK0 configuration with:
* - 8 mA output drive strength
* - PLL0 as clock source of multisynth 0
* - Multisynth 0 as clock source of output divider
* - Multisynth 0 can change PLL0
* - Set initial clock frequency of 74.25MHz
*/
clkout@0 {
reg = <0>;
silabs,drive-strength = <8>;
silabs,multisynth-source = <0>;
silabs,clock-source = <0>;
silabs,pll-master;
clock-frequency = <74250000>;
};
/*
* Overwrite CLK1 configuration with:
* - 4 mA output drive strength
* - PLL1 as clock source of multisynth 1
* - Multisynth 1 as clock source of output divider
* - Multisynth 1 can change PLL1
* - Reset PLL1 when enabling this clock output
*/
clkout@1 {
reg = <1>;
silabs,drive-strength = <4>;
silabs,multisynth-source = <1>;
silabs,clock-source = <0>;
silabs,pll-master;
silabs,pll-reset;
};
/*
* Overwrite CLK2 configuration with:
* - XTAL as clock source of output divider
*/
clkout@2 {
reg = <2>;
silabs,clock-source = <2>;
};
};
};

46
dts/upstream/Bindings/clock/sophgo,cv1800-clk.yaml Normal file
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@ -0,0 +1,46 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sophgo,cv1800-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo CV1800 Series Clock Controller
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
properties:
compatible:
enum:
- sophgo,cv1800-clk
- sophgo,cv1810-clk
reg:
maxItems: 1
clocks:
maxItems: 1
"#clock-cells":
const: 1
description:
See <dt-bindings/clock/sophgo,cv1800.h> for valid indices.
required:
- compatible
- reg
- clocks
- "#clock-cells"
additionalProperties: false
examples:
- |
clock-controller@3002000 {
compatible = "sophgo,cv1800-clk";
reg = <0x03002000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
...

76
dts/upstream/Bindings/clock/st,stm32mp25-rcc.yaml Normal file
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@ -0,0 +1,76 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STM32MP25 Reset Clock Controller
maintainers:
- Gabriel Fernandez <gabriel.fernandez@foss.st.com>
description: |
The RCC hardware block is both a reset and a clock controller.
RCC makes also power management (resume/supend).
See also::
include/dt-bindings/clock/st,stm32mp25-rcc.h
include/dt-bindings/reset/st,stm32mp25-rcc.h
properties:
compatible:
enum:
- st,stm32mp25-rcc
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
clocks:
items:
- description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
- description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
- description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
- description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
- description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
clock-names:
items:
- const: hse
- const: hsi
- const: msi
- const: lse
- const: lsi
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
rcc: clock-controller@44200000 {
compatible = "st,stm32mp25-rcc";
reg = <0x44200000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
clock-names = "hse", "hsi", "msi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_MSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>;
};
...

1
dts/upstream/Bindings/clock/xlnx,clocking-wizard.yaml
View File

@ -20,6 +20,7 @@ properties:
- xlnx,clocking-wizard
- xlnx,clocking-wizard-v5.2
- xlnx,clocking-wizard-v6.0
- xlnx,versal-clk-wizard
reg:

31
dts/upstream/Bindings/clock/xlnx,versal-clk.yaml
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@ -31,11 +31,11 @@ properties:
clocks:
description: List of clock specifiers which are external input
clocks to the given clock controller.
minItems: 3
minItems: 2
maxItems: 8
clock-names:
minItems: 3
minItems: 2
maxItems: 8
required:
@ -59,15 +59,34 @@ allOf:
clocks:
items:
- description: reference clock
- description: alternate reference clock
- description: alternate reference clock for programmable logic
clock-names:
items:
- const: ref
- const: alt_ref
- const: pl_alt_ref
- if:
properties:
compatible:
contains:
enum:
- xlnx,versal-net-clk
then:
properties:
clocks:
items:
- description: reference clock
- description: alternate reference clock for programmable logic
- description: alternate reference clock
clock-names:
items:
- const: ref
- const: pl_alt_ref
- const: alt_ref
- if:
properties:
compatible:
@ -110,8 +129,8 @@ examples:
versal_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,versal-clk";
clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
clock-names = "ref", "alt_ref", "pl_alt_ref";
clocks = <&ref>, <&pl_alt_ref>;
clock-names = "ref", "pl_alt_ref";
};
};
};

124
dts/upstream/Bindings/connector/usb-connector.yaml
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@ -66,7 +66,6 @@ properties:
Particularly, if use an output GPIO to control a VBUS regulator, should
model it as a regulator. See bindings/regulator/fixed-regulator.yaml
# The following are optional properties for "usb-c-connector".
power-role:
description: Determines the power role that the Type C connector will
support. "dual" refers to Dual Role Port (DRP).
@ -119,30 +118,6 @@ properties:
# The following are optional properties for "usb-c-connector" with power
# delivery support.
source-pdos:
description: An array of u32 with each entry providing supported power
source data object(PDO), the detailed bit definitions of PDO can be found
in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
Source_Capabilities Message, the order of each entry(PDO) should follow
the PD spec chapter 6.4.1. Required for power source and power dual role.
User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
defined in dt-bindings/usb/pd.h.
minItems: 1
maxItems: 7
$ref: /schemas/types.yaml#/definitions/uint32-array
sink-pdos:
description: An array of u32 with each entry providing supported power sink
data object(PDO), the detailed bit definitions of PDO can be found in
"Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
Sink Capabilities Message, the order of each entry(PDO) should follow the
PD spec chapter 6.4.1. Required for power sink and power dual role. User
can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
in dt-bindings/usb/pd.h.
minItems: 1
maxItems: 7
$ref: /schemas/types.yaml#/definitions/uint32-array
sink-vdos:
description: An array of u32 with each entry, a Vendor Defined Message Object (VDO),
providing additional information corresponding to the product, the detailed bit
@ -166,10 +141,43 @@ properties:
maxItems: 6
$ref: /schemas/types.yaml#/definitions/uint32-array
op-sink-microwatt:
description: Sink required operating power in microwatt, if source can't
offer the power, Capability Mismatch is set. Required for power sink and
power dual role.
accessory-mode-audio:
type: boolean
description: Whether the device supports Audio Adapter Accessory Mode. This
is only necessary if there are no other means to discover supported
alternative modes (e.g. through the UCSI firmware interface).
accessory-mode-debug:
type: boolean
description: Whether the device supports Debug Accessory Mode. This
is only necessary if there are no other means to discover supported
alternative modes (e.g. through the UCSI firmware interface).
altmodes:
type: object
description: List of Alternative Modes supported by the schematics on the
particular device. This is only necessary if there are no other means to
discover supported alternative modes (e.g. through the UCSI firmware
interface).
additionalProperties: false
patternProperties:
"^(displayport)$":
type: object
description:
A single USB-C Alternative Mode as supported by the USB-C connector logic.
additionalProperties: false
properties:
svid:
$ref: /schemas/types.yaml#/definitions/uint16
description: Unique value assigned by USB-IF to the Vendor / AltMode.
enum: [ 0xff01 ]
vdo:
$ref: /schemas/types.yaml#/definitions/uint32
description: VDO returned by Discover Modes USB PD command.
port:
$ref: /schemas/graph.yaml#/properties/port
@ -231,6 +239,20 @@ properties:
SNK_READY for non-pd link.
type: boolean
capabilities:
description: A child node to contain all the selectable USB Power Delivery capabilities.
type: object
patternProperties:
"^caps-[0-9]+$":
description: Child nodes under "capabilities" node. Each node contains a selectable USB
Power Delivery capability.
type: object
$ref: "#/$defs/capabilities"
unevaluatedProperties: false
additionalProperties: false
dependencies:
sink-vdos-v1: [ sink-vdos ]
sink-vdos: [ sink-vdos-v1 ]
@ -238,7 +260,42 @@ dependencies:
required:
- compatible
$defs:
capabilities:
type: object
properties:
source-pdos:
description: An array of u32 with each entry providing supported power
source data object(PDO), the detailed bit definitions of PDO can be found
in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
Source_Capabilities Message, the order of each entry(PDO) should follow
the PD spec chapter 6.4.1. Required for power source and power dual role.
User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
defined in dt-bindings/usb/pd.h.
minItems: 1
maxItems: 7
$ref: /schemas/types.yaml#/definitions/uint32-array
sink-pdos:
description: An array of u32 with each entry providing supported power sink
data object(PDO), the detailed bit definitions of PDO can be found in
"Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
Sink Capabilities Message, the order of each entry(PDO) should follow the
PD spec chapter 6.4.1. Required for power sink and power dual role. User
can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
in dt-bindings/usb/pd.h.
minItems: 1
maxItems: 7
$ref: /schemas/types.yaml#/definitions/uint32-array
op-sink-microwatt:
description: Sink required operating power in microwatt, if source can't
offer the power, Capability Mismatch is set. Required for power sink and
power dual role.
allOf:
- $ref: "#/$defs/capabilities"
- if:
properties:
compatible:
@ -267,7 +324,7 @@ anyOf:
- typec-power-opmode
- new-source-frs-typec-current
additionalProperties: false
unevaluatedProperties: false
examples:
# Micro-USB connector with HS lines routed via controller (MUIC).
@ -289,6 +346,13 @@ examples:
compatible = "usb-c-connector";
label = "USB-C";
altmodes {
displayport {
svid = /bits/ 16 <0xff01>;
vdo = <0x00001c46>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;

81
dts/upstream/Bindings/cpu/idle-states.yaml
View File

@ -243,7 +243,64 @@ description: |+
just supports idle_standby, an idle-states node is not required.
===========================================
6 - References
6 - Qualcomm specific STATES
===========================================
Idle states have different enter/exit latency and residency values.
The idle states supported by the QCOM SoC are defined as -
* Standby
* Retention
* Standalone Power Collapse (Standalone PC or SPC)
* Power Collapse (PC)
Standby: Standby does a little more in addition to architectural clock gating.
When the WFI instruction is executed the ARM core would gate its internal
clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
trigger to execute the SPM state machine. The SPM state machine waits for the
interrupt to trigger the core back in to active. This triggers the cache
hierarchy to enter standby states, when all cpus are idle. An interrupt brings
the SPM state machine out of its wait, the next step is to ensure that the
cache hierarchy is also out of standby, and then the cpu is allowed to resume
execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
driver and is not defined in the DT. The SPM state machine should be
configured to execute this state by default and after executing every other
state below.
Retention: Retention is a low power state where the core is clock gated and
the memory and the registers associated with the core are retained. The
voltage may be reduced to the minimum value needed to keep the processor
registers active. The SPM should be configured to execute the retention
sequence and would wait for interrupt, before restoring the cpu to execution
state. Retention may have a slightly higher latency than Standby.
Standalone PC: A cpu can power down and warmboot if there is a sufficient time
between the time it enters idle and the next known wake up. SPC mode is used
to indicate a core entering a power down state without consulting any other
cpu or the system resources. This helps save power only on that core. The SPM
sequence for this idle state is programmed to power down the supply to the
core, wait for the interrupt, restore power to the core, and ensure the
system state including cache hierarchy is ready before allowing core to
resume. Applying power and resetting the core causes the core to warmboot
back into Elevation Level (EL) which trampolines the control back to the
kernel. Entering a power down state for the cpu, needs to be done by trapping
into a EL. Failing to do so, would result in a crash enforced by the warm boot
code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
be flushed in s/w, before powering down the core.
Power Collapse: This state is similar to the SPC mode, but distinguishes
itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
modes. In a hierarchical power domain SoC, this means L2 and other caches can
be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
voltages reduced, provided all cpus enter this state. Since the span of low
power modes possible at this state is vast, the exit latency and the residency
of this low power mode would be considered high even though at a cpu level,
this essentially is cpu power down. The SPM in this state also may handshake
with the Resource power manager (RPM) processor in the SoC to indicate a
complete application processor subsystem shut down.
===========================================
7 - References
===========================================
[1] ARM Linux Kernel documentation - CPUs bindings
@ -301,9 +358,16 @@ patternProperties:
properties:
compatible:
enum:
- arm,idle-state
- riscv,idle-state
oneOf:
- items:
- enum:
- qcom,idle-state-ret
- qcom,idle-state-spc
- qcom,idle-state-pc
- const: arm,idle-state
- enum:
- arm,idle-state
- riscv,idle-state
arm,psci-suspend-param:
$ref: /schemas/types.yaml#/definitions/uint32
@ -852,4 +916,13 @@ examples:
};
};
// Example 4 - Qualcomm SPC
idle-states {
cpu_spc: cpu-spc {
compatible = "qcom,idle-state-spc", "arm,idle-state";
entry-latency-us = <150>;
exit-latency-us = <200>;
min-residency-us = <2000>;
};
};
...

86
dts/upstream/Bindings/crypto/inside-secure,safexcel.yaml Normal file
View File

@ -0,0 +1,86 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/inside-secure,safexcel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Inside Secure SafeXcel cryptographic engine
maintainers:
- Antoine Tenart <atenart@kernel.org>
properties:
compatible:
oneOf:
- const: inside-secure,safexcel-eip197b
- const: inside-secure,safexcel-eip197d
- const: inside-secure,safexcel-eip97ies
- const: inside-secure,safexcel-eip197
description: Equivalent of inside-secure,safexcel-eip197b
deprecated: true
- const: inside-secure,safexcel-eip97
description: Equivalent of inside-secure,safexcel-eip97ies
deprecated: true
reg:
maxItems: 1
interrupts:
maxItems: 6
interrupt-names:
items:
- const: ring0
- const: ring1
- const: ring2
- const: ring3
- const: eip
- const: mem
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: core
- const: reg
required:
- reg
- interrupts
- interrupt-names
allOf:
- if:
properties:
clocks:
minItems: 2
then:
properties:
clock-names:
minItems: 2
required:
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
crypto@800000 {
compatible = "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2", "ring3", "eip", "mem";
clocks = <&cpm_syscon0 1 26>;
clock-names = "core";
};

40
dts/upstream/Bindings/crypto/inside-secure-safexcel.txt
View File

@ -1,40 +0,0 @@
Inside Secure SafeXcel cryptographic engine
Required properties:
- compatible: Should be "inside-secure,safexcel-eip197b",
"inside-secure,safexcel-eip197d" or
"inside-secure,safexcel-eip97ies".
- reg: Base physical address of the engine and length of memory mapped region.
- interrupts: Interrupt numbers for the rings and engine.
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
Optional properties:
- clocks: Reference to the crypto engine clocks, the second clock is
needed for the Armada 7K/8K SoCs.
- clock-names: mandatory if there is a second clock, in this case the
name must be "core" for the first clock and "reg" for
the second one.
Backward compatibility:
Two compatibles are kept for backward compatibility, but shouldn't be used for
new submissions:
- "inside-secure,safexcel-eip197" is equivalent to
"inside-secure,safexcel-eip197b".
- "inside-secure,safexcel-eip97" is equivalent to
"inside-secure,safexcel-eip97ies".
Example:
crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
"eip";
clocks = <&cpm_syscon0 1 26>;
};

1
dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml
View File

@ -16,6 +16,7 @@ properties:
- qcom,sa8775p-inline-crypto-engine
- qcom,sm8450-inline-crypto-engine
- qcom,sm8550-inline-crypto-engine
- qcom,sm8650-inline-crypto-engine
- const: qcom,inline-crypto-engine
reg:

1
dts/upstream/Bindings/crypto/qcom,prng.yaml
View File

@ -21,6 +21,7 @@ properties:
- qcom,sc7280-trng
- qcom,sm8450-trng
- qcom,sm8550-trng
- qcom,sm8650-trng
- const: qcom,trng
reg:

14
dts/upstream/Bindings/crypto/qcom-qce.yaml
View File

@ -44,10 +44,12 @@ properties:
- items:
- enum:
- qcom,sc7280-qce
- qcom,sm8250-qce
- qcom,sm8350-qce
- qcom,sm8450-qce
- qcom,sm8550-qce
- qcom,sm8650-qce
- const: qcom,sm8150-qce
- const: qcom,qce
@ -96,6 +98,7 @@ allOf:
- qcom,crypto-v5.4
- qcom,ipq6018-qce
- qcom,ipq8074-qce
- qcom,ipq9574-qce
- qcom,msm8996-qce
- qcom,sdm845-qce
then:
@ -129,6 +132,17 @@ allOf:
- clocks
- clock-names
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8150-qce
then:
properties:
clocks: false
clock-names: false
required:
- compatible
- reg

21
dts/upstream/Bindings/display/bridge/lontium,lt8912b.yaml
View File

@ -55,6 +55,27 @@ properties:
- port@0
- port@1
vcchdmipll-supply:
description: A 1.8V supply that powers the HDMI PLL.
vcchdmitx-supply:
description: A 1.8V supply that powers the HDMI TX part.
vcclvdspll-supply:
description: A 1.8V supply that powers the LVDS PLL.
vcclvdstx-supply:
description: A 1.8V supply that powers the LVDS TX part.
vccmipirx-supply:
description: A 1.8V supply that powers the MIPI RX part.
vccsysclk-supply:
description: A 1.8V supply that powers the SYSCLK.
vdd-supply:
description: A 1.8V supply that powers the digital part.
required:
- compatible
- reg

7
dts/upstream/Bindings/display/bridge/nxp,tda998x.yaml
View File

@ -29,19 +29,22 @@ properties:
audio-ports:
description:
Array of 8-bit values, 2 values per DAI (Documentation/sound/soc/dai.rst).
Array of 2 values per DAI (Documentation/sound/soc/dai.rst).
The implementation allows one or two DAIs.
If two DAIs are defined, they must be of different type.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 1
maxItems: 2
items:
minItems: 1
items:
- description: |
The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S
(see include/dt-bindings/display/tda998x.h).
enum: [ 1, 2 ]
- description:
The second value defines the tda998x AP_ENA reg content when the
DAI in question is used.
maximum: 0xff
'#sound-dai-cells':
enum: [ 0, 1 ]

1
dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
View File

@ -24,6 +24,7 @@ properties:
- enum:
- mediatek,mt8173-disp-aal
- mediatek,mt8183-disp-aal
- mediatek,mt8195-mdp3-aal
- items:
- enum:
- mediatek,mt2712-disp-aal

1
dts/upstream/Bindings/display/mediatek/mediatek,color.yaml
View File

@ -26,6 +26,7 @@ properties:
- mediatek,mt2701-disp-color
- mediatek,mt8167-disp-color
- mediatek,mt8173-disp-color
- mediatek,mt8195-mdp3-color
- items:
- enum:
- mediatek,mt7623-disp-color

4
dts/upstream/Bindings/display/mediatek/mediatek,dsi.yaml
View File

@ -34,6 +34,10 @@ properties:
- enum:
- mediatek,mt6795-dsi
- const: mediatek,mt8173-dsi
- items:
- enum:
- mediatek,mt8195-dsi
- const: mediatek,mt8183-dsi
reg:
maxItems: 1

6
dts/upstream/Bindings/display/mediatek/mediatek,ethdr.yaml
View File

@ -23,7 +23,11 @@ description:
properties:
compatible:
const: mediatek,mt8195-disp-ethdr
oneOf:
- const: mediatek,mt8195-disp-ethdr
- items:
- const: mediatek,mt8188-disp-ethdr
- const: mediatek,mt8195-disp-ethdr
reg:
maxItems: 7

88
dts/upstream/Bindings/display/mediatek/mediatek,mdp-rdma.yaml
View File

@ -1,88 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MDP RDMA
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
description:
The MediaTek MDP RDMA stands for Read Direct Memory Access.
It provides real time data to the back-end panel driver, such as DSI,
DPI and DP_INTF.
It contains one line buffer to store the sufficient pixel data.
RDMA device node must be siblings to the central MMSYS_CONFIG node.
For a description of the MMSYS_CONFIG binding, see
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
properties:
compatible:
const: mediatek,mt8195-vdo1-rdma
reg:
maxItems: 1
interrupts:
maxItems: 1
power-domains:
maxItems: 1
clocks:
items:
- description: RDMA Clock
iommus:
maxItems: 1
mediatek,gce-client-reg:
description:
The register of display function block to be set by gce. There are 4 arguments,
such as gce node, subsys id, offset and register size. The subsys id that is
mapping to the register of display function blocks is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
- description: GCE subsys id
- description: register offset
- description: register size
maxItems: 1
required:
- compatible
- reg
- power-domains
- clocks
- iommus
- mediatek,gce-client-reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
rdma@1c104000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c104000 0 0x1000>;
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
};
};

4
dts/upstream/Bindings/display/mediatek/mediatek,merge.yaml
View File

@ -24,9 +24,13 @@ properties:
- enum:
- mediatek,mt8173-disp-merge
- mediatek,mt8195-disp-merge
- mediatek,mt8195-mdp3-merge
- items:
- const: mediatek,mt6795-disp-merge
- const: mediatek,mt8173-disp-merge
- items:
- const: mediatek,mt8188-disp-merge
- const: mediatek,mt8195-disp-merge
reg:
maxItems: 1

1
dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
View File

@ -26,6 +26,7 @@ properties:
- mediatek,mt8173-disp-ovl
- mediatek,mt8183-disp-ovl
- mediatek,mt8192-disp-ovl
- mediatek,mt8195-mdp3-ovl
- items:
- enum:
- mediatek,mt7623-disp-ovl

83
dts/upstream/Bindings/display/mediatek/mediatek,padding.yaml Normal file
View File

@ -0,0 +1,83 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Display Padding
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
description:
Padding provides ability to add pixels to width and height of a layer with
specified colors. Due to hardware design, Mixer in VDOSYS1 requires
width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
we need Padding to deal with odd width.
Please notice that even if the Padding is in bypass mode, settings in
register must be cleared to 0, or undefined behaviors could happen.
properties:
compatible:
enum:
- mediatek,mt8188-disp-padding
- mediatek,mt8195-mdp3-padding
reg:
maxItems: 1
power-domains:
maxItems: 1
clocks:
items:
- description: Padding's clocks
mediatek,gce-client-reg:
description:
GCE (Global Command Engine) is a multi-core micro processor that helps
its clients to execute commands without interrupting CPU. This property
describes GCE client's information that is composed by 4 fields.
1. Phandle of the GCE (there may be several GCE processors)
2. Sub-system ID defined in the dt-binding like a user ID
(Please refer to include/dt-bindings/gce/<chip>-gce.h)
3. Offset from base address of the subsys you are at
4. Size of the register the client needs
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: Phandle of the GCE
- description: Subsys ID defined in the dt-binding
- description: Offset from base address of the subsys
- description: Size of register
maxItems: 1
required:
- compatible
- reg
- power-domains
- clocks
- mediatek,gce-client-reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <dt-bindings/power/mediatek,mt8188-power.h>
#include <dt-bindings/gce/mt8195-gce.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
padding0: padding@1c11d000 {
compatible = "mediatek,mt8188-disp-padding";
reg = <0 0x1c11d000 0 0x1000>;
clocks = <&vdosys1 CLK_VDO1_PADDING0>;
power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
};
};

27
dts/upstream/Bindings/display/mediatek/mediatek,split.yaml
View File

@ -23,6 +23,7 @@ properties:
oneOf:
- enum:
- mediatek,mt8173-disp-split
- mediatek,mt8195-mdp3-split
- items:
- const: mediatek,mt6795-disp-split
- const: mediatek,mt8173-disp-split
@ -38,6 +39,21 @@ properties:
the power controller specified by phandle. See
Documentation/devicetree/bindings/power/power-domain.yaml for details.
mediatek,gce-client-reg:
description:
The register of display function block to be set by gce. There are 4 arguments,
such as gce node, subsys id, offset and register size. The subsys id that is
mapping to the register of display function blocks is defined in the gce header
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
- description: GCE subsys id
- description: register offset
- description: register size
maxItems: 1
clocks:
items:
- description: SPLIT Clock
@ -48,6 +64,17 @@ required:
- power-domains
- clocks
allOf:
- if:
properties:
compatible:
contains:
const: mediatek,mt8195-mdp3-split
then:
required:
- mediatek,gce-client-reg
additionalProperties: false
examples:

2
dts/upstream/Bindings/display/msm/dp-controller.yaml
View File

@ -26,8 +26,10 @@ properties:
- qcom,sc8280xp-edp
- qcom,sdm845-dp
- qcom,sm8350-dp
- qcom,sm8650-dp
- items:
- enum:
- qcom,sm8150-dp
- qcom,sm8250-dp
- qcom,sm8450-dp
- qcom,sm8550-dp

3
dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
View File

@ -25,6 +25,7 @@ properties:
- qcom,sc7180-dsi-ctrl
- qcom,sc7280-dsi-ctrl
- qcom,sdm660-dsi-ctrl
- qcom,sdm670-dsi-ctrl
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6125-dsi-ctrl
@ -35,6 +36,7 @@ properties:
- qcom,sm8350-dsi-ctrl
- qcom,sm8450-dsi-ctrl
- qcom,sm8550-dsi-ctrl
- qcom,sm8650-dsi-ctrl
- const: qcom,mdss-dsi-ctrl
- enum:
- qcom,dsi-ctrl-6g-qcm2290
@ -333,6 +335,7 @@ allOf:
- qcom,sm8350-dsi-ctrl
- qcom,sm8450-dsi-ctrl
- qcom,sm8550-dsi-ctrl
- qcom,sm8650-dsi-ctrl
then:
properties:
clocks:

1
dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml
View File

@ -22,6 +22,7 @@ properties:
- qcom,sm8350-dsi-phy-5nm
- qcom,sm8450-dsi-phy-5nm
- qcom,sm8550-dsi-phy-4nm
- qcom,sm8650-dsi-phy-4nm
reg:
items:

18
dts/upstream/Bindings/display/msm/mdss-common.yaml
View File

@ -61,17 +61,27 @@ properties:
ranges: true
# This is not a perfect description, but it's impossible to discern and match
# the entries like we do with interconnect-names
interconnects:
minItems: 1
items:
- description: Interconnect path from mdp0 (or a single mdp) port to the data bus
- description: Interconnect path from mdp1 port to the data bus
- description: Interconnect path from CPU to the reg bus
interconnect-names:
minItems: 1
items:
- const: mdp0-mem
- const: mdp1-mem
oneOf:
- minItems: 1
items:
- const: mdp0-mem
- const: cpu-cfg
- minItems: 2
items:
- const: mdp0-mem
- const: mdp1-mem
- const: cpu-cfg
resets:
items:

21
dts/upstream/Bindings/display/msm/qcom,qcm2290-mdss.yaml
View File

@ -36,10 +36,14 @@ properties:
maxItems: 2
interconnects:
maxItems: 1
items:
- description: Interconnect path from mdp0 port to the data bus
- description: Interconnect path from CPU to the reg bus
interconnect-names:
maxItems: 1
items:
- const: mdp0-mem
- const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
@ -56,7 +60,9 @@ patternProperties:
properties:
compatible:
const: qcom,dsi-ctrl-6g-qcm2290
items:
- const: qcom,qcm2290-dsi-ctrl
- const: qcom,mdss-dsi-ctrl
"^phy@[0-9a-f]+$":
type: object
@ -96,8 +102,10 @@ examples:
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
interconnect-names = "mdp0-mem";
interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>,
<&bimc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "mdp0-mem",
"cpu-cfg";
iommus = <&apps_smmu 0x420 0x2>,
<&apps_smmu 0x421 0x0>;
@ -136,7 +144,8 @@ examples:
};
dsi@5e94000 {
compatible = "qcom,dsi-ctrl-6g-qcm2290";
compatible = "qcom,qcm2290-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0x05e94000 0x400>;
reg-names = "dsi_ctrl";

14
dts/upstream/Bindings/display/msm/qcom,sc7180-mdss.yaml
View File

@ -36,10 +36,14 @@ properties:
maxItems: 1
interconnects:
maxItems: 1
items:
- description: Interconnect path from mdp0 port to the data bus
- description: Interconnect path from CPU to the reg bus
interconnect-names:
maxItems: 1
items:
- const: mdp0-mem
- const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
@ -106,8 +110,10 @@ examples:
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
interconnect-names = "mdp0-mem";
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "mdp0-mem",
"cpu-cfg";
iommus = <&apps_smmu 0x800 0x2>;
ranges;

14
dts/upstream/Bindings/display/msm/qcom,sc7280-mdss.yaml
View File

@ -36,10 +36,14 @@ properties:
maxItems: 1
interconnects:
maxItems: 1
items:
- description: Interconnect path from mdp0 port to the data bus
- description: Interconnect path from CPU to the reg bus
interconnect-names:
maxItems: 1
items:
- const: mdp0-mem
- const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
@ -118,8 +122,10 @@ examples:
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
interconnect-names = "mdp0-mem";
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_DISPLAY_CFG>;
interconnect-names = "mdp0-mem",
"cpu-cfg";
iommus = <&apps_smmu 0x900 0x402>;
ranges;

292
dts/upstream/Bindings/display/msm/qcom,sdm670-mdss.yaml Normal file
View File

@ -0,0 +1,292 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM670 Display MDSS
maintainers:
- Richard Acayan <mailingradian@gmail.com>
description:
SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
like DPU display controller, DSI and DP interfaces etc.
$ref: /schemas/display/msm/mdss-common.yaml#
properties:
compatible:
const: qcom,sdm670-mdss
clocks:
items:
- description: Display AHB clock from gcc
- description: Display core clock
clock-names:
items:
- const: iface
- const: core
iommus:
maxItems: 2
interconnects:
maxItems: 2
interconnect-names:
maxItems: 2
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sdm670-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,sdm670-dp
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: qcom,sdm670-dsi-ctrl
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
const: qcom,dsi-phy-10nm
required:
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-subsystem@ae00000 {
compatible = "qcom,sdm670-mdss";
reg = <0x0ae00000 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "core";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
<&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
interconnect-names = "mdp0-mem", "mdp1-mem";
iommus = <&apps_smmu 0x880 0x8>,
<&apps_smmu 0xc80 0x8>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
display-controller@ae01000 {
compatible = "qcom,sdm670-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
interrupt-parent = <&mdss>;
interrupts = <0>;
power-domains = <&rpmhpd SDM670_CX>;
operating-points-v2 = <&mdp_opp_table>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf2_out: endpoint {
remote-endpoint = <&mdss_dsi1_in>;
};
};
};
};
dsi@ae94000 {
compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0ae94000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM670_CX>;
phys = <&mdss_dsi0_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
};
};
};
};
mdss_dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0x0ae94400 0x200>,
<0x0ae94600 0x280>,
<0x0ae94a00 0x1e0>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
vdds-supply = <&vreg_dsi_phy>;
};
dsi@ae96000 {
compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0ae96000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5>;
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM670_CX>;
phys = <&dsi1_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi1_in: endpoint {
remote-endpoint = <&dpu_intf2_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi1_out: endpoint {
};
};
};
};
mdss_dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0x0ae96400 0x200>,
<0x0ae96600 0x280>,
<0x0ae96a00 0x10e>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
vdds-supply = <&vreg_dsi_phy>;
};
};
...

4
dts/upstream/Bindings/display/msm/qcom,sdm845-dpu.yaml
View File

@ -13,7 +13,9 @@ $ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,sdm845-dpu
enum:
- qcom,sdm670-dpu
- qcom,sdm845-dpu
reg:
items:

10
dts/upstream/Bindings/display/msm/qcom,sm6115-mdss.yaml
View File

@ -29,6 +29,16 @@ properties:
iommus:
maxItems: 2
interconnects:
items:
- description: Interconnect path from mdp0 port to the data bus
- description: Interconnect path from CPU to the reg bus
interconnect-names:
items:
- const: mdp0-mem
- const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object

8
dts/upstream/Bindings/display/msm/qcom,sm6125-mdss.yaml
View File

@ -35,10 +35,14 @@ properties:
maxItems: 1
interconnects:
maxItems: 2
items:
- description: Interconnect path from mdp0 port to the data bus
- description: Interconnect path from CPU to the reg bus
interconnect-names:
maxItems: 2
items:
- const: mdp0-mem
- const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":

8
dts/upstream/Bindings/display/msm/qcom,sm6350-mdss.yaml
View File

@ -35,10 +35,14 @@ properties:
maxItems: 1
interconnects:
maxItems: 2
items:
- description: Interconnect path from mdp0 port to the data bus
- description: Interconnect path from CPU to the reg bus
interconnect-names:
maxItems: 2
items:
- const: mdp0-mem
- const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":

8
dts/upstream/Bindings/display/msm/qcom,sm6375-mdss.yaml
View File

@ -35,10 +35,14 @@ properties:
maxItems: 1
interconnects:
maxItems: 2
items:
- description: Interconnect path from mdp0 port to the data bus
- description: Interconnect path from CPU to the reg bus
interconnect-names:
maxItems: 2
items:
- const: mdp0-mem
- const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":

6
dts/upstream/Bindings/display/msm/qcom,sm8150-mdss.yaml
View File

@ -69,7 +69,7 @@ patternProperties:
properties:
compatible:
const: qcom,dsi-phy-7nm
const: qcom,dsi-phy-7nm-8150
unevaluatedProperties: false
@ -247,7 +247,7 @@ examples:
};
dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-7nm";
compatible = "qcom,dsi-phy-7nm-8150";
reg = <0x0ae94400 0x200>,
<0x0ae94600 0x280>,
<0x0ae94900 0x260>;
@ -318,7 +318,7 @@ examples:
};
dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-7nm";
compatible = "qcom,dsi-phy-7nm-8150";
reg = <0x0ae96400 0x200>,
<0x0ae96600 0x280>,
<0x0ae96900 0x260>;

10
dts/upstream/Bindings/display/msm/qcom,sm8250-mdss.yaml
View File

@ -52,6 +52,16 @@ patternProperties:
compatible:
const: qcom,sm8250-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
items:
- const: qcom,sm8250-dp
- const: qcom,sm8350-dp
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true

13
dts/upstream/Bindings/display/msm/qcom,sm8450-mdss.yaml
View File

@ -30,10 +30,10 @@ properties:
maxItems: 1
interconnects:
maxItems: 2
maxItems: 3
interconnect-names:
maxItems: 2
maxItems: 3
patternProperties:
"^display-controller@[0-9a-f]+$":
@ -91,9 +91,12 @@ examples:
reg = <0x0ae00000 0x1000>;
reg-names = "mdss";
interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
<&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
interconnect-names = "mdp0-mem", "mdp1-mem";
interconnects = <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>,
<&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "mdp0-mem",
"mdp1-mem",
"cpu-cfg";
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;

127
dts/upstream/Bindings/display/msm/qcom,sm8650-dpu.yaml Normal file
View File

@ -0,0 +1,127 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8650 Display DPU
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,sm8650-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display hf axi
- description: Display MDSS ahb
- description: Display lut
- description: Display core
- description: Display vsync
clock-names:
items:
- const: nrt_bus
- const: iface
- const: lut
- const: core
- const: vsync
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-controller@ae01000 {
compatible = "qcom,sm8650-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc_axi_clk>,
<&dispcc_ahb_clk>,
<&dispcc_mdp_lut_clk>,
<&dispcc_mdp_clk>,
<&dispcc_vsync_clk>;
clock-names = "nrt_bus",
"iface",
"lut",
"core",
"vsync";
assigned-clocks = <&dispcc_vsync_clk>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-325000000 {
opp-hz = /bits/ 64 <325000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-375000000 {
opp-hz = /bits/ 64 <375000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-514000000 {
opp-hz = /bits/ 64 <514000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
...

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