224 lines
6.1 KiB
YAML
224 lines
6.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM6125 Display MDSS
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maintainers:
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- Marijn Suijten <marijn.suijten@somainline.org>
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description:
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SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
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like DPU display controller, DSI and DP interfaces etc.
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$ref: /schemas/display/msm/mdss-common.yaml#
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properties:
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compatible:
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const: qcom,sm6125-mdss
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clocks:
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items:
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- description: Display AHB clock from gcc
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- description: Display AHB clock
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- description: Display core clock
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clock-names:
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items:
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- const: iface
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- const: ahb
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- const: core
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iommus:
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maxItems: 1
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interconnects:
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items:
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- description: Interconnect path from mdp0 port to the data bus
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- description: Interconnect path from CPU to the reg bus
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interconnect-names:
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items:
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- const: mdp0-mem
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- const: cpu-cfg
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,sm6125-dpu
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"^dsi@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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items:
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- const: qcom,sm6125-dsi-ctrl
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- const: qcom,mdss-dsi-ctrl
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"^phy@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,sm6125-dsi-phy-14nm
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
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#include <dt-bindings/clock/qcom,gcc-sm6125.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-subsystem@5e00000 {
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compatible = "qcom,sm6125-mdss";
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reg = <0x05e00000 0x1000>;
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reg-names = "mdss";
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface",
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"ahb",
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"core";
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power-domains = <&dispcc MDSS_GDSC>;
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iommus = <&apps_smmu 0x400 0x0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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display-controller@5e01000 {
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compatible = "qcom,sm6125-dpu";
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reg = <0x05e01000 0x83208>,
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<0x05eb0000 0x2008>;
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reg-names = "mdp", "vbif";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_ROT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
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<&gcc GCC_DISP_THROTTLE_CORE_CLK>;
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clock-names = "bus",
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"iface",
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"rot",
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"lut",
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"core",
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"vsync",
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"throttle";
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assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmpd SM6125_VDDCX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&mdss_dsi0_in>;
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};
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};
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};
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};
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dsi@5e94000 {
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compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x05e94000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmpd SM6125_VDDCX>;
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phys = <&mdss_dsi0_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi0_out: endpoint {
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};
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};
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};
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};
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phy@5e94400 {
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compatible = "qcom,sm6125-dsi-phy-14nm";
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reg = <0x05e94400 0x100>,
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<0x05e94500 0x300>,
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<0x05e94800 0x188>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmcc RPM_SMD_XO_CLK_SRC>;
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clock-names = "iface",
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"ref";
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required-opps = <&rpmpd_opp_nom>;
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power-domains = <&rpmpd SM6125_VDDMX>;
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};
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};
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...
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