u-boot/drivers/clk/exynos/clk-pll.h
Sam Protsenko f77780b0ee clk: exynos: Fix incorrect clock lookup for non-top CMUs
Samsung clock drivers usually define the clock indices that are unique
per one CMU, but are not unique across all CMUs. That is, clock indices
start from 1 for each CMU, as provided in CMU bindings header. The way
the clock lookup via clk_get_by_index() works at the moment is by using
clk_of_xlate_default(), which returns globally non-unique clock ids for
for clocks registered with Samsung CCF API, which leads to incorrect
clocks being obtained. One way to fix that would be to make all clock
ids defined in the bindings header unique, but it'd make it incompatible
with Linux kernel bindings header. A better way to solve this issue is
to calculate the global clock id and use it when registering a clock
with clk_dm() and when obtaining it, in a custom .of_xlate function.

This patch adds an API for such mapping calculation, introducing the
necessary modifications to CMU registering functions in Samsung CCF.
Exynos850 clock driver (the only driver that uses Samsung CCF at the
moment) is modified accordingly, as it uses the changed API. So the
clock lookup with clk-exynos850.c driver is also fixed here.

The global clock id is calculated from CMU id and local clock id in
SAMSUNG_TO_CLK_ID() macro like this:

    clk_id_global = cmu_id * 256 + clk_id_local

leaving a range of up to 256 clocks for each CMU. Then this mapping
macro is used in clk_dm() to register clocks using their global ids, and
in .of_xlate() to lookup the clock by its local id correctly. Because
.of_xlate() operation has a separate function for each CMU, it "knows"
the correct way of finding the correct clk_id_global by provided
clk_id_local.

Fixes: ff3e8b8c6c ("clk: exynos: Add Samsung clock framework")
Fixes: a36cc5e3ef ("clk: exynos: Add Exynos850 clock driver")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-03-26 18:56:55 +09:00

30 lines
657 B
C

/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Samsung Electronics
* Copyright (C) 2023 Linaro Ltd.
*
* Authors:
* Thomas Abraham <thomas.ab@samsung.com>
* Sam Protsenko <semen.protsenko@linaro.org>
*
* Common Clock Framework support for all PLL's in Samsung platforms.
*/
#ifndef __EXYNOS_CLK_PLL_H
#define __EXYNOS_CLK_PLL_H
#include <linux/clk-provider.h>
struct samsung_pll_clock;
enum samsung_pll_type {
pll_0822x,
pll_0831x,
};
void samsung_clk_register_pll(void __iomem *base, unsigned int cmu_id,
const struct samsung_pll_clock *clk_list,
unsigned int nr_clk);
#endif /* __EXYNOS_CLK_PLL_H */