57285737cb
Sync the devicetree files from the official Linux kernel tree, v6.4-rc2. This is covering both 64-bit and 32-bit Allwinner SoCs with Arm Ltd. cores, we skip the new RISC-V bits for now, as sunxi RISC-V support is still work in progress. Among smaller cosmetic changes, this adds a SATA regulator node which we need in U-Boot to get rid of hard-coded GPIOs. Also this updates the Allwinner F1C100s DTs, enabling USB support, and also adds the DTs for two new boards. As before, this omits the non-backwards compatible changes to the R_INTC controller, to remain compatible with older kernels. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
74 lines
1.2 KiB
Plaintext
74 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
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/*
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* Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
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*/
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/dts-v1/;
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#include "suniv-f1c100s.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Lichee Pi Nano";
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compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
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aliases {
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mmc0 = &mmc0;
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serial0 = &uart0;
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spi0 = &spi0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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reg_vcc3v3: vcc3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&mmc0 {
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broken-cd;
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bus-width = <4>;
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disable-wp;
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status = "okay";
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vmmc-supply = <®_vcc3v3>;
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pc_pins>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "winbond,w25q128", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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};
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};
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&otg_sram {
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status = "okay";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pe_pins>;
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status = "okay";
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};
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&usb_otg {
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dr_mode = "otg";
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status = "okay";
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};
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&usbphy {
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usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
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status = "okay";
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};
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