141 lines
3.3 KiB
Plaintext
141 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2023 Yilin Sun <imi415@imi.moe>
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "cvitek,cv1800b";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <25000000>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cvitek,cv1800b", "thead,c906", "riscv";
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reg = <0>;
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riscv,isa = "rv64imafdc";
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mmu-type = "sv39";
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <256>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <256>;
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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};
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osc: oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc_25m";
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clock-frequency = <25000000>;
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#clock-cells = <0>;
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};
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apb_clk: apb-clk-clock {
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compatible = "fixed-clock";
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clock-output-names = "apb_clk";
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clock-frequency = <25000000>;
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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plic: interrupt-controller@70000000 {
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compatible = "cvitek,cv1800b-plic", "thead,c900-plic";
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reg = <0x0 0x70000000 0x0 0x04000000>;
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interrupt-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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riscv,ndev = <101>;
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};
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clint: timer@74000000 {
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compatible = "cvitek,cv1800b-clint", "thead,c900-clint";
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reg = <0x0 0x74000000 0x0 0x00010000>;
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interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
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};
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pinctrl: pinctrl@03000000 {
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compatible = "cvitek,cv1800b-pinctrl";
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reg = <0x0 0x03000000 0x0 0x00001000>;
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};
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uart0: serial@04140000 {
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compatible = "cvitek,cv1800b-uart", "snps,dw-apb-uart";
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reg = <0x0 0x04140000 0x0 0x1000>;
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interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_clk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@04150000 {
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compatible = "cvitek,cv1800b-uart", "snps,dw-apb-uart";
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reg = <0x0 0x04150000 0x0 0x1000>;
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interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_clk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@04160000 {
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compatible = "cvitek,cv1800b-uart", "snps,dw-apb-uart";
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reg = <0x0 0x04160000 0x0 0x1000>;
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interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_clk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@04170000 {
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compatible = "cvitek,cv1800b-uart", "snps,dw-apb-uart";
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reg = <0x0 0x04170000 0x0 0x1000>;
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interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_clk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart4: serial@041C0000 {
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compatible = "cvitek,cv1800b-uart", "snps,dw-apb-uart";
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reg = <0x0 0x041C0000 0x0 0x1000>;
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interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_clk>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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i2c0: i2c@04000000 {
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compatible = "cvitek,cv1800b-i2c", "snps,designware-i2c";
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reg = <0x0 0x04000000 0x0 0x1000>;
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interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb_clk>;
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status = "disabled";
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};
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};
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};
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