87 lines
3.0 KiB
C
87 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2023 Yilin Sun <imi415@imi.moe>
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*/
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#ifndef DT_CV1800B_PINCTRL_H
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#define DT_CV1800B_PINCTRL_H
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#define CVI_CTRL_SD0_CLK (0x000U)
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#define CVI_CTRL_SD0_CMD (0x004U)
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#define CVI_CTRL_SD0_D0 (0x008U)
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#define CVI_CTRL_SD0_D1 (0x00CU)
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#define CVI_CTRL_SD0_D2 (0x010U)
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#define CVI_CTRL_SD0_D3 (0x014U)
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#define CVI_CTRL_SD0_CD (0x018U)
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#define CVI_CTRL_SD0_PWR_EN (0x01CU)
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#define CVI_CTRL_SPK_EN (0x020U)
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#define CVI_CTRL_UART0_TX (0x024U)
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#define CVI_CTRL_UART0_RX (0x028U)
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#define CVI_CTRL_SPINOR_HOLD_X (0x02CU)
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#define CVI_CTRL_SPINOR_SCK (0x030U)
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#define CVI_CTRL_SPINOR_MOSI (0x034U)
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#define CVI_CTRL_SPINOR_WP_X (0x038U)
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#define CVI_CTRL_SPINOR_MISO (0x03CU)
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#define CVI_CTRL_SPINOR_CS_X (0x040U)
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#define CVI_CTRL_JTAG_CPU_TMS (0x044U)
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#define CVI_CTRL_JTAG_CPU_TCK (0x048U)
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#define CVI_CTRL_IIC0_SCL (0x04CU)
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#define CVI_CTRL_IIC0_SDA (0x050U)
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#define CVI_CTRL_AUX0 (0x054U)
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#define CVI_CTRL_GPIO_ZQ (0x058U)
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#define CVI_CTRL_PWR_VBAT_DET (0x05CU)
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#define CVI_CTRL_PWR_RSTN (0x060U)
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#define CVI_CTRL_PWR_SEQ1 (0x064U)
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#define CVI_CTRL_PWR_SEQ2 (0x068U)
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#define CVI_CTRL_PWR_WAKEUP0 (0x06CU)
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#define CVI_CTRL_PWR_BUTTON1 (0x070U)
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#define CVI_CTRL_XTAL_XIN (0x074U)
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#define CVI_CTRL_PWR_GPIO0 (0x078U)
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#define CVI_CTRL_PWR_GPIO1 (0x07CU)
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#define CVI_CTRL_PWR_GPIO2 (0x080U)
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#define CVI_CTRL_SD1_GPIO1 (0x084U)
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#define CVI_CTRL_SD1_GPIO0 (0x088U)
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#define CVI_CTRL_SD1_D3 (0x08CU)
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#define CVI_CTRL_SD1_D2 (0x090U)
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#define CVI_CTRL_SD1_D1 (0x094U)
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#define CVI_CTRL_SD1_D0 (0x098U)
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#define CVI_CTRL_SD1_CMD (0x09CU)
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#define CVI_CTRL_SD1_CLK (0x0A0U)
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#define CVI_CTRL_PWM0_BUCK (0x0A4U)
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#define CVI_CTRL_ADC1 (0x0A8U)
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#define CVI_CTRL_USB_VBUS_DET (0x0ACU)
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#define CVI_CTRL_MUX_SPI1_MISO (0x0B0U)
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#define CVI_CTRL_MUX_SPI1_MOSI (0x0B4U)
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#define CVI_CTRL_MUX_SPI1_CS (0x0B8U)
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#define CVI_CTRL_MUX_SPI1_SCK (0x0BCU)
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#define CVI_CTRL_PAD_ETH_TXP (0x0C0U)
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#define CVI_CTRL_PAD_ETH_TXM (0x0C4U)
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#define CVI_CTRL_PAD_ETH_RXP (0x0C8U)
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#define CVI_CTRL_PAD_ETH_RXM (0x0CCU)
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#define CVI_CTRL_GPIO_RTX (0x0D0U)
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#define CVI_CTRL_PAD_MIPIRX4N (0x0D4U)
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#define CVI_CTRL_PAD_MIPIRX4P (0x0D8U)
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#define CVI_CTRL_PAD_MIPIRX3N (0x0DCU)
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#define CVI_CTRL_PAD_MIPIRX3P (0x0E0U)
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#define CVI_CTRL_PAD_MIPIRX2N (0x0E4U)
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#define CVI_CTRL_PAD_MIPIRX2P (0x0E8U)
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#define CVI_CTRL_PAD_MIPIRX1N (0x0ECU)
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#define CVI_CTRL_PAD_MIPIRX1P (0x0F0U)
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#define CVI_CTRL_PAD_MIPIRX0N (0x0F4U)
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#define CVI_CTRL_PAD_MIPIRX0P (0x0F8U)
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#define CVI_CTRL_PAD_MIPI_TXM2 (0x0FCU)
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#define CVI_CTRL_PAD_MIPI_TXP2 (0x100U)
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#define CVI_CTRL_PAD_MIPI_TXM1 (0x104U)
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#define CVI_CTRL_PAD_MIPI_TXP1 (0x108U)
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#define CVI_CTRL_PAD_MIPI_TXM0 (0x10CU)
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#define CVI_CTRL_PAD_MIPI_TXP0 (0x110U)
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#define CVI_CTRL_PKG_TYPE0 (0x114U)
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#define CVI_CTRL_PKG_TYPE1 (0x118U)
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#define CVI_CTRL_PKG_TYPE2 (0x11CU)
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#define CVI_CTRL_PAD_AUD_AINL_MIC (0x120U)
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#define CVI_CTRL_PAD_AUD_AINR_MIC (0x124U)
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#define CVI_CTRL_PAD_AUD_AOUTL (0x128U)
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#define CVI_CTRL_PAD_AUD_AOUTR (0x12CU)
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#endif /* DT_CV1800B_PINCTRL_H */
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