a2d6fbf5ff
In Linux IMX and IMXRT use the device tree to hold the anatop address. The anatop is used in clock drivers as it controls the internal PLLs This will move the macro from asm/arch-imxrt to the device tree. This presumably should also be done with the other IMX boards as well. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
148 lines
3.4 KiB
Plaintext
148 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) 2020
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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#include "armv7-m.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/imxrt1020-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/memory/imxrt-sdram.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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mmc0 = &usdhc1;
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serial0 = &lpuart1;
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};
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clocks {
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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osc: osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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soc {
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semc: semc@402f0000 {
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compatible = "fsl,imxrt-semc";
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reg = <0x402f0000 0x4000>;
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clocks = <&clks IMXRT1020_CLK_SEMC>;
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pinctrl-0 = <&pinctrl_semc>;
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pinctrl-names = "default";
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status = "okay";
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};
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lpuart1: serial@40184000 {
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compatible = "fsl,imxrt-lpuart";
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reg = <0x40184000 0x4000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMXRT1020_CLK_LPUART1>;
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clock-names = "per";
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status = "disabled";
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};
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iomuxc: iomuxc@401f8000 {
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compatible = "fsl,imxrt-iomuxc";
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reg = <0x401f8000 0x4000>;
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fsl,mux_mask = <0x7>;
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};
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anatop: anatop@400d8000 {
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compatible = "fsl,imxrt-anatop";
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reg = <0x400d8000 0x4000>;
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};
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clks: ccm@400fc000 {
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compatible = "fsl,imxrt1020-ccm";
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reg = <0x400fc000 0x4000>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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#clock-cells = <1>;
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};
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usdhc1: usdhc@402c0000 {
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compatible = "fsl,imxrt-usdhc";
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reg = <0x402c0000 0x10000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMXRT1020_CLK_USDHC1>;
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clock-names = "per";
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bus-width = <4>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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status = "disabled";
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};
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gpio1: gpio@401b8000 {
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compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
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reg = <0x401b8000 0x4000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@401bc000 {
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compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
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reg = <0x401bc000 0x4000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@401c0000 {
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compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
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reg = <0x401c0000 0x4000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@400c0000 {
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compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
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reg = <0x400c0000 0x4000>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpt1: gpt1@401ec000 {
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compatible = "fsl,imxrt-gpt";
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reg = <0x401ec000 0x4000>;
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interrupts = <100>;
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clocks = <&osc>;
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status = "disabled";
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};
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};
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};
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