3757be5a6a
This extra binding is non-standard and now unneeded as we bind the sysreset driver automatically. This matches what is done in Linux and allows us to more closely match the DTBs. Remove the binding and all users. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Tested-by: Jonathan Humphreys <j-humphreys@ti.com>
160 lines
2.2 KiB
Plaintext
160 lines
2.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* phyCORE-AM62x dts file for SPLs
|
|
* Copyright (C) 2022 - 2023 Phytec Messtechnik GmbH
|
|
* Author: Wadim Egorov <w.egorov@phytec.de>
|
|
*
|
|
* Product homepage:
|
|
* https://www.phytec.com/product/phyboard-am62x
|
|
*/
|
|
|
|
#include "k3-am625-phycore-som-binman.dtsi"
|
|
|
|
/ {
|
|
chosen {
|
|
stdout-path = "serial2:115200n8";
|
|
tick-timer = &main_timer0;
|
|
};
|
|
|
|
aliases {
|
|
mmc0 = &sdhci0;
|
|
mmc1 = &sdhci1;
|
|
};
|
|
|
|
memory@80000000 {
|
|
bootph-all;
|
|
};
|
|
};
|
|
|
|
&cpsw3g {
|
|
bootph-all;
|
|
};
|
|
|
|
&cpsw_port1 {
|
|
bootph-all;
|
|
};
|
|
|
|
&cpsw_port2 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&cpsw3g_phy1 {
|
|
bootph-all;
|
|
};
|
|
|
|
&fss {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_bcdma {
|
|
bootph-all;
|
|
reg = <0x00 0x485c0100 0x00 0x100>,
|
|
<0x00 0x4c000000 0x00 0x20000>,
|
|
<0x00 0x4a820000 0x00 0x20000>,
|
|
<0x00 0x4aa40000 0x00 0x20000>,
|
|
<0x00 0x4bc00000 0x00 0x100000>,
|
|
<0x00 0x48600000 0x00 0x8000>,
|
|
<0x00 0x484a4000 0x00 0x2000>,
|
|
<0x00 0x484c2000 0x00 0x2000>;
|
|
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
|
|
"ringrt" , "cfg", "tchan", "rchan";
|
|
};
|
|
|
|
&main_gpio0 {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_mdio1_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_i2c0 {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_i2c0_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_mmc0_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_mmc1_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_pktdma {
|
|
bootph-all;
|
|
reg = <0x00 0x485c0000 0x00 0x100>,
|
|
<0x00 0x4a800000 0x00 0x20000>,
|
|
<0x00 0x4aa00000 0x00 0x20000>,
|
|
<0x00 0x4b800000 0x00 0x200000>,
|
|
<0x00 0x485e0000 0x00 0x10000>,
|
|
<0x00 0x484a0000 0x00 0x2000>,
|
|
<0x00 0x484c0000 0x00 0x2000>,
|
|
<0x00 0x48430000 0x00 0x1000>;
|
|
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
|
|
"cfg", "tchan", "rchan", "rflow";
|
|
};
|
|
|
|
&main_rgmii1_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_timer0 {
|
|
clock-frequency = <25000000>;
|
|
};
|
|
|
|
&main_uart0 {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_uart0_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_uart1 {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_uart1_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&ospi0 {
|
|
bootph-all;
|
|
|
|
flash@0 {
|
|
bootph-all;
|
|
};
|
|
};
|
|
|
|
&ospi0_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&sdhci0 {
|
|
bootph-all;
|
|
};
|
|
|
|
&sdhci1 {
|
|
bootph-all;
|
|
};
|
|
|
|
&vcc_3v3_mmc {
|
|
bootph-all;
|
|
};
|
|
|
|
&vcc_5v0_som {
|
|
bootph-all;
|
|
};
|
|
|
|
&vddshv5_sdio {
|
|
bootph-all;
|
|
};
|
|
|
|
&wkup_uart0 {
|
|
bootph-all;
|
|
};
|