03ee0553a0
Sync linux dts files for rv1126 boards from linux v6.8-rc1 tag. Includes the newly added dts for Sonoff iHost. Signed-off-by: Tim Lunn <tim@feathertop.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
624 lines
16 KiB
Plaintext
624 lines
16 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/clock/rockchip,rv1126-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/power/rockchip,rv1126-power.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "rockchip,rv1126";
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interrupt-parent = <&gic>;
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aliases {
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i2c0 = &i2c0;
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i2c2 = &i2c2;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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enable-method = "psci";
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clocks = <&cru ARMCLK>;
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};
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cpu1: cpu@f01 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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enable-method = "psci";
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clocks = <&cru ARMCLK>;
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};
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cpu2: cpu@f02 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf02>;
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enable-method = "psci";
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clocks = <&cru ARMCLK>;
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};
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cpu3: cpu@f03 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf03>;
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enable-method = "psci";
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clocks = <&cru ARMCLK>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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display_subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop_out>;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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grf: syscon@fe000000 {
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compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
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reg = <0xfe000000 0x20000>;
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};
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pmugrf: syscon@fe020000 {
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compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
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reg = <0xfe020000 0x1000>;
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pmu_io_domains: io-domains {
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compatible = "rockchip,rv1126-pmu-io-voltage-domain";
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status = "disabled";
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};
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};
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qos_emmc: qos@fe860000 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe860000 0x20>;
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};
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qos_nandc: qos@fe860080 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe860080 0x20>;
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};
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qos_sfc: qos@fe860200 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe860200 0x20>;
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};
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qos_sdio: qos@fe86c000 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe86c000 0x20>;
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};
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qos_iep: qos@fe8a0000 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe8a0000 0x20>;
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};
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qos_rga_rd: qos@fe8a0080 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe8a0080 0x20>;
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};
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qos_rga_wr: qos@fe8a0100 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe8a0100 0x20>;
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};
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qos_vop: qos@fe8a0180 {
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compatible = "rockchip,rv1126-qos", "syscon";
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reg = <0xfe8a0180 0x20>;
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};
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gic: interrupt-controller@feff0000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0xfeff1000 0x1000>,
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<0xfeff2000 0x2000>,
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<0xfeff4000 0x2000>,
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<0xfeff6000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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pmu: power-management@ff3e0000 {
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compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
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reg = <0xff3e0000 0x1000>;
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power: power-controller {
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compatible = "rockchip,rv1126-power-controller";
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#power-domain-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domain@RV1126_PD_NVM {
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reg = <RV1126_PD_NVM>;
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clocks = <&cru HCLK_EMMC>,
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<&cru CLK_EMMC>,
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<&cru HCLK_NANDC>,
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<&cru CLK_NANDC>,
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<&cru HCLK_SFC>,
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<&cru HCLK_SFCXIP>,
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<&cru SCLK_SFC>;
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pm_qos = <&qos_emmc>,
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<&qos_nandc>,
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<&qos_sfc>;
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#power-domain-cells = <0>;
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};
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power-domain@RV1126_PD_SDIO {
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reg = <RV1126_PD_SDIO>;
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clocks = <&cru HCLK_SDIO>,
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<&cru CLK_SDIO>;
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pm_qos = <&qos_sdio>;
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#power-domain-cells = <0>;
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};
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power-domain@RV1126_PD_VO {
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reg = <RV1126_PD_VO>;
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clocks = <&cru ACLK_RGA>,
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<&cru HCLK_RGA>,
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<&cru CLK_RGA_CORE>,
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<&cru ACLK_VOP>,
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<&cru HCLK_VOP>,
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<&cru DCLK_VOP>,
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<&cru PCLK_DSIHOST>,
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<&cru ACLK_IEP>,
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<&cru HCLK_IEP>,
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<&cru CLK_IEP_CORE>;
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pm_qos = <&qos_rga_rd>,
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<&qos_rga_wr>,
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<&qos_vop>,
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<&qos_iep>;
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#power-domain-cells = <0>;
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};
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};
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};
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i2c0: i2c@ff3f0000 {
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compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
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reg = <0xff3f0000 0x1000>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,grf = <&pmugrf>;
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clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
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clock-names = "i2c", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@ff400000 {
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compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
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reg = <0xff400000 0x1000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,grf = <&pmugrf>;
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clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
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clock-names = "i2c", "pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart1: serial@ff410000 {
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compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
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reg = <0xff410000 0x100>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmac 7>, <&dmac 6>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1m0_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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pwm2: pwm@ff430020 {
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compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
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reg = <0xff430020 0x10>;
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clock-names = "pwm", "pclk";
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clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm2m0_pins>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pmucru: clock-controller@ff480000 {
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compatible = "rockchip,rv1126-pmucru";
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reg = <0xff480000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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cru: clock-controller@ff490000 {
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compatible = "rockchip,rv1126-cru";
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reg = <0xff490000 0x1000>;
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clocks = <&xin24m>;
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clock-names = "xin24m";
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dmac: dma-controller@ff4e0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xff4e0000 0x4000>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-periph-burst;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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};
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pwm11: pwm@ff550030 {
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compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
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reg = <0xff550030 0x10>;
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clock-names = "pwm", "pclk";
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clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
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pinctrl-0 = <&pwm11m0_pins>;
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pinctrl-names = "default";
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#pwm-cells = <3>;
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status = "disabled";
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};
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uart0: serial@ff560000 {
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compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
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reg = <0xff560000 0x100>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmac 5>, <&dmac 4>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@ff570000 {
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compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
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reg = <0xff570000 0x100>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmac 9>, <&dmac 8>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m1_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@ff580000 {
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compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
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reg = <0xff580000 0x100>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmac 11>, <&dmac 10>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart3m0_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart4: serial@ff590000 {
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compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
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reg = <0xff590000 0x100>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmac 13>, <&dmac 12>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart4m0_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart5: serial@ff5a0000 {
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compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
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reg = <0xff5a0000 0x100>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmac 15>, <&dmac 14>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&uart5m0_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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saradc: adc@ff5e0000 {
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compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
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reg = <0xff5e0000 0x100>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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resets = <&cru SRST_SARADC_P>;
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reset-names = "saradc-apb";
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status = "disabled";
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};
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timer0: timer@ff660000 {
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compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
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reg = <0xff660000 0x20>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
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clock-names = "pclk", "timer";
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};
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vop: vop@ffb00000 {
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compatible = "rockchip,rv1126-vop";
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reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
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reset-names = "axi", "ahb", "dclk";
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resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
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iommus = <&vop_mmu>;
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power-domains = <&power RV1126_PD_VO>;
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status = "disabled";
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vop_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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vop_out_rgb: endpoint@0 {
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reg = <0>;
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};
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vop_out_dsi: endpoint@1 {
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reg = <1>;
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};
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};
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};
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vop_mmu: iommu@ffb00f00 {
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compatible = "rockchip,iommu";
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reg = <0xffb00f00 0x100>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "aclk", "iface";
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clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
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#iommu-cells = <0>;
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power-domains = <&power RV1126_PD_VO>;
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status = "disabled";
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};
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gmac: ethernet@ffc40000 {
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compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
|
|
reg = <0xffc40000 0x4000>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq", "eth_wake_irq";
|
|
rockchip,grf = <&grf>;
|
|
clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
|
|
<&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
|
|
<&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
|
|
<&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
|
|
clock-names = "stmmaceth", "mac_clk_rx",
|
|
"mac_clk_tx", "clk_mac_ref",
|
|
"aclk_mac", "pclk_mac",
|
|
"clk_mac_speed", "ptp_ref";
|
|
resets = <&cru SRST_GMAC_A>;
|
|
reset-names = "stmmaceth";
|
|
|
|
snps,mixed-burst;
|
|
snps,tso;
|
|
|
|
snps,axi-config = <&stmmac_axi_setup>;
|
|
snps,mtl-rx-config = <&mtl_rx_setup>;
|
|
snps,mtl-tx-config = <&mtl_tx_setup>;
|
|
status = "disabled";
|
|
|
|
mdio: mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
};
|
|
|
|
stmmac_axi_setup: stmmac-axi-config {
|
|
snps,wr_osr_lmt = <4>;
|
|
snps,rd_osr_lmt = <8>;
|
|
snps,blen = <0 0 0 0 16 8 4>;
|
|
};
|
|
|
|
mtl_rx_setup: rx-queues-config {
|
|
snps,rx-queues-to-use = <1>;
|
|
queue0 {};
|
|
};
|
|
|
|
mtl_tx_setup: tx-queues-config {
|
|
snps,tx-queues-to-use = <1>;
|
|
queue0 {};
|
|
};
|
|
};
|
|
|
|
emmc: mmc@ffc50000 {
|
|
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0xffc50000 0x4000>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
|
|
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
max-frequency = <200000000>;
|
|
power-domains = <&power RV1126_PD_NVM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc: mmc@ffc60000 {
|
|
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0xffc60000 0x4000>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
|
|
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
max-frequency = <200000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdio: mmc@ffc70000 {
|
|
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0xffc70000 0x4000>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
|
|
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
max-frequency = <200000000>;
|
|
power-domains = <&power RV1126_PD_SDIO>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sfc: spi@ffc90000 {
|
|
compatible = "rockchip,sfc";
|
|
reg = <0xffc90000 0x4000>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
assigned-clocks = <&cru SCLK_SFC>;
|
|
assigned-clock-rates = <80000000>;
|
|
clock-names = "clk_sfc", "hclk_sfc";
|
|
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
|
power-domains = <&power RV1126_PD_NVM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rv1126-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
rockchip,pmu = <&pmugrf>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
gpio0: gpio@ff460000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff460000 0x100>;
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio@ff620000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff620000 0x100>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@ff630000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff630000 0x100>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@ff640000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff640000 0x100>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio@ff650000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0xff650000 0x100>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "rv1126-pinctrl.dtsi"
|