237 lines
8.1 KiB
Plaintext
237 lines
8.1 KiB
Plaintext
/*
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* Copyright 2018-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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void Clock_Init()
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{
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unsigned int reg;
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// Enable all clocks
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MEM_WriteU32(0x400FC068,0xffffffff);
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MEM_WriteU32(0x400FC06C,0xffffffff);
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MEM_WriteU32(0x400FC070,0xffffffff);
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MEM_WriteU32(0x400FC074,0xffffffff);
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MEM_WriteU32(0x400FC078,0xffffffff);
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MEM_WriteU32(0x400FC07C,0xffffffff);
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MEM_WriteU32(0x400FC080,0xffffffff);
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// IPG_PODF: 2 divide by 3
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MEM_WriteU32(0x400FC014,0x000A8200);
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// PERCLK_PODF: 1 divide by 2
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MEM_WriteU32(0x400FC01C,0x04900001);
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// Enable SYS PLL but keep it bypassed.
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MEM_WriteU32(0x400D8030,0x00012001);
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do
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{
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reg = MEM_ReadU32(0x400D8030);
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} while((reg & 0x80000000) == 0);
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// Disable bypass of SYS PLL
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MEM_WriteU32(0x400D8030,0x00002001);
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// PFD2_FRAC: 24, PLL2 PFD2=528*18/PFD2_FRAC=396
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// Ungate SYS PLL PFD2
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reg = MEM_ReadU32(0x400D8100);
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reg &= ~0xBF0000;
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reg |= 0x180000;
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MEM_WriteU32(0x400D8100, reg);
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// SEMC_ALT_CLK_SEL: 0 PLL2 (SYS PLL) PFD2
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// SEMC_CLK_SEL: 1 SEMC_ALT_CLK
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// SEMC_PODF: 2 divide by 3
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reg = MEM_ReadU32(0x400FC014);
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reg &= ~0x700C0;
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reg |= 0x20040;
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MEM_WriteU32(0x400FC014, reg);
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// Disable MPU which will be enabled by ROM to prevent code execution
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reg = MEM_ReadU32(0xE000ED94);
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reg &= ~0x1;
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MEM_WriteU32(0xE000ED94, reg);
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Report("Clock Init Done");
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}
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void SDRAM_WaitIpCmdDone(void)
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{
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unsigned int reg;
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do
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{
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reg = MEM_ReadU32(0x402F003C);
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}while((reg & 0x3) == 0);
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}
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void SDRAM_Init() {
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// Config IOMUX for SDRAM
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MEM_WriteU32(0x401F8014,0x00000000); // EMC_00
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MEM_WriteU32(0x401F8018,0x00000000); // EMC_01
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MEM_WriteU32(0x401F801C,0x00000000); // EMC_02
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MEM_WriteU32(0x401F8020,0x00000000); // EMC_03
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MEM_WriteU32(0x401F8024,0x00000000); // EMC_04
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MEM_WriteU32(0x401F8028,0x00000000); // EMC_05
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MEM_WriteU32(0x401F802C,0x00000000); // EMC_06
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MEM_WriteU32(0x401F8030,0x00000000); // EMC_07
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MEM_WriteU32(0x401F8034,0x00000000); // EMC_08
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MEM_WriteU32(0x401F8038,0x00000000); // EMC_09
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MEM_WriteU32(0x401F803C,0x00000000); // EMC_10
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MEM_WriteU32(0x401F8040,0x00000000); // EMC_11
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MEM_WriteU32(0x401F8044,0x00000000); // EMC_12
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MEM_WriteU32(0x401F8048,0x00000000); // EMC_13
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MEM_WriteU32(0x401F804C,0x00000000); // EMC_14
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MEM_WriteU32(0x401F8050,0x00000000); // EMC_15
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MEM_WriteU32(0x401F8054,0x00000000); // EMC_16
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MEM_WriteU32(0x401F8058,0x00000000); // EMC_17
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MEM_WriteU32(0x401F805C,0x00000000); // EMC_18
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MEM_WriteU32(0x401F8060,0x00000000); // EMC_19
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MEM_WriteU32(0x401F8064,0x00000000); // EMC_20
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MEM_WriteU32(0x401F8068,0x00000000); // EMC_21
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MEM_WriteU32(0x401F806C,0x00000000); // EMC_22
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MEM_WriteU32(0x401F8070,0x00000000); // EMC_23
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MEM_WriteU32(0x401F8074,0x00000000); // EMC_24
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MEM_WriteU32(0x401F8078,0x00000000); // EMC_25
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MEM_WriteU32(0x401F807C,0x00000000); // EMC_26
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MEM_WriteU32(0x401F8080,0x00000000); // EMC_27
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MEM_WriteU32(0x401F8084,0x00000010); // EMC_28, DQS PIN, enable SION
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MEM_WriteU32(0x401F8088,0x00000000); // EMC_29
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MEM_WriteU32(0x401F808C,0x00000000); // EMC_30
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MEM_WriteU32(0x401F8090,0x00000000); // EMC_31
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MEM_WriteU32(0x401F8094,0x00000000); // EMC_32
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MEM_WriteU32(0x401F8098,0x00000000); // EMC_33
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MEM_WriteU32(0x401F809C,0x00000000); // EMC_34
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MEM_WriteU32(0x401F80A0,0x00000000); // EMC_35
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MEM_WriteU32(0x401F80A4,0x00000000); // EMC_36
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MEM_WriteU32(0x401F80A8,0x00000000); // EMC_37
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MEM_WriteU32(0x401F80AC,0x00000000); // EMC_38
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MEM_WriteU32(0x401F80B0,0x00000000); // EMC_39
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// PAD ctrl
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// drive strength = 0x7 to increase drive strength
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// otherwise the data7 bit may fail.
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MEM_WriteU32(0x401F8188,0x000000F1); // EMC_00
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MEM_WriteU32(0x401F818C,0x000000F1); // EMC_01
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MEM_WriteU32(0x401F8190,0x000000F1); // EMC_02
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MEM_WriteU32(0x401F8194,0x000000F1); // EMC_03
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MEM_WriteU32(0x401F8198,0x000000F1); // EMC_04
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MEM_WriteU32(0x401F819C,0x000000F1); // EMC_05
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MEM_WriteU32(0x401F81A0,0x000000F1); // EMC_06
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MEM_WriteU32(0x401F81A4,0x000000F1); // EMC_07
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MEM_WriteU32(0x401F81A8,0x000000F1); // EMC_08
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MEM_WriteU32(0x401F81AC,0x000000F1); // EMC_09
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MEM_WriteU32(0x401F81B0,0x000000F1); // EMC_10
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MEM_WriteU32(0x401F81B4,0x000000F1); // EMC_11
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MEM_WriteU32(0x401F81B8,0x000000F1); // EMC_12
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MEM_WriteU32(0x401F81BC,0x000000F1); // EMC_13
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MEM_WriteU32(0x401F81C0,0x000000F1); // EMC_14
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MEM_WriteU32(0x401F81C4,0x000000F1); // EMC_15
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MEM_WriteU32(0x401F81C8,0x000000F1); // EMC_16
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MEM_WriteU32(0x401F81CC,0x000000F1); // EMC_17
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MEM_WriteU32(0x401F81D0,0x000000F1); // EMC_18
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MEM_WriteU32(0x401F81D4,0x000000F1); // EMC_19
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MEM_WriteU32(0x401F81D8,0x000000F1); // EMC_20
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MEM_WriteU32(0x401F81DC,0x000000F1); // EMC_21
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MEM_WriteU32(0x401F81E0,0x000000F1); // EMC_22
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MEM_WriteU32(0x401F81E4,0x000000F1); // EMC_23
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MEM_WriteU32(0x401F81E8,0x000000F1); // EMC_24
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MEM_WriteU32(0x401F81EC,0x000000F1); // EMC_25
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MEM_WriteU32(0x401F81F0,0x000000F1); // EMC_26
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MEM_WriteU32(0x401F81F4,0x000000F1); // EMC_27
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MEM_WriteU32(0x401F81F8,0x000000F1); // EMC_28
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MEM_WriteU32(0x401F81FC,0x000000F1); // EMC_29
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MEM_WriteU32(0x401F8200,0x000000F1); // EMC_30
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MEM_WriteU32(0x401F8204,0x000000F1); // EMC_31
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MEM_WriteU32(0x401F8208,0x000000F1); // EMC_32
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MEM_WriteU32(0x401F820C,0x000000F1); // EMC_33
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MEM_WriteU32(0x401F8210,0x000000F1); // EMC_34
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MEM_WriteU32(0x401F8214,0x000000F1); // EMC_35
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MEM_WriteU32(0x401F8218,0x000000F1); // EMC_36
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MEM_WriteU32(0x401F821C,0x000000F1); // EMC_37
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MEM_WriteU32(0x401F8220,0x000000F1); // EMC_38
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MEM_WriteU32(0x401F8224,0x000000F1); // EMC_39
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// Config SDR Controller Registers/
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MEM_WriteU32(0x402F0000,0x10000004); // MCR
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MEM_WriteU32(0x402F0008,0x00000081); // BMCR0
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MEM_WriteU32(0x402F000C,0x00000081); // BMCR1
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MEM_WriteU32(0x402F0010,0x8000001B); // BR0, 32MB
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MEM_WriteU32(0x402F0014,0x8200001B); // BR1, 32MB
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MEM_WriteU32(0x402F0018,0x8400001B); // BR2, 32MB
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MEM_WriteU32(0x402F001C,0x8600001B); // BR3, 32MB
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MEM_WriteU32(0x402F0020,0x90000021); // BR4,
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MEM_WriteU32(0x402F0024,0xA0000019); // BR5,
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MEM_WriteU32(0x402F0028,0xA8000017); // BR6,
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MEM_WriteU32(0x402F002C,0xA900001B); // BR7,
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MEM_WriteU32(0x402F0030,0x00000021); // BR8,
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MEM_WriteU32(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE, SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE.
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// MEM_WriteU32(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1
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MEM_WriteU32(0x402F0040,0x00000F31); // SDRAMCR0
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MEM_WriteU32(0x402F0044,0x00652922); // SDRAMCR1
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MEM_WriteU32(0x402F0048,0x00010920); // SDRAMCR2
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MEM_WriteU32(0x402F004C,0x50210A09); // SDRAMCR3
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MEM_WriteU32(0x402F0080,0x00000021); // DBICR0
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MEM_WriteU32(0x402F0084,0x00888888); // DBICR1
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MEM_WriteU32(0x402F0094,0x00000002); // IPCR1
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MEM_WriteU32(0x402F0098,0x00000000); // IPCR2
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MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
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MEM_WriteU32(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
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SDRAM_WaitIpCmdDone();
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MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
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MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF
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SDRAM_WaitIpCmdDone();
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MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
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MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF
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SDRAM_WaitIpCmdDone();
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MEM_WriteU32(0x402F00A0,0x00000033); // IPTXDAT
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MEM_WriteU32(0x402F0090,0x80000000); // IPCR0
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MEM_WriteU32(0x402F009C,0xA55A000A); // SD_CC_IMS
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SDRAM_WaitIpCmdDone();
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MEM_WriteU32(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done.
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Report("SDRAM Init Done");
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}
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void RestoreFlexRAM()
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{
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unsigned int base;
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unsigned int value;
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base = 0x400AC000;
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value = MEM_ReadU32(base + 0x44);
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value &= ~(0xFFFF);
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value |= 0x5FA5;
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MEM_WriteU32(base + 0x44, value);
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value = MEM_ReadU32(base + 0x40);
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value |= (1 << 2);
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MEM_WriteU32(base + 0x40, value);
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Report("FlexRAM configuration is restored");
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}
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/* ConfigTarget */
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void ConfigTargetSettings(void)
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{
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Report("Config JTAG Speed to 4000kHz");
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JTAG_Speed = 4000;
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}
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/* SetupTarget */
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void SetupTarget(void) {
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Report("Enabling i.MXRT SDRAM");
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RestoreFlexRAM();
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Clock_Init();
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SDRAM_Init();
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}
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/* AfterResetTarget */
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void AfterResetTarget(void) {
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RestoreFlexRAM();
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Clock_Init();
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SDRAM_Init();
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}
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