Initial commit.

Signed-off-by: Yilin Sun <imi415@imi.moe>

.gitignore

@@ -0,0 +1,2 @@
+/target
+/Cargo.lock

Cargo.toml

@@ -0,0 +1,15 @@
+[package]
+name = "ch57x-pac"
+version = "0.1.0"
+edition = "2021"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+critical-section = { version = "1.0", optional = true }
+cortex-m = "0.7.6"
+cortex-m-rt = { version = "0.6.13", optional = true }
+vcell = "0.1.2"
+
+[features]
+rt = ["cortex-m-rt/device"]

build.rs

@@ -0,0 +1,16 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+fn main() {
+    if env::var_os("CARGO_FEATURE_RT").is_some() {
+        let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+        File::create(out.join("device.x"))
+            .unwrap()
+            .write_all(include_bytes!("device.x"))
+            .unwrap();
+        println!("cargo:rustc-link-search={}", out.display());
+        println!("cargo:rerun-if-changed=device.x");
+    }
+    println!("cargo:rerun-if-changed=build.rs");
+}

device.x

@@ -0,0 +1,21 @@
+PROVIDE(TMR0 = DefaultHandler);
+PROVIDE(GPIO = DefaultHandler);
+PROVIDE(SLAVE = DefaultHandler);
+PROVIDE(SPI0 = DefaultHandler);
+PROVIDE(BB = DefaultHandler);
+PROVIDE(LLE = DefaultHandler);
+PROVIDE(USB = DefaultHandler);
+PROVIDE(ETH = DefaultHandler);
+PROVIDE(TMR1 = DefaultHandler);
+PROVIDE(TMR2 = DefaultHandler);
+PROVIDE(UART0 = DefaultHandler);
+PROVIDE(UART1 = DefaultHandler);
+PROVIDE(RTC = DefaultHandler);
+PROVIDE(ADC = DefaultHandler);
+PROVIDE(SPI1 = DefaultHandler);
+PROVIDE(LED = DefaultHandler);
+PROVIDE(TMR3 = DefaultHandler);
+PROVIDE(UART2 = DefaultHandler);
+PROVIDE(UART3 = DefaultHandler);
+PROVIDE(WDOG_BAT = DefaultHandler);
+

src/eth.rs

@@ -0,0 +1,180 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 0x03],
+    #[doc = "0x03 - soso"]
+    pub r8_eth_eie: R8_ETH_EIE,
+    #[doc = "0x04 - soso"]
+    pub r8_eth_eir: R8_ETH_EIR,
+    #[doc = "0x05 - soso"]
+    pub r8_eth_estat: R8_ETH_ESTAT,
+    #[doc = "0x06 - soso"]
+    pub r8_eth_econ2: R8_ETH_ECON2,
+    #[doc = "0x07 - soso"]
+    pub r8_eth_econ1: R8_ETH_ECON1,
+    #[doc = "0x08 - soso"]
+    pub r16_eth_etxst: R16_ETH_ETXST,
+    #[doc = "0x0a - soso"]
+    pub r16_eth_etxln: R16_ETH_ETXLN,
+    #[doc = "0x0c - soso"]
+    pub r16_eth_erxst: R16_ETH_ERXST,
+    #[doc = "0x0e - soso"]
+    pub r16_eth_erxln: R16_ETH_ERXLN,
+    #[doc = "0x10 - soso"]
+    pub r8_eth_eht0: R8_ETH_EHT0,
+    #[doc = "0x11 - soso"]
+    pub r8_eth_eht1: R8_ETH_EHT1,
+    #[doc = "0x12 - soso"]
+    pub r8_eth_eht2: R8_ETH_EHT2,
+    #[doc = "0x13 - soso"]
+    pub r8_eth_eht3: R8_ETH_EHT3,
+    #[doc = "0x14 - soso"]
+    pub r8_eth_eht4: R8_ETH_EHT4,
+    #[doc = "0x15 - soso"]
+    pub r8_eth_eht5: R8_ETH_EHT5,
+    #[doc = "0x16 - soso"]
+    pub r8_eth_eht6: R8_ETH_EHT6,
+    #[doc = "0x17 - soso"]
+    pub r8_eth_eht7: R8_ETH_EHT7,
+    #[doc = "0x18 - soso"]
+    pub r8_eth_erxfcon: R8_ETH_ERXFCON,
+    #[doc = "0x19 - soso"]
+    pub r8_eth_macon1: R8_ETH_MACON1,
+    #[doc = "0x1a - soso"]
+    pub r8_eth_macon2: R8_ETH_MACON2,
+    #[doc = "0x1b - soso"]
+    pub r8_eth_mabbipg: R8_ETH_MABBIPG,
+    #[doc = "0x1c - soso"]
+    pub r16_eth_epaus: R16_ETH_EPAUS,
+    #[doc = "0x1e - soso"]
+    pub r16_eth_mamxfl: R16_ETH_MAMXFL,
+    #[doc = "0x20 - soso"]
+    pub r16_eth_mird: R16_ETH_MIRD,
+    _reserved24: [u8; 0x02],
+    #[doc = "0x24 - soso"]
+    pub r8_eth_miregadr: R8_ETH_MIREGADR,
+    #[doc = "0x25 - soso"]
+    pub r8_eth_mistat: R8_ETH_MISTAT,
+    #[doc = "0x26 - soso"]
+    pub r16_eth_miwr: R16_ETH_MIWR,
+    #[doc = "0x28 - soso"]
+    pub r32_eth_maadrl: R32_ETH_MAADRL,
+    #[doc = "0x2c - soso"]
+    pub r16_eth_maadrh: R16_ETH_MAADRH,
+}
+#[doc = "R8_ETH_EIE (rw) register accessor: an alias for `Reg<R8_ETH_EIE_SPEC>`"]
+pub type R8_ETH_EIE = crate::Reg<r8_eth_eie::R8_ETH_EIE_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_eie;
+#[doc = "R8_ETH_EIR (rw) register accessor: an alias for `Reg<R8_ETH_EIR_SPEC>`"]
+pub type R8_ETH_EIR = crate::Reg<r8_eth_eir::R8_ETH_EIR_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_eir;
+#[doc = "R8_ETH_ESTAT (r) register accessor: an alias for `Reg<R8_ETH_ESTAT_SPEC>`"]
+pub type R8_ETH_ESTAT = crate::Reg<r8_eth_estat::R8_ETH_ESTAT_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_estat;
+#[doc = "R8_ETH_ECON2 (rw) register accessor: an alias for `Reg<R8_ETH_ECON2_SPEC>`"]
+pub type R8_ETH_ECON2 = crate::Reg<r8_eth_econ2::R8_ETH_ECON2_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_econ2;
+#[doc = "R8_ETH_ECON1 (rw) register accessor: an alias for `Reg<R8_ETH_ECON1_SPEC>`"]
+pub type R8_ETH_ECON1 = crate::Reg<r8_eth_econ1::R8_ETH_ECON1_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_econ1;
+#[doc = "R16_ETH_ETXST (rw) register accessor: an alias for `Reg<R16_ETH_ETXST_SPEC>`"]
+pub type R16_ETH_ETXST = crate::Reg<r16_eth_etxst::R16_ETH_ETXST_SPEC>;
+#[doc = "soso"]
+pub mod r16_eth_etxst;
+#[doc = "R16_ETH_ETXLN (rw) register accessor: an alias for `Reg<R16_ETH_ETXLN_SPEC>`"]
+pub type R16_ETH_ETXLN = crate::Reg<r16_eth_etxln::R16_ETH_ETXLN_SPEC>;
+#[doc = "soso"]
+pub mod r16_eth_etxln;
+#[doc = "R16_ETH_ERXST (rw) register accessor: an alias for `Reg<R16_ETH_ERXST_SPEC>`"]
+pub type R16_ETH_ERXST = crate::Reg<r16_eth_erxst::R16_ETH_ERXST_SPEC>;
+#[doc = "soso"]
+pub mod r16_eth_erxst;
+#[doc = "R16_ETH_ERXLN (rw) register accessor: an alias for `Reg<R16_ETH_ERXLN_SPEC>`"]
+pub type R16_ETH_ERXLN = crate::Reg<r16_eth_erxln::R16_ETH_ERXLN_SPEC>;
+#[doc = "soso"]
+pub mod r16_eth_erxln;
+#[doc = "R8_ETH_EHT0 (rw) register accessor: an alias for `Reg<R8_ETH_EHT0_SPEC>`"]
+pub type R8_ETH_EHT0 = crate::Reg<r8_eth_eht0::R8_ETH_EHT0_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_eht0;
+#[doc = "R8_ETH_EHT1 (rw) register accessor: an alias for `Reg<R8_ETH_EHT1_SPEC>`"]
+pub type R8_ETH_EHT1 = crate::Reg<r8_eth_eht1::R8_ETH_EHT1_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_eht1;
+#[doc = "R8_ETH_EHT2 (rw) register accessor: an alias for `Reg<R8_ETH_EHT2_SPEC>`"]
+pub type R8_ETH_EHT2 = crate::Reg<r8_eth_eht2::R8_ETH_EHT2_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_eht2;
+#[doc = "R8_ETH_EHT3 (rw) register accessor: an alias for `Reg<R8_ETH_EHT3_SPEC>`"]
+pub type R8_ETH_EHT3 = crate::Reg<r8_eth_eht3::R8_ETH_EHT3_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_eht3;
+#[doc = "R8_ETH_EHT4 (rw) register accessor: an alias for `Reg<R8_ETH_EHT4_SPEC>`"]
+pub type R8_ETH_EHT4 = crate::Reg<r8_eth_eht4::R8_ETH_EHT4_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_eht4;
+#[doc = "R8_ETH_EHT5 (rw) register accessor: an alias for `Reg<R8_ETH_EHT5_SPEC>`"]
+pub type R8_ETH_EHT5 = crate::Reg<r8_eth_eht5::R8_ETH_EHT5_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_eht5;
+#[doc = "R8_ETH_EHT6 (rw) register accessor: an alias for `Reg<R8_ETH_EHT6_SPEC>`"]
+pub type R8_ETH_EHT6 = crate::Reg<r8_eth_eht6::R8_ETH_EHT6_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_eht6;
+#[doc = "R8_ETH_EHT7 (rw) register accessor: an alias for `Reg<R8_ETH_EHT7_SPEC>`"]
+pub type R8_ETH_EHT7 = crate::Reg<r8_eth_eht7::R8_ETH_EHT7_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_eht7;
+#[doc = "R8_ETH_ERXFCON (rw) register accessor: an alias for `Reg<R8_ETH_ERXFCON_SPEC>`"]
+pub type R8_ETH_ERXFCON = crate::Reg<r8_eth_erxfcon::R8_ETH_ERXFCON_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_erxfcon;
+#[doc = "R8_ETH_MACON1 (rw) register accessor: an alias for `Reg<R8_ETH_MACON1_SPEC>`"]
+pub type R8_ETH_MACON1 = crate::Reg<r8_eth_macon1::R8_ETH_MACON1_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_macon1;
+#[doc = "R8_ETH_MACON2 (rw) register accessor: an alias for `Reg<R8_ETH_MACON2_SPEC>`"]
+pub type R8_ETH_MACON2 = crate::Reg<r8_eth_macon2::R8_ETH_MACON2_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_macon2;
+#[doc = "R8_ETH_MABBIPG (rw) register accessor: an alias for `Reg<R8_ETH_MABBIPG_SPEC>`"]
+pub type R8_ETH_MABBIPG = crate::Reg<r8_eth_mabbipg::R8_ETH_MABBIPG_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_mabbipg;
+#[doc = "R16_ETH_EPAUS (rw) register accessor: an alias for `Reg<R16_ETH_EPAUS_SPEC>`"]
+pub type R16_ETH_EPAUS = crate::Reg<r16_eth_epaus::R16_ETH_EPAUS_SPEC>;
+#[doc = "soso"]
+pub mod r16_eth_epaus;
+#[doc = "R16_ETH_MAMXFL (rw) register accessor: an alias for `Reg<R16_ETH_MAMXFL_SPEC>`"]
+pub type R16_ETH_MAMXFL = crate::Reg<r16_eth_mamxfl::R16_ETH_MAMXFL_SPEC>;
+#[doc = "soso"]
+pub mod r16_eth_mamxfl;
+#[doc = "R16_ETH_MIRD (rw) register accessor: an alias for `Reg<R16_ETH_MIRD_SPEC>`"]
+pub type R16_ETH_MIRD = crate::Reg<r16_eth_mird::R16_ETH_MIRD_SPEC>;
+#[doc = "soso"]
+pub mod r16_eth_mird;
+#[doc = "R8_ETH_MIREGADR (rw) register accessor: an alias for `Reg<R8_ETH_MIREGADR_SPEC>`"]
+pub type R8_ETH_MIREGADR = crate::Reg<r8_eth_miregadr::R8_ETH_MIREGADR_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_miregadr;
+#[doc = "R8_ETH_MISTAT (r) register accessor: an alias for `Reg<R8_ETH_MISTAT_SPEC>`"]
+pub type R8_ETH_MISTAT = crate::Reg<r8_eth_mistat::R8_ETH_MISTAT_SPEC>;
+#[doc = "soso"]
+pub mod r8_eth_mistat;
+#[doc = "R16_ETH_MIWR (w) register accessor: an alias for `Reg<R16_ETH_MIWR_SPEC>`"]
+pub type R16_ETH_MIWR = crate::Reg<r16_eth_miwr::R16_ETH_MIWR_SPEC>;
+#[doc = "soso"]
+pub mod r16_eth_miwr;
+#[doc = "R32_ETH_MAADRL (rw) register accessor: an alias for `Reg<R32_ETH_MAADRL_SPEC>`"]
+pub type R32_ETH_MAADRL = crate::Reg<r32_eth_maadrl::R32_ETH_MAADRL_SPEC>;
+#[doc = "soso"]
+pub mod r32_eth_maadrl;
+#[doc = "R16_ETH_MAADRH (rw) register accessor: an alias for `Reg<R16_ETH_MAADRH_SPEC>`"]
+pub type R16_ETH_MAADRH = crate::Reg<r16_eth_maadrh::R16_ETH_MAADRH_SPEC>;
+#[doc = "soso"]
+pub mod r16_eth_maadrh;

src/eth/r16_eth_epaus.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_ETH_EPAUS` reader"]
+pub struct R(crate::R<R16_ETH_EPAUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_ETH_EPAUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_ETH_EPAUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_ETH_EPAUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_ETH_EPAUS` writer"]
+pub struct W(crate::W<R16_ETH_EPAUS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_ETH_EPAUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_ETH_EPAUS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_ETH_EPAUS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_eth_epaus](index.html) module"]
+pub struct R16_ETH_EPAUS_SPEC;
+impl crate::RegisterSpec for R16_ETH_EPAUS_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_eth_epaus::R](R) reader structure"]
+impl crate::Readable for R16_ETH_EPAUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_eth_epaus::W](W) writer structure"]
+impl crate::Writable for R16_ETH_EPAUS_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_ETH_EPAUS to value 0"]
+impl crate::Resettable for R16_ETH_EPAUS_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r16_eth_erxln.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_ETH_ERXLN` reader"]
+pub struct R(crate::R<R16_ETH_ERXLN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_ETH_ERXLN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_ETH_ERXLN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_ETH_ERXLN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_ETH_ERXLN` writer"]
+pub struct W(crate::W<R16_ETH_ERXLN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_ETH_ERXLN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_ETH_ERXLN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_ETH_ERXLN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_eth_erxln](index.html) module"]
+pub struct R16_ETH_ERXLN_SPEC;
+impl crate::RegisterSpec for R16_ETH_ERXLN_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_eth_erxln::R](R) reader structure"]
+impl crate::Readable for R16_ETH_ERXLN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_eth_erxln::W](W) writer structure"]
+impl crate::Writable for R16_ETH_ERXLN_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_ETH_ERXLN to value 0"]
+impl crate::Resettable for R16_ETH_ERXLN_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r16_eth_erxst.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_ETH_ERXST` reader"]
+pub struct R(crate::R<R16_ETH_ERXST_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_ETH_ERXST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_ETH_ERXST_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_ETH_ERXST_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_ETH_ERXST` writer"]
+pub struct W(crate::W<R16_ETH_ERXST_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_ETH_ERXST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_ETH_ERXST_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_ETH_ERXST_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_eth_erxst](index.html) module"]
+pub struct R16_ETH_ERXST_SPEC;
+impl crate::RegisterSpec for R16_ETH_ERXST_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_eth_erxst::R](R) reader structure"]
+impl crate::Readable for R16_ETH_ERXST_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_eth_erxst::W](W) writer structure"]
+impl crate::Writable for R16_ETH_ERXST_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_ETH_ERXST to value 0"]
+impl crate::Resettable for R16_ETH_ERXST_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r16_eth_etxln.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_ETH_ETXLN` reader"]
+pub struct R(crate::R<R16_ETH_ETXLN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_ETH_ETXLN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_ETH_ETXLN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_ETH_ETXLN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_ETH_ETXLN` writer"]
+pub struct W(crate::W<R16_ETH_ETXLN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_ETH_ETXLN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_ETH_ETXLN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_ETH_ETXLN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_eth_etxln](index.html) module"]
+pub struct R16_ETH_ETXLN_SPEC;
+impl crate::RegisterSpec for R16_ETH_ETXLN_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_eth_etxln::R](R) reader structure"]
+impl crate::Readable for R16_ETH_ETXLN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_eth_etxln::W](W) writer structure"]
+impl crate::Writable for R16_ETH_ETXLN_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_ETH_ETXLN to value 0"]
+impl crate::Resettable for R16_ETH_ETXLN_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r16_eth_etxst.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_ETH_ETXST` reader"]
+pub struct R(crate::R<R16_ETH_ETXST_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_ETH_ETXST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_ETH_ETXST_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_ETH_ETXST_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_ETH_ETXST` writer"]
+pub struct W(crate::W<R16_ETH_ETXST_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_ETH_ETXST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_ETH_ETXST_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_ETH_ETXST_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_eth_etxst](index.html) module"]
+pub struct R16_ETH_ETXST_SPEC;
+impl crate::RegisterSpec for R16_ETH_ETXST_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_eth_etxst::R](R) reader structure"]
+impl crate::Readable for R16_ETH_ETXST_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_eth_etxst::W](W) writer structure"]
+impl crate::Writable for R16_ETH_ETXST_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_ETH_ETXST to value 0"]
+impl crate::Resettable for R16_ETH_ETXST_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r16_eth_maadrh.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_ETH_MAADRH` reader"]
+pub struct R(crate::R<R16_ETH_MAADRH_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_ETH_MAADRH_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_ETH_MAADRH_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_ETH_MAADRH_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_ETH_MAADRH` writer"]
+pub struct W(crate::W<R16_ETH_MAADRH_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_ETH_MAADRH_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_ETH_MAADRH_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_ETH_MAADRH_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_eth_maadrh](index.html) module"]
+pub struct R16_ETH_MAADRH_SPEC;
+impl crate::RegisterSpec for R16_ETH_MAADRH_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_eth_maadrh::R](R) reader structure"]
+impl crate::Readable for R16_ETH_MAADRH_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_eth_maadrh::W](W) writer structure"]
+impl crate::Writable for R16_ETH_MAADRH_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_ETH_MAADRH to value 0"]
+impl crate::Resettable for R16_ETH_MAADRH_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r16_eth_mamxfl.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_ETH_MAMXFL` reader"]
+pub struct R(crate::R<R16_ETH_MAMXFL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_ETH_MAMXFL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_ETH_MAMXFL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_ETH_MAMXFL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_ETH_MAMXFL` writer"]
+pub struct W(crate::W<R16_ETH_MAMXFL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_ETH_MAMXFL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_ETH_MAMXFL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_ETH_MAMXFL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_eth_mamxfl](index.html) module"]
+pub struct R16_ETH_MAMXFL_SPEC;
+impl crate::RegisterSpec for R16_ETH_MAMXFL_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_eth_mamxfl::R](R) reader structure"]
+impl crate::Readable for R16_ETH_MAMXFL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_eth_mamxfl::W](W) writer structure"]
+impl crate::Writable for R16_ETH_MAMXFL_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_ETH_MAMXFL to value 0"]
+impl crate::Resettable for R16_ETH_MAMXFL_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r16_eth_mird.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_ETH_MIRD` reader"]
+pub struct R(crate::R<R16_ETH_MIRD_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_ETH_MIRD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_ETH_MIRD_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_ETH_MIRD_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_ETH_MIRD` writer"]
+pub struct W(crate::W<R16_ETH_MIRD_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_ETH_MIRD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_ETH_MIRD_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_ETH_MIRD_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_eth_mird](index.html) module"]
+pub struct R16_ETH_MIRD_SPEC;
+impl crate::RegisterSpec for R16_ETH_MIRD_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_eth_mird::R](R) reader structure"]
+impl crate::Readable for R16_ETH_MIRD_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_eth_mird::W](W) writer structure"]
+impl crate::Writable for R16_ETH_MIRD_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_ETH_MIRD to value 0"]
+impl crate::Resettable for R16_ETH_MIRD_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r16_eth_miwr.rs

@@ -0,0 +1,44 @@
+#[doc = "Register `R16_ETH_MIWR` writer"]
+pub struct W(crate::W<R16_ETH_MIWR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_ETH_MIWR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_ETH_MIWR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_ETH_MIWR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_eth_miwr](index.html) module"]
+pub struct R16_ETH_MIWR_SPEC;
+impl crate::RegisterSpec for R16_ETH_MIWR_SPEC {
+    type Ux = u16;
+}
+#[doc = "`write(|w| ..)` method takes [r16_eth_miwr::W](W) writer structure"]
+impl crate::Writable for R16_ETH_MIWR_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_ETH_MIWR to value 0"]
+impl crate::Resettable for R16_ETH_MIWR_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r32_eth_maadrl.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R32_ETH_MAADRL` reader"]
+pub struct R(crate::R<R32_ETH_MAADRL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R32_ETH_MAADRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R32_ETH_MAADRL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R32_ETH_MAADRL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R32_ETH_MAADRL` writer"]
+pub struct W(crate::W<R32_ETH_MAADRL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R32_ETH_MAADRL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R32_ETH_MAADRL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R32_ETH_MAADRL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r32_eth_maadrl](index.html) module"]
+pub struct R32_ETH_MAADRL_SPEC;
+impl crate::RegisterSpec for R32_ETH_MAADRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [r32_eth_maadrl::R](R) reader structure"]
+impl crate::Readable for R32_ETH_MAADRL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r32_eth_maadrl::W](W) writer structure"]
+impl crate::Writable for R32_ETH_MAADRL_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R32_ETH_MAADRL to value 0"]
+impl crate::Resettable for R32_ETH_MAADRL_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_econ1.rs

@@ -0,0 +1,129 @@
+#[doc = "Register `R8_ETH_ECON1` reader"]
+pub struct R(crate::R<R8_ETH_ECON1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_ECON1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_ECON1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_ECON1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_ECON1` writer"]
+pub struct W(crate::W<R8_ETH_ECON1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_ECON1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_ECON1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_ECON1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_ETH_ECON1_RXEN` reader - soso"]
+pub type RB_ETH_ECON1_RXEN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ECON1_RXEN` writer - soso"]
+pub type RB_ETH_ECON1_RXEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_ECON1_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_ECON1_TXRTS` reader - soso"]
+pub type RB_ETH_ECON1_TXRTS_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ECON1_TXRTS` writer - soso"]
+pub type RB_ETH_ECON1_TXRTS_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_ECON1_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_ECON1_RXRST` reader - soso"]
+pub type RB_ETH_ECON1_RXRST_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ECON1_RXRST` writer - soso"]
+pub type RB_ETH_ECON1_RXRST_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_ECON1_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_ECON1_TXRST` reader - soso"]
+pub type RB_ETH_ECON1_TXRST_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ECON1_TXRST` writer - soso"]
+pub type RB_ETH_ECON1_TXRST_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_ECON1_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 2 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_econ1_rxen(&self) -> RB_ETH_ECON1_RXEN_R {
+        RB_ETH_ECON1_RXEN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_econ1_txrts(&self) -> RB_ETH_ECON1_TXRTS_R {
+        RB_ETH_ECON1_TXRTS_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 6 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_econ1_rxrst(&self) -> RB_ETH_ECON1_RXRST_R {
+        RB_ETH_ECON1_RXRST_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_econ1_txrst(&self) -> RB_ETH_ECON1_TXRST_R {
+        RB_ETH_ECON1_TXRST_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 2 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_econ1_rxen(&mut self) -> RB_ETH_ECON1_RXEN_W<2> {
+        RB_ETH_ECON1_RXEN_W::new(self)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_econ1_txrts(&mut self) -> RB_ETH_ECON1_TXRTS_W<3> {
+        RB_ETH_ECON1_TXRTS_W::new(self)
+    }
+    #[doc = "Bit 6 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_econ1_rxrst(&mut self) -> RB_ETH_ECON1_RXRST_W<6> {
+        RB_ETH_ECON1_RXRST_W::new(self)
+    }
+    #[doc = "Bit 7 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_econ1_txrst(&mut self) -> RB_ETH_ECON1_TXRST_W<7> {
+        RB_ETH_ECON1_TXRST_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_econ1](index.html) module"]
+pub struct R8_ETH_ECON1_SPEC;
+impl crate::RegisterSpec for R8_ETH_ECON1_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_econ1::R](R) reader structure"]
+impl crate::Readable for R8_ETH_ECON1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_econ1::W](W) writer structure"]
+impl crate::Writable for R8_ETH_ECON1_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_ECON1 to value 0"]
+impl crate::Resettable for R8_ETH_ECON1_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_econ2.rs

@@ -0,0 +1,96 @@
+#[doc = "Register `R8_ETH_ECON2` reader"]
+pub struct R(crate::R<R8_ETH_ECON2_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_ECON2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_ECON2_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_ECON2_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_ECON2` writer"]
+pub struct W(crate::W<R8_ETH_ECON2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_ECON2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_ECON2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_ECON2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_ETH_ECON2_TX` reader - soso"]
+pub type RB_ETH_ECON2_TX_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ECON2_TX` writer - soso"]
+pub type RB_ETH_ECON2_TX_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_ECON2_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_ECON2_RX` reader - soso"]
+pub type RB_ETH_ECON2_RX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_ETH_ECON2_RX` writer - soso"]
+pub type RB_ETH_ECON2_RX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u8, R8_ETH_ECON2_SPEC, u8, u8, 3, O>;
+impl R {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_econ2_tx(&self) -> RB_ETH_ECON2_TX_R {
+        RB_ETH_ECON2_TX_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 1:3 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_econ2_rx(&self) -> RB_ETH_ECON2_RX_R {
+        RB_ETH_ECON2_RX_R::new((self.bits >> 1) & 7)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_econ2_tx(&mut self) -> RB_ETH_ECON2_TX_W<0> {
+        RB_ETH_ECON2_TX_W::new(self)
+    }
+    #[doc = "Bits 1:3 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_econ2_rx(&mut self) -> RB_ETH_ECON2_RX_W<1> {
+        RB_ETH_ECON2_RX_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_econ2](index.html) module"]
+pub struct R8_ETH_ECON2_SPEC;
+impl crate::RegisterSpec for R8_ETH_ECON2_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_econ2::R](R) reader structure"]
+impl crate::Readable for R8_ETH_ECON2_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_econ2::W](W) writer structure"]
+impl crate::Writable for R8_ETH_ECON2_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_ECON2 to value 0"]
+impl crate::Resettable for R8_ETH_ECON2_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_eht0.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_ETH_EHT0` reader"]
+pub struct R(crate::R<R8_ETH_EHT0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_EHT0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_EHT0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_EHT0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_EHT0` writer"]
+pub struct W(crate::W<R8_ETH_EHT0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_EHT0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_EHT0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_EHT0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_eht0](index.html) module"]
+pub struct R8_ETH_EHT0_SPEC;
+impl crate::RegisterSpec for R8_ETH_EHT0_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_eht0::R](R) reader structure"]
+impl crate::Readable for R8_ETH_EHT0_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_eht0::W](W) writer structure"]
+impl crate::Writable for R8_ETH_EHT0_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_EHT0 to value 0"]
+impl crate::Resettable for R8_ETH_EHT0_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_eht1.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_ETH_EHT1` reader"]
+pub struct R(crate::R<R8_ETH_EHT1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_EHT1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_EHT1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_EHT1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_EHT1` writer"]
+pub struct W(crate::W<R8_ETH_EHT1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_EHT1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_EHT1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_EHT1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_eht1](index.html) module"]
+pub struct R8_ETH_EHT1_SPEC;
+impl crate::RegisterSpec for R8_ETH_EHT1_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_eht1::R](R) reader structure"]
+impl crate::Readable for R8_ETH_EHT1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_eht1::W](W) writer structure"]
+impl crate::Writable for R8_ETH_EHT1_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_EHT1 to value 0"]
+impl crate::Resettable for R8_ETH_EHT1_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_eht2.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_ETH_EHT2` reader"]
+pub struct R(crate::R<R8_ETH_EHT2_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_EHT2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_EHT2_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_EHT2_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_EHT2` writer"]
+pub struct W(crate::W<R8_ETH_EHT2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_EHT2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_EHT2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_EHT2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_eht2](index.html) module"]
+pub struct R8_ETH_EHT2_SPEC;
+impl crate::RegisterSpec for R8_ETH_EHT2_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_eht2::R](R) reader structure"]
+impl crate::Readable for R8_ETH_EHT2_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_eht2::W](W) writer structure"]
+impl crate::Writable for R8_ETH_EHT2_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_EHT2 to value 0"]
+impl crate::Resettable for R8_ETH_EHT2_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_eht3.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_ETH_EHT3` reader"]
+pub struct R(crate::R<R8_ETH_EHT3_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_EHT3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_EHT3_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_EHT3_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_EHT3` writer"]
+pub struct W(crate::W<R8_ETH_EHT3_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_EHT3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_EHT3_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_EHT3_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_eht3](index.html) module"]
+pub struct R8_ETH_EHT3_SPEC;
+impl crate::RegisterSpec for R8_ETH_EHT3_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_eht3::R](R) reader structure"]
+impl crate::Readable for R8_ETH_EHT3_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_eht3::W](W) writer structure"]
+impl crate::Writable for R8_ETH_EHT3_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_EHT3 to value 0"]
+impl crate::Resettable for R8_ETH_EHT3_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_eht4.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_ETH_EHT4` reader"]
+pub struct R(crate::R<R8_ETH_EHT4_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_EHT4_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_EHT4_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_EHT4_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_EHT4` writer"]
+pub struct W(crate::W<R8_ETH_EHT4_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_EHT4_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_EHT4_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_EHT4_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_eht4](index.html) module"]
+pub struct R8_ETH_EHT4_SPEC;
+impl crate::RegisterSpec for R8_ETH_EHT4_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_eht4::R](R) reader structure"]
+impl crate::Readable for R8_ETH_EHT4_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_eht4::W](W) writer structure"]
+impl crate::Writable for R8_ETH_EHT4_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_EHT4 to value 0"]
+impl crate::Resettable for R8_ETH_EHT4_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_eht5.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_ETH_EHT5` reader"]
+pub struct R(crate::R<R8_ETH_EHT5_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_EHT5_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_EHT5_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_EHT5_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_EHT5` writer"]
+pub struct W(crate::W<R8_ETH_EHT5_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_EHT5_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_EHT5_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_EHT5_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_eht5](index.html) module"]
+pub struct R8_ETH_EHT5_SPEC;
+impl crate::RegisterSpec for R8_ETH_EHT5_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_eht5::R](R) reader structure"]
+impl crate::Readable for R8_ETH_EHT5_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_eht5::W](W) writer structure"]
+impl crate::Writable for R8_ETH_EHT5_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_EHT5 to value 0"]
+impl crate::Resettable for R8_ETH_EHT5_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_eht6.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_ETH_EHT6` reader"]
+pub struct R(crate::R<R8_ETH_EHT6_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_EHT6_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_EHT6_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_EHT6_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_EHT6` writer"]
+pub struct W(crate::W<R8_ETH_EHT6_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_EHT6_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_EHT6_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_EHT6_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_eht6](index.html) module"]
+pub struct R8_ETH_EHT6_SPEC;
+impl crate::RegisterSpec for R8_ETH_EHT6_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_eht6::R](R) reader structure"]
+impl crate::Readable for R8_ETH_EHT6_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_eht6::W](W) writer structure"]
+impl crate::Writable for R8_ETH_EHT6_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_EHT6 to value 0"]
+impl crate::Resettable for R8_ETH_EHT6_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_eht7.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_ETH_EHT7` reader"]
+pub struct R(crate::R<R8_ETH_EHT7_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_EHT7_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_EHT7_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_EHT7_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_EHT7` writer"]
+pub struct W(crate::W<R8_ETH_EHT7_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_EHT7_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_EHT7_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_EHT7_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_eht7](index.html) module"]
+pub struct R8_ETH_EHT7_SPEC;
+impl crate::RegisterSpec for R8_ETH_EHT7_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_eht7::R](R) reader structure"]
+impl crate::Readable for R8_ETH_EHT7_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_eht7::W](W) writer structure"]
+impl crate::Writable for R8_ETH_EHT7_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_EHT7 to value 0"]
+impl crate::Resettable for R8_ETH_EHT7_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_eie.rs

@@ -0,0 +1,170 @@
+#[doc = "Register `R8_ETH_EIE` reader"]
+pub struct R(crate::R<R8_ETH_EIE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_EIE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_EIE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_EIE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_EIE` writer"]
+pub struct W(crate::W<R8_ETH_EIE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_EIE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_EIE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_EIE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_ETH_EIE_RXERIE` reader - soso"]
+pub type RB_ETH_EIE_RXERIE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIE_RXERIE` writer - soso"]
+pub type RB_ETH_EIE_RXERIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIE_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_EIE_TXERIE` reader - soso"]
+pub type RB_ETH_EIE_TXERIE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIE_TXERIE` writer - soso"]
+pub type RB_ETH_EIE_TXERIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIE_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_EIE_R_EN50` reader - soso"]
+pub type RB_ETH_EIE_R_EN50_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIE_R_EN50` writer - soso"]
+pub type RB_ETH_EIE_R_EN50_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIE_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_EIE_TXIE` reader - soso"]
+pub type RB_ETH_EIE_TXIE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIE_TXIE` writer - soso"]
+pub type RB_ETH_EIE_TXIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIE_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_EIE_LINKIE` reader - soso"]
+pub type RB_ETH_EIE_LINKIE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIE_LINKIE` writer - soso"]
+pub type RB_ETH_EIE_LINKIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIE_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_EIE_RXIE` reader - soso"]
+pub type RB_ETH_EIE_RXIE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIE_RXIE` writer - soso"]
+pub type RB_ETH_EIE_RXIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIE_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_EIE_INTIE` reader - soso"]
+pub type RB_ETH_EIE_INTIE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIE_INTIE` writer - soso"]
+pub type RB_ETH_EIE_INTIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIE_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eie_rxerie(&self) -> RB_ETH_EIE_RXERIE_R {
+        RB_ETH_EIE_RXERIE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eie_txerie(&self) -> RB_ETH_EIE_TXERIE_R {
+        RB_ETH_EIE_TXERIE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eie_r_en50(&self) -> RB_ETH_EIE_R_EN50_R {
+        RB_ETH_EIE_R_EN50_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eie_txie(&self) -> RB_ETH_EIE_TXIE_R {
+        RB_ETH_EIE_TXIE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eie_linkie(&self) -> RB_ETH_EIE_LINKIE_R {
+        RB_ETH_EIE_LINKIE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 6 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eie_rxie(&self) -> RB_ETH_EIE_RXIE_R {
+        RB_ETH_EIE_RXIE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eie_intie(&self) -> RB_ETH_EIE_INTIE_R {
+        RB_ETH_EIE_INTIE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eie_rxerie(&mut self) -> RB_ETH_EIE_RXERIE_W<0> {
+        RB_ETH_EIE_RXERIE_W::new(self)
+    }
+    #[doc = "Bit 1 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eie_txerie(&mut self) -> RB_ETH_EIE_TXERIE_W<1> {
+        RB_ETH_EIE_TXERIE_W::new(self)
+    }
+    #[doc = "Bit 2 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eie_r_en50(&mut self) -> RB_ETH_EIE_R_EN50_W<2> {
+        RB_ETH_EIE_R_EN50_W::new(self)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eie_txie(&mut self) -> RB_ETH_EIE_TXIE_W<3> {
+        RB_ETH_EIE_TXIE_W::new(self)
+    }
+    #[doc = "Bit 4 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eie_linkie(&mut self) -> RB_ETH_EIE_LINKIE_W<4> {
+        RB_ETH_EIE_LINKIE_W::new(self)
+    }
+    #[doc = "Bit 6 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eie_rxie(&mut self) -> RB_ETH_EIE_RXIE_W<6> {
+        RB_ETH_EIE_RXIE_W::new(self)
+    }
+    #[doc = "Bit 7 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eie_intie(&mut self) -> RB_ETH_EIE_INTIE_W<7> {
+        RB_ETH_EIE_INTIE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_eie](index.html) module"]
+pub struct R8_ETH_EIE_SPEC;
+impl crate::RegisterSpec for R8_ETH_EIE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_eie::R](R) reader structure"]
+impl crate::Readable for R8_ETH_EIE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_eie::W](W) writer structure"]
+impl crate::Writable for R8_ETH_EIE_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_EIE to value 0"]
+impl crate::Resettable for R8_ETH_EIE_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_eir.rs

@@ -0,0 +1,140 @@
+#[doc = "Register `R8_ETH_EIR` reader"]
+pub struct R(crate::R<R8_ETH_EIR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_EIR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_EIR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_EIR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_EIR` writer"]
+pub struct W(crate::W<R8_ETH_EIR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_EIR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_EIR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_EIR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_ETH_EIR_RXERIF` reader - soso"]
+pub type RB_ETH_EIR_RXERIF_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIR_RXERIF` writer - soso"]
+pub type RB_ETH_EIR_RXERIF_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIR_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_EIR_TXERIF` reader - soso"]
+pub type RB_ETH_EIR_TXERIF_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIR_TXERIF` writer - soso"]
+pub type RB_ETH_EIR_TXERIF_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIR_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_EIR_TXIF` reader - soso"]
+pub type RB_ETH_EIR_TXIF_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIR_TXIF` writer - soso"]
+pub type RB_ETH_EIR_TXIF_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIR_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_EIR_LINKIF` reader - soso"]
+pub type RB_ETH_EIR_LINKIF_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIR_LINKIF` writer - soso"]
+pub type RB_ETH_EIR_LINKIF_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIR_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_EIR_RXIF` reader - soso"]
+pub type RB_ETH_EIR_RXIF_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_EIR_RXIF` writer - soso"]
+pub type RB_ETH_EIR_RXIF_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_ETH_EIR_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eir_rxerif(&self) -> RB_ETH_EIR_RXERIF_R {
+        RB_ETH_EIR_RXERIF_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eir_txerif(&self) -> RB_ETH_EIR_TXERIF_R {
+        RB_ETH_EIR_TXERIF_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eir_txif(&self) -> RB_ETH_EIR_TXIF_R {
+        RB_ETH_EIR_TXIF_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eir_linkif(&self) -> RB_ETH_EIR_LINKIF_R {
+        RB_ETH_EIR_LINKIF_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 6 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_eir_rxif(&self) -> RB_ETH_EIR_RXIF_R {
+        RB_ETH_EIR_RXIF_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eir_rxerif(&mut self) -> RB_ETH_EIR_RXERIF_W<0> {
+        RB_ETH_EIR_RXERIF_W::new(self)
+    }
+    #[doc = "Bit 1 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eir_txerif(&mut self) -> RB_ETH_EIR_TXERIF_W<1> {
+        RB_ETH_EIR_TXERIF_W::new(self)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eir_txif(&mut self) -> RB_ETH_EIR_TXIF_W<3> {
+        RB_ETH_EIR_TXIF_W::new(self)
+    }
+    #[doc = "Bit 4 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eir_linkif(&mut self) -> RB_ETH_EIR_LINKIF_W<4> {
+        RB_ETH_EIR_LINKIF_W::new(self)
+    }
+    #[doc = "Bit 6 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_eir_rxif(&mut self) -> RB_ETH_EIR_RXIF_W<6> {
+        RB_ETH_EIR_RXIF_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_eir](index.html) module"]
+pub struct R8_ETH_EIR_SPEC;
+impl crate::RegisterSpec for R8_ETH_EIR_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_eir::R](R) reader structure"]
+impl crate::Readable for R8_ETH_EIR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_eir::W](W) writer structure"]
+impl crate::Writable for R8_ETH_EIR_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_EIR to value 0"]
+impl crate::Resettable for R8_ETH_EIR_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_erxfcon.rs

@@ -0,0 +1,177 @@
+#[doc = "Register `R8_ETH_ERXFCON` reader"]
+pub struct R(crate::R<R8_ETH_ERXFCON_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_ERXFCON_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_ERXFCON_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_ERXFCON_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_ERXFCON` writer"]
+pub struct W(crate::W<R8_ETH_ERXFCON_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_ERXFCON_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_ERXFCON_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_ERXFCON_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_ETH_ERXFCON_BCEN` reader - soso"]
+pub type RB_ETH_ERXFCON_BCEN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ERXFCON_BCEN` writer - soso"]
+pub type RB_ETH_ERXFCON_BCEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_ERXFCON_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_ERXFCON_MCEN` reader - soso"]
+pub type RB_ETH_ERXFCON_MCEN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ERXFCON_MCEN` writer - soso"]
+pub type RB_ETH_ERXFCON_MCEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_ERXFCON_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_ERXFCON_HTEN` reader - soso"]
+pub type RB_ETH_ERXFCON_HTEN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ERXFCON_HTEN` writer - soso"]
+pub type RB_ETH_ERXFCON_HTEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_ERXFCON_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_ERXFCON_MPEN` reader - soso"]
+pub type RB_ETH_ERXFCON_MPEN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ERXFCON_MPEN` writer - soso"]
+pub type RB_ETH_ERXFCON_MPEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_ERXFCON_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_ERXFCON_CRCEN` reader - soso"]
+pub type RB_ETH_ERXFCON_CRCEN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ERXFCON_CRCEN` writer - soso"]
+pub type RB_ETH_ERXFCON_CRCEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_ERXFCON_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_ERXFCON_ANDOR` reader - soso"]
+pub type RB_ETH_ERXFCON_ANDOR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ERXFCON_ANDOR` writer - soso"]
+pub type RB_ETH_ERXFCON_ANDOR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_ERXFCON_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_ERXFCON_UCEN` reader - soso"]
+pub type RB_ETH_ERXFCON_UCEN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ERXFCON_UCEN` writer - soso"]
+pub type RB_ETH_ERXFCON_UCEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_ERXFCON_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_erxfcon_bcen(&self) -> RB_ETH_ERXFCON_BCEN_R {
+        RB_ETH_ERXFCON_BCEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_erxfcon_mcen(&self) -> RB_ETH_ERXFCON_MCEN_R {
+        RB_ETH_ERXFCON_MCEN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_erxfcon_hten(&self) -> RB_ETH_ERXFCON_HTEN_R {
+        RB_ETH_ERXFCON_HTEN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_erxfcon_mpen(&self) -> RB_ETH_ERXFCON_MPEN_R {
+        RB_ETH_ERXFCON_MPEN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 5 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_erxfcon_crcen(&self) -> RB_ETH_ERXFCON_CRCEN_R {
+        RB_ETH_ERXFCON_CRCEN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_erxfcon_andor(&self) -> RB_ETH_ERXFCON_ANDOR_R {
+        RB_ETH_ERXFCON_ANDOR_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_erxfcon_ucen(&self) -> RB_ETH_ERXFCON_UCEN_R {
+        RB_ETH_ERXFCON_UCEN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_erxfcon_bcen(&mut self) -> RB_ETH_ERXFCON_BCEN_W<0> {
+        RB_ETH_ERXFCON_BCEN_W::new(self)
+    }
+    #[doc = "Bit 1 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_erxfcon_mcen(&mut self) -> RB_ETH_ERXFCON_MCEN_W<1> {
+        RB_ETH_ERXFCON_MCEN_W::new(self)
+    }
+    #[doc = "Bit 2 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_erxfcon_hten(&mut self) -> RB_ETH_ERXFCON_HTEN_W<2> {
+        RB_ETH_ERXFCON_HTEN_W::new(self)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_erxfcon_mpen(&mut self) -> RB_ETH_ERXFCON_MPEN_W<3> {
+        RB_ETH_ERXFCON_MPEN_W::new(self)
+    }
+    #[doc = "Bit 5 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_erxfcon_crcen(&mut self) -> RB_ETH_ERXFCON_CRCEN_W<5> {
+        RB_ETH_ERXFCON_CRCEN_W::new(self)
+    }
+    #[doc = "Bit 6 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_erxfcon_andor(&mut self) -> RB_ETH_ERXFCON_ANDOR_W<6> {
+        RB_ETH_ERXFCON_ANDOR_W::new(self)
+    }
+    #[doc = "Bit 7 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_erxfcon_ucen(&mut self) -> RB_ETH_ERXFCON_UCEN_W<7> {
+        RB_ETH_ERXFCON_UCEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_erxfcon](index.html) module"]
+pub struct R8_ETH_ERXFCON_SPEC;
+impl crate::RegisterSpec for R8_ETH_ERXFCON_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_erxfcon::R](R) reader structure"]
+impl crate::Readable for R8_ETH_ERXFCON_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_erxfcon::W](W) writer structure"]
+impl crate::Writable for R8_ETH_ERXFCON_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_ERXFCON to value 0"]
+impl crate::Resettable for R8_ETH_ERXFCON_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_estat.rs

@@ -0,0 +1,79 @@
+#[doc = "Register `R8_ETH_ESTAT` reader"]
+pub struct R(crate::R<R8_ETH_ESTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_ESTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_ESTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_ESTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `RB_ETH_ESTAT_TXABRT` reader - soso"]
+pub type RB_ETH_ESTAT_TXABRT_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ESTAT_RXBUSY` reader - soso"]
+pub type RB_ETH_ESTAT_RXBUSY_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ESTAT_RXMORE` reader - soso"]
+pub type RB_ETH_ESTAT_RXMORE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ESTAT_RXNIBBLE` reader - soso"]
+pub type RB_ETH_ESTAT_RXNIBBLE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ESTAT_RXCRCER` reader - soso"]
+pub type RB_ETH_ESTAT_RXCRCER_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ESTAT_BUFER` reader - soso"]
+pub type RB_ETH_ESTAT_BUFER_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_ESTAT_INT` reader - soso"]
+pub type RB_ETH_ESTAT_INT_R = crate::BitReader<bool>;
+impl R {
+    #[doc = "Bit 1 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_estat_txabrt(&self) -> RB_ETH_ESTAT_TXABRT_R {
+        RB_ETH_ESTAT_TXABRT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_estat_rxbusy(&self) -> RB_ETH_ESTAT_RXBUSY_R {
+        RB_ETH_ESTAT_RXBUSY_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_estat_rxmore(&self) -> RB_ETH_ESTAT_RXMORE_R {
+        RB_ETH_ESTAT_RXMORE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_estat_rxnibble(&self) -> RB_ETH_ESTAT_RXNIBBLE_R {
+        RB_ETH_ESTAT_RXNIBBLE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_estat_rxcrcer(&self) -> RB_ETH_ESTAT_RXCRCER_R {
+        RB_ETH_ESTAT_RXCRCER_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_estat_bufer(&self) -> RB_ETH_ESTAT_BUFER_R {
+        RB_ETH_ESTAT_BUFER_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_estat_int(&self) -> RB_ETH_ESTAT_INT_R {
+        RB_ETH_ESTAT_INT_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_estat](index.html) module"]
+pub struct R8_ETH_ESTAT_SPEC;
+impl crate::RegisterSpec for R8_ETH_ESTAT_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_estat::R](R) reader structure"]
+impl crate::Readable for R8_ETH_ESTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets R8_ETH_ESTAT to value 0"]
+impl crate::Resettable for R8_ETH_ESTAT_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_mabbipg.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `R8_ETH_MABBIPG` reader"]
+pub struct R(crate::R<R8_ETH_MABBIPG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_MABBIPG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_MABBIPG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_MABBIPG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_MABBIPG` writer"]
+pub struct W(crate::W<R8_ETH_MABBIPG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_MABBIPG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_MABBIPG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_MABBIPG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_ETH_MABBIPG_MABBIPG` reader - soso"]
+pub type RB_ETH_MABBIPG_MABBIPG_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_ETH_MABBIPG_MABBIPG` writer - soso"]
+pub type RB_ETH_MABBIPG_MABBIPG_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u8, R8_ETH_MABBIPG_SPEC, u8, u8, 7, O>;
+impl R {
+    #[doc = "Bits 0:6 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_mabbipg_mabbipg(&self) -> RB_ETH_MABBIPG_MABBIPG_R {
+        RB_ETH_MABBIPG_MABBIPG_R::new(self.bits & 0x7f)
+    }
+}
+impl W {
+    #[doc = "Bits 0:6 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_mabbipg_mabbipg(&mut self) -> RB_ETH_MABBIPG_MABBIPG_W<0> {
+        RB_ETH_MABBIPG_MABBIPG_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_mabbipg](index.html) module"]
+pub struct R8_ETH_MABBIPG_SPEC;
+impl crate::RegisterSpec for R8_ETH_MABBIPG_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_mabbipg::R](R) reader structure"]
+impl crate::Readable for R8_ETH_MABBIPG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_mabbipg::W](W) writer structure"]
+impl crate::Writable for R8_ETH_MABBIPG_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_MABBIPG to value 0"]
+impl crate::Resettable for R8_ETH_MABBIPG_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_macon1.rs

@@ -0,0 +1,145 @@
+#[doc = "Register `R8_ETH_MACON1` reader"]
+pub struct R(crate::R<R8_ETH_MACON1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_MACON1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_MACON1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_MACON1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_MACON1` writer"]
+pub struct W(crate::W<R8_ETH_MACON1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_MACON1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_MACON1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_MACON1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_ETH_MACON1_MARXEN` reader - soso"]
+pub type RB_ETH_MACON1_MARXEN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_MACON1_MARXEN` writer - soso"]
+pub type RB_ETH_MACON1_MARXEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_MACON1_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_MACON1_PASSALL` reader - soso"]
+pub type RB_ETH_MACON1_PASSALL_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_MACON1_PASSALL` writer - soso"]
+pub type RB_ETH_MACON1_PASSALL_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_MACON1_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_MACON1_RXPAUS` reader - soso"]
+pub type RB_ETH_MACON1_RXPAUS_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_MACON1_RXPAUS` writer - soso"]
+pub type RB_ETH_MACON1_RXPAUS_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_MACON1_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_MACON1_TXPAUS` reader - soso"]
+pub type RB_ETH_MACON1_TXPAUS_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_MACON1_TXPAUS` writer - soso"]
+pub type RB_ETH_MACON1_TXPAUS_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_MACON1_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_MACON1_FCEN` reader - soso"]
+pub type RB_ETH_MACON1_FCEN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_ETH_MACON1_FCEN` writer - soso"]
+pub type RB_ETH_MACON1_FCEN_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u8, R8_ETH_MACON1_SPEC, u8, u8, 2, O>;
+impl R {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_macon1_marxen(&self) -> RB_ETH_MACON1_MARXEN_R {
+        RB_ETH_MACON1_MARXEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_macon1_passall(&self) -> RB_ETH_MACON1_PASSALL_R {
+        RB_ETH_MACON1_PASSALL_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_macon1_rxpaus(&self) -> RB_ETH_MACON1_RXPAUS_R {
+        RB_ETH_MACON1_RXPAUS_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_macon1_txpaus(&self) -> RB_ETH_MACON1_TXPAUS_R {
+        RB_ETH_MACON1_TXPAUS_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bits 4:5 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_macon1_fcen(&self) -> RB_ETH_MACON1_FCEN_R {
+        RB_ETH_MACON1_FCEN_R::new((self.bits >> 4) & 3)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_macon1_marxen(&mut self) -> RB_ETH_MACON1_MARXEN_W<0> {
+        RB_ETH_MACON1_MARXEN_W::new(self)
+    }
+    #[doc = "Bit 1 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_macon1_passall(&mut self) -> RB_ETH_MACON1_PASSALL_W<1> {
+        RB_ETH_MACON1_PASSALL_W::new(self)
+    }
+    #[doc = "Bit 2 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_macon1_rxpaus(&mut self) -> RB_ETH_MACON1_RXPAUS_W<2> {
+        RB_ETH_MACON1_RXPAUS_W::new(self)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_macon1_txpaus(&mut self) -> RB_ETH_MACON1_TXPAUS_W<3> {
+        RB_ETH_MACON1_TXPAUS_W::new(self)
+    }
+    #[doc = "Bits 4:5 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_macon1_fcen(&mut self) -> RB_ETH_MACON1_FCEN_W<4> {
+        RB_ETH_MACON1_FCEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_macon1](index.html) module"]
+pub struct R8_ETH_MACON1_SPEC;
+impl crate::RegisterSpec for R8_ETH_MACON1_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_macon1::R](R) reader structure"]
+impl crate::Readable for R8_ETH_MACON1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_macon1::W](W) writer structure"]
+impl crate::Writable for R8_ETH_MACON1_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_MACON1 to value 0"]
+impl crate::Resettable for R8_ETH_MACON1_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_macon2.rs

@@ -0,0 +1,145 @@
+#[doc = "Register `R8_ETH_MACON2` reader"]
+pub struct R(crate::R<R8_ETH_MACON2_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_MACON2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_MACON2_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_MACON2_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_MACON2` writer"]
+pub struct W(crate::W<R8_ETH_MACON2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_MACON2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_MACON2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_MACON2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_ETH_MACON2_FULDPX` reader - soso"]
+pub type RB_ETH_MACON2_FULDPX_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_MACON2_FULDPX` writer - soso"]
+pub type RB_ETH_MACON2_FULDPX_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_MACON2_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_MACON2_HFRMEN` reader - soso"]
+pub type RB_ETH_MACON2_HFRMEN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_MACON2_HFRMEN` writer - soso"]
+pub type RB_ETH_MACON2_HFRMEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_MACON2_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_MACON2_PHDREN` reader - soso"]
+pub type RB_ETH_MACON2_PHDREN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_MACON2_PHDREN` writer - soso"]
+pub type RB_ETH_MACON2_PHDREN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_MACON2_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_MACON2_TXCRCEN` reader - soso"]
+pub type RB_ETH_MACON2_TXCRCEN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ETH_MACON2_TXCRCEN` writer - soso"]
+pub type RB_ETH_MACON2_TXCRCEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_ETH_MACON2_SPEC, bool, O>;
+#[doc = "Field `RB_ETH_MACON2_PADCFG` reader - soso"]
+pub type RB_ETH_MACON2_PADCFG_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_ETH_MACON2_PADCFG` writer - soso"]
+pub type RB_ETH_MACON2_PADCFG_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u8, R8_ETH_MACON2_SPEC, u8, u8, 3, O>;
+impl R {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_macon2_fuldpx(&self) -> RB_ETH_MACON2_FULDPX_R {
+        RB_ETH_MACON2_FULDPX_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 2 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_macon2_hfrmen(&self) -> RB_ETH_MACON2_HFRMEN_R {
+        RB_ETH_MACON2_HFRMEN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_macon2_phdren(&self) -> RB_ETH_MACON2_PHDREN_R {
+        RB_ETH_MACON2_PHDREN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_macon2_txcrcen(&self) -> RB_ETH_MACON2_TXCRCEN_R {
+        RB_ETH_MACON2_TXCRCEN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bits 5:7 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_macon2_padcfg(&self) -> RB_ETH_MACON2_PADCFG_R {
+        RB_ETH_MACON2_PADCFG_R::new((self.bits >> 5) & 7)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_macon2_fuldpx(&mut self) -> RB_ETH_MACON2_FULDPX_W<0> {
+        RB_ETH_MACON2_FULDPX_W::new(self)
+    }
+    #[doc = "Bit 2 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_macon2_hfrmen(&mut self) -> RB_ETH_MACON2_HFRMEN_W<2> {
+        RB_ETH_MACON2_HFRMEN_W::new(self)
+    }
+    #[doc = "Bit 3 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_macon2_phdren(&mut self) -> RB_ETH_MACON2_PHDREN_W<3> {
+        RB_ETH_MACON2_PHDREN_W::new(self)
+    }
+    #[doc = "Bit 4 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_macon2_txcrcen(&mut self) -> RB_ETH_MACON2_TXCRCEN_W<4> {
+        RB_ETH_MACON2_TXCRCEN_W::new(self)
+    }
+    #[doc = "Bits 5:7 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_macon2_padcfg(&mut self) -> RB_ETH_MACON2_PADCFG_W<5> {
+        RB_ETH_MACON2_PADCFG_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_macon2](index.html) module"]
+pub struct R8_ETH_MACON2_SPEC;
+impl crate::RegisterSpec for R8_ETH_MACON2_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_macon2::R](R) reader structure"]
+impl crate::Readable for R8_ETH_MACON2_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_macon2::W](W) writer structure"]
+impl crate::Writable for R8_ETH_MACON2_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_MACON2 to value 0"]
+impl crate::Resettable for R8_ETH_MACON2_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_miregadr.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `R8_ETH_MIREGADR` reader"]
+pub struct R(crate::R<R8_ETH_MIREGADR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_MIREGADR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_MIREGADR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_MIREGADR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_ETH_MIREGADR` writer"]
+pub struct W(crate::W<R8_ETH_MIREGADR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_ETH_MIREGADR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_ETH_MIREGADR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_ETH_MIREGADR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_ETH_MIREGADR_MASK` reader - soso"]
+pub type RB_ETH_MIREGADR_MASK_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_ETH_MIREGADR_MASK` writer - soso"]
+pub type RB_ETH_MIREGADR_MASK_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u8, R8_ETH_MIREGADR_SPEC, u8, u8, 5, O>;
+impl R {
+    #[doc = "Bits 0:4 - soso"]
+    #[inline(always)]
+    pub fn rb_eth_miregadr_mask(&self) -> RB_ETH_MIREGADR_MASK_R {
+        RB_ETH_MIREGADR_MASK_R::new(self.bits & 0x1f)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - soso"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_eth_miregadr_mask(&mut self) -> RB_ETH_MIREGADR_MASK_W<0> {
+        RB_ETH_MIREGADR_MASK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_miregadr](index.html) module"]
+pub struct R8_ETH_MIREGADR_SPEC;
+impl crate::RegisterSpec for R8_ETH_MIREGADR_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_miregadr::R](R) reader structure"]
+impl crate::Readable for R8_ETH_MIREGADR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_eth_miregadr::W](W) writer structure"]
+impl crate::Writable for R8_ETH_MIREGADR_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_ETH_MIREGADR to value 0"]
+impl crate::Resettable for R8_ETH_MIREGADR_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/eth/r8_eth_mistat.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `R8_ETH_MISTAT` reader"]
+pub struct R(crate::R<R8_ETH_MISTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_ETH_MISTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_ETH_MISTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_ETH_MISTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "soso\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_eth_mistat](index.html) module"]
+pub struct R8_ETH_MISTAT_SPEC;
+impl crate::RegisterSpec for R8_ETH_MISTAT_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_eth_mistat::R](R) reader structure"]
+impl crate::Readable for R8_ETH_MISTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets R8_ETH_MISTAT to value 0"]
+impl crate::Resettable for R8_ETH_MISTAT_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/flash.rs

@@ -0,0 +1,34 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - RW, Flash ROM data"]
+    pub r32_flash_data: R32_FLASH_DATA,
+    #[doc = "0x04 - RW, Flash ROM address"]
+    pub r32_flash_addr: R32_FLASH_ADDR,
+    #[doc = "0x08 - WO, Flash ROM operation command"]
+    pub r8_flash_command: R8_FLASH_COMMAND,
+    #[doc = "0x09 - RW, Flash ROM protect control"]
+    pub r8_flash_protect: R8_FLASH_PROTECT,
+    #[doc = "0x0a - RO, Flash ROM operation status"]
+    pub r16_flash_status: R16_FLASH_STATUS,
+}
+#[doc = "R32_FLASH_DATA (rw) register accessor: an alias for `Reg<R32_FLASH_DATA_SPEC>`"]
+pub type R32_FLASH_DATA = crate::Reg<r32_flash_data::R32_FLASH_DATA_SPEC>;
+#[doc = "RW, Flash ROM data"]
+pub mod r32_flash_data;
+#[doc = "R32_FLASH_ADDR (rw) register accessor: an alias for `Reg<R32_FLASH_ADDR_SPEC>`"]
+pub type R32_FLASH_ADDR = crate::Reg<r32_flash_addr::R32_FLASH_ADDR_SPEC>;
+#[doc = "RW, Flash ROM address"]
+pub mod r32_flash_addr;
+#[doc = "R8_FLASH_COMMAND (w) register accessor: an alias for `Reg<R8_FLASH_COMMAND_SPEC>`"]
+pub type R8_FLASH_COMMAND = crate::Reg<r8_flash_command::R8_FLASH_COMMAND_SPEC>;
+#[doc = "WO, Flash ROM operation command"]
+pub mod r8_flash_command;
+#[doc = "R8_FLASH_PROTECT (rw) register accessor: an alias for `Reg<R8_FLASH_PROTECT_SPEC>`"]
+pub type R8_FLASH_PROTECT = crate::Reg<r8_flash_protect::R8_FLASH_PROTECT_SPEC>;
+#[doc = "RW, Flash ROM protect control"]
+pub mod r8_flash_protect;
+#[doc = "R16_FLASH_STATUS (r) register accessor: an alias for `Reg<R16_FLASH_STATUS_SPEC>`"]
+pub type R16_FLASH_STATUS = crate::Reg<r16_flash_status::R16_FLASH_STATUS_SPEC>;
+#[doc = "RO, Flash ROM operation status"]
+pub mod r16_flash_status;

src/flash/r16_flash_status.rs

@@ -0,0 +1,58 @@
+#[doc = "Register `R16_FLASH_STATUS` reader"]
+pub struct R(crate::R<R16_FLASH_STATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_FLASH_STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_FLASH_STATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_FLASH_STATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `RB_ROM_CMD_TOUT` reader - RO, Flash ROM operation result: 0=success, 1=operation time out"]
+pub type RB_ROM_CMD_TOUT_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ROM_CMD_ERR` reader - RO, Flash ROM operation command error flag: 0=command accepted, 1=unknown command"]
+pub type RB_ROM_CMD_ERR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ROM_ADDR_OK` reader - RO, Flash ROM erase/write operation address valid flag, can be reviewed before or after operation: 0=invalid parameter, 1=address valid"]
+pub type RB_ROM_ADDR_OK_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ROM_READ_FREE` reader - RO, indicate protected status of Flash ROM code and data: 0=reading protect, 1=enable read by external programmer"]
+pub type RB_ROM_READ_FREE_R = crate::BitReader<bool>;
+impl R {
+    #[doc = "Bit 0 - RO, Flash ROM operation result: 0=success, 1=operation time out"]
+    #[inline(always)]
+    pub fn rb_rom_cmd_tout(&self) -> RB_ROM_CMD_TOUT_R {
+        RB_ROM_CMD_TOUT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RO, Flash ROM operation command error flag: 0=command accepted, 1=unknown command"]
+    #[inline(always)]
+    pub fn rb_rom_cmd_err(&self) -> RB_ROM_CMD_ERR_R {
+        RB_ROM_CMD_ERR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RO, Flash ROM erase/write operation address valid flag, can be reviewed before or after operation: 0=invalid parameter, 1=address valid"]
+    #[inline(always)]
+    pub fn rb_rom_addr_ok(&self) -> RB_ROM_ADDR_OK_R {
+        RB_ROM_ADDR_OK_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 8 - RO, indicate protected status of Flash ROM code and data: 0=reading protect, 1=enable read by external programmer"]
+    #[inline(always)]
+    pub fn rb_rom_read_free(&self) -> RB_ROM_READ_FREE_R {
+        RB_ROM_READ_FREE_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+#[doc = "RO, Flash ROM operation status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_flash_status](index.html) module"]
+pub struct R16_FLASH_STATUS_SPEC;
+impl crate::RegisterSpec for R16_FLASH_STATUS_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_flash_status::R](R) reader structure"]
+impl crate::Readable for R16_FLASH_STATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets R16_FLASH_STATUS to value 0"]
+impl crate::Resettable for R16_FLASH_STATUS_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/flash/r32_flash_addr.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R32_FLASH_ADDR` reader"]
+pub struct R(crate::R<R32_FLASH_ADDR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R32_FLASH_ADDR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R32_FLASH_ADDR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R32_FLASH_ADDR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R32_FLASH_ADDR` writer"]
+pub struct W(crate::W<R32_FLASH_ADDR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R32_FLASH_ADDR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R32_FLASH_ADDR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R32_FLASH_ADDR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, Flash ROM address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r32_flash_addr](index.html) module"]
+pub struct R32_FLASH_ADDR_SPEC;
+impl crate::RegisterSpec for R32_FLASH_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [r32_flash_addr::R](R) reader structure"]
+impl crate::Readable for R32_FLASH_ADDR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r32_flash_addr::W](W) writer structure"]
+impl crate::Writable for R32_FLASH_ADDR_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R32_FLASH_ADDR to value 0"]
+impl crate::Resettable for R32_FLASH_ADDR_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/flash/r32_flash_data.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R32_FLASH_DATA` reader"]
+pub struct R(crate::R<R32_FLASH_DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R32_FLASH_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R32_FLASH_DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R32_FLASH_DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R32_FLASH_DATA` writer"]
+pub struct W(crate::W<R32_FLASH_DATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R32_FLASH_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R32_FLASH_DATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R32_FLASH_DATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, Flash ROM data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r32_flash_data](index.html) module"]
+pub struct R32_FLASH_DATA_SPEC;
+impl crate::RegisterSpec for R32_FLASH_DATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [r32_flash_data::R](R) reader structure"]
+impl crate::Readable for R32_FLASH_DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r32_flash_data::W](W) writer structure"]
+impl crate::Writable for R32_FLASH_DATA_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R32_FLASH_DATA to value 0"]
+impl crate::Resettable for R32_FLASH_DATA_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/flash/r8_flash_command.rs

@@ -0,0 +1,44 @@
+#[doc = "Register `R8_FLASH_COMMAND` writer"]
+pub struct W(crate::W<R8_FLASH_COMMAND_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_FLASH_COMMAND_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_FLASH_COMMAND_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_FLASH_COMMAND_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "WO, Flash ROM operation command\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_flash_command](index.html) module"]
+pub struct R8_FLASH_COMMAND_SPEC;
+impl crate::RegisterSpec for R8_FLASH_COMMAND_SPEC {
+    type Ux = u8;
+}
+#[doc = "`write(|w| ..)` method takes [r8_flash_command::W](W) writer structure"]
+impl crate::Writable for R8_FLASH_COMMAND_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_FLASH_COMMAND to value 0"]
+impl crate::Resettable for R8_FLASH_COMMAND_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/flash/r8_flash_protect.rs

@@ -0,0 +1,106 @@
+#[doc = "Register `R8_FLASH_PROTECT` reader"]
+pub struct R(crate::R<R8_FLASH_PROTECT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_FLASH_PROTECT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_FLASH_PROTECT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_FLASH_PROTECT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_FLASH_PROTECT` writer"]
+pub struct W(crate::W<R8_FLASH_PROTECT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_FLASH_PROTECT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_FLASH_PROTECT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_FLASH_PROTECT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_ROM_DATA_WE` reader - RW, enable Flash ROM data area being erase/write: 0=writing protect, 1=enable program and erase"]
+pub type RB_ROM_DATA_WE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ROM_DATA_WE` writer - RW, enable Flash ROM data area being erase/write: 0=writing protect, 1=enable program and erase"]
+pub type RB_ROM_DATA_WE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_FLASH_PROTECT_SPEC, bool, O>;
+#[doc = "Field `RB_ROM_CODE_WE` reader - RW, enable Flash ROM code area being erase/write: 0=writing protect, 1=enable program and erase"]
+pub type RB_ROM_CODE_WE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_ROM_CODE_WE` writer - RW, enable Flash ROM code area being erase/write: 0=writing protect, 1=enable program and erase"]
+pub type RB_ROM_CODE_WE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_FLASH_PROTECT_SPEC, bool, O>;
+#[doc = "Field `RB_ROM_WE_MUST_10` writer - RW, must write 10"]
+pub type RB_ROM_WE_MUST_10_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u8, R8_FLASH_PROTECT_SPEC, u8, u8, 2, O>;
+impl R {
+    #[doc = "Bit 2 - RW, enable Flash ROM data area being erase/write: 0=writing protect, 1=enable program and erase"]
+    #[inline(always)]
+    pub fn rb_rom_data_we(&self) -> RB_ROM_DATA_WE_R {
+        RB_ROM_DATA_WE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RW, enable Flash ROM code area being erase/write: 0=writing protect, 1=enable program and erase"]
+    #[inline(always)]
+    pub fn rb_rom_code_we(&self) -> RB_ROM_CODE_WE_R {
+        RB_ROM_CODE_WE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 2 - RW, enable Flash ROM data area being erase/write: 0=writing protect, 1=enable program and erase"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_rom_data_we(&mut self) -> RB_ROM_DATA_WE_W<2> {
+        RB_ROM_DATA_WE_W::new(self)
+    }
+    #[doc = "Bit 3 - RW, enable Flash ROM code area being erase/write: 0=writing protect, 1=enable program and erase"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_rom_code_we(&mut self) -> RB_ROM_CODE_WE_W<3> {
+        RB_ROM_CODE_WE_W::new(self)
+    }
+    #[doc = "Bits 6:7 - RW, must write 10"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_rom_we_must_10(&mut self) -> RB_ROM_WE_MUST_10_W<6> {
+        RB_ROM_WE_MUST_10_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, Flash ROM protect control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_flash_protect](index.html) module"]
+pub struct R8_FLASH_PROTECT_SPEC;
+impl crate::RegisterSpec for R8_FLASH_PROTECT_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_flash_protect::R](R) reader structure"]
+impl crate::Readable for R8_FLASH_PROTECT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_flash_protect::W](W) writer structure"]
+impl crate::Writable for R8_FLASH_PROTECT_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_FLASH_PROTECT to value 0"]
+impl crate::Resettable for R8_FLASH_PROTECT_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/generic.rs

@@ -0,0 +1,634 @@
+use core::marker;
+#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
+pub trait RawReg:
+    Copy
+    + Default
+    + From<bool>
+    + core::ops::BitOr<Output = Self>
+    + core::ops::BitAnd<Output = Self>
+    + core::ops::BitOrAssign
+    + core::ops::BitAndAssign
+    + core::ops::Not<Output = Self>
+    + core::ops::Shl<u8, Output = Self>
+{
+    #[doc = " Mask for bits of width `WI`"]
+    fn mask<const WI: u8>() -> Self;
+    #[doc = " Mask for bits of width 1"]
+    fn one() -> Self;
+}
+macro_rules! raw_reg {
+    ($ U : ty , $ size : literal , $ mask : ident) => {
+        impl RawReg for $U {
+            #[inline(always)]
+            fn mask<const WI: u8>() -> Self {
+                $mask::<WI>()
+            }
+            #[inline(always)]
+            fn one() -> Self {
+                1
+            }
+        }
+        const fn $mask<const WI: u8>() -> $U {
+            <$U>::MAX >> ($size - WI)
+        }
+    };
+}
+raw_reg!(u8, 8, mask_u8);
+raw_reg!(u16, 16, mask_u16);
+raw_reg!(u32, 32, mask_u32);
+raw_reg!(u64, 64, mask_u64);
+#[doc = " Raw register type"]
+pub trait RegisterSpec {
+    #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
+    type Ux: RawReg;
+}
+#[doc = " Trait implemented by readable registers to enable the `read` method."]
+#[doc = ""]
+#[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
+pub trait Readable: RegisterSpec {
+    #[doc = " Result from a call to `read` and argument to `modify`."]
+    type Reader: From<R<Self>> + core::ops::Deref<Target = R<Self>>;
+}
+#[doc = " Trait implemented by writeable registers."]
+#[doc = ""]
+#[doc = " This enables the  `write`, `write_with_zero` and `reset` methods."]
+#[doc = ""]
+#[doc = " Registers marked with `Readable` can be also be `modify`'ed."]
+pub trait Writable: RegisterSpec {
+    #[doc = " Writer type argument to `write`, et al."]
+    type Writer: From<W<Self>> + core::ops::DerefMut<Target = W<Self>>;
+    #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
+    #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
+}
+#[doc = " Reset value of the register."]
+#[doc = ""]
+#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
+#[doc = " register by using the `reset` method."]
+pub trait Resettable: RegisterSpec {
+    #[doc = " Reset value of the register."]
+    const RESET_VALUE: Self::Ux;
+    #[doc = " Reset value of the register."]
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        Self::RESET_VALUE
+    }
+}
+#[doc = " This structure provides volatile access to registers."]
+#[repr(transparent)]
+pub struct Reg<REG: RegisterSpec> {
+    register: vcell::VolatileCell<REG::Ux>,
+    _marker: marker::PhantomData<REG>,
+}
+unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
+impl<REG: RegisterSpec> Reg<REG> {
+    #[doc = " Returns the underlying memory address of register."]
+    #[doc = ""]
+    #[doc = " ```ignore"]
+    #[doc = " let reg_ptr = periph.reg.as_ptr();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn as_ptr(&self) -> *mut REG::Ux {
+        self.register.as_ptr()
+    }
+}
+impl<REG: Readable> Reg<REG> {
+    #[doc = " Reads the contents of a `Readable` register."]
+    #[doc = ""]
+    #[doc = " You can read the raw contents of a register by using `bits`:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.read().bits();"]
+    #[doc = " ```"]
+    #[doc = " or get the content of a particular field of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let reader = periph.reg.read();"]
+    #[doc = " let bits = reader.field1().bits();"]
+    #[doc = " let flag = reader.field2().bit_is_set();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn read(&self) -> REG::Reader {
+        REG::Reader::from(R {
+            bits: self.register.get(),
+            _reg: marker::PhantomData,
+        })
+    }
+}
+impl<REG: Resettable + Writable> Reg<REG> {
+    #[doc = " Writes the reset value to `Writable` register."]
+    #[doc = ""]
+    #[doc = " Resets the register to its initial state."]
+    #[inline(always)]
+    pub fn reset(&self) {
+        self.register.set(REG::RESET_VALUE)
+    }
+    #[doc = " Writes bits to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[inline(always)]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut REG::Writer::from(W {
+                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                _reg: marker::PhantomData,
+            }))
+            .bits,
+        );
+    }
+}
+impl<REG: Writable> Reg<REG> {
+    #[doc = " Writes 0 to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Unsafe to use with registers which don't allow to write 0."]
+    #[inline(always)]
+    pub unsafe fn write_with_zero<F>(&self, f: F)
+    where
+        F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut REG::Writer::from(W {
+                bits: REG::Ux::default(),
+                _reg: marker::PhantomData,
+            }))
+            .bits,
+        );
+    }
+}
+impl<REG: Readable + Writable> Reg<REG> {
+    #[doc = " Modifies the contents of the register by reading and then writing it."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
+    #[doc = "    r.bits() | 3"]
+    #[doc = " ) });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&REG::Reader, &'w mut REG::Writer) -> &'w mut W<REG>,
+    {
+        let bits = self.register.get();
+        self.register.set(
+            f(
+                &REG::Reader::from(R {
+                    bits,
+                    _reg: marker::PhantomData,
+                }),
+                &mut REG::Writer::from(W {
+                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                    _reg: marker::PhantomData,
+                }),
+            )
+            .bits,
+        );
+    }
+}
+#[doc = " Register reader."]
+#[doc = ""]
+#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
+#[doc = " method."]
+pub struct R<REG: RegisterSpec + ?Sized> {
+    pub(crate) bits: REG::Ux,
+    _reg: marker::PhantomData<REG>,
+}
+impl<REG: RegisterSpec> R<REG> {
+    #[doc = " Reads raw bits from register."]
+    #[inline(always)]
+    pub fn bits(&self) -> REG::Ux {
+        self.bits
+    }
+}
+impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
+where
+    REG::Ux: PartialEq,
+    FI: Copy,
+    REG::Ux: From<FI>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&REG::Ux::from(*other))
+    }
+}
+#[doc = " Register writer."]
+#[doc = ""]
+#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
+pub struct W<REG: RegisterSpec + ?Sized> {
+    #[doc = "Writable bits"]
+    pub(crate) bits: REG::Ux,
+    _reg: marker::PhantomData<REG>,
+}
+impl<REG: RegisterSpec> W<REG> {
+    #[doc = " Writes raw bits to the register."]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Read datasheet or reference manual to find what values are allowed to pass."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc(hidden)]
+pub struct FieldReaderRaw<U, T> {
+    pub(crate) bits: U,
+    _reg: marker::PhantomData<T>,
+}
+impl<U, FI> FieldReaderRaw<U, FI>
+where
+    U: Copy,
+{
+    #[doc = " Creates a new instance of the reader."]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(bits: U) -> Self {
+        Self {
+            bits,
+            _reg: marker::PhantomData,
+        }
+    }
+}
+#[doc(hidden)]
+pub struct BitReaderRaw<T> {
+    pub(crate) bits: bool,
+    _reg: marker::PhantomData<T>,
+}
+impl<FI> BitReaderRaw<FI> {
+    #[doc = " Creates a new instance of the reader."]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        Self {
+            bits,
+            _reg: marker::PhantomData,
+        }
+    }
+}
+#[doc = " Field reader."]
+#[doc = ""]
+#[doc = " Result of the `read` methods of fields."]
+pub type FieldReader<U, FI> = FieldReaderRaw<U, FI>;
+#[doc = " Bit-wise field reader"]
+pub type BitReader<FI> = BitReaderRaw<FI>;
+impl<U, FI> FieldReader<U, FI>
+where
+    U: Copy,
+{
+    #[doc = " Reads raw bits from field."]
+    #[inline(always)]
+    pub fn bits(&self) -> U {
+        self.bits
+    }
+}
+impl<U, FI> PartialEq<FI> for FieldReader<U, FI>
+where
+    U: PartialEq,
+    FI: Copy,
+    U: From<FI>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&U::from(*other))
+    }
+}
+impl<FI> PartialEq<FI> for BitReader<FI>
+where
+    FI: Copy,
+    bool: From<FI>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&bool::from(*other))
+    }
+}
+impl<FI> BitReader<FI> {
+    #[doc = " Value of the field as raw bits."]
+    #[inline(always)]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = " Returns `true` if the bit is clear (0)."]
+    #[inline(always)]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = " Returns `true` if the bit is set (1)."]
+    #[inline(always)]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc(hidden)]
+pub struct Safe;
+#[doc(hidden)]
+pub struct Unsafe;
+#[doc(hidden)]
+pub struct FieldWriterRaw<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    N: From<FI>,
+{
+    pub(crate) w: &'a mut REG::Writer,
+    _field: marker::PhantomData<(N, FI, Safety)>,
+}
+impl<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8>
+    FieldWriterRaw<'a, U, REG, N, FI, Safety, WI, O>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    N: From<FI>,
+{
+    #[doc = " Creates a new instance of the writer"]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(w: &'a mut REG::Writer) -> Self {
+        Self {
+            w,
+            _field: marker::PhantomData,
+        }
+    }
+}
+#[doc(hidden)]
+pub struct BitWriterRaw<'a, U, REG, FI, M, const O: u8>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    bool: From<FI>,
+{
+    pub(crate) w: &'a mut REG::Writer,
+    _field: marker::PhantomData<(FI, M)>,
+}
+impl<'a, U, REG, FI, M, const O: u8> BitWriterRaw<'a, U, REG, FI, M, O>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    bool: From<FI>,
+{
+    #[doc = " Creates a new instance of the writer"]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(w: &'a mut REG::Writer) -> Self {
+        Self {
+            w,
+            _field: marker::PhantomData,
+        }
+    }
+}
+#[doc = " Write field Proxy with unsafe `bits`"]
+pub type FieldWriter<'a, U, REG, N, FI, const WI: u8, const O: u8> =
+    FieldWriterRaw<'a, U, REG, N, FI, Unsafe, WI, O>;
+#[doc = " Write field Proxy with safe `bits`"]
+pub type FieldWriterSafe<'a, U, REG, N, FI, const WI: u8, const O: u8> =
+    FieldWriterRaw<'a, U, REG, N, FI, Safe, WI, O>;
+impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    N: From<FI>,
+{
+    #[doc = " Field width"]
+    pub const WIDTH: u8 = WI;
+}
+impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    N: From<FI>,
+{
+    #[doc = " Field width"]
+    pub const WIDTH: u8 = WI;
+}
+macro_rules! bit_proxy {
+    ($ writer : ident , $ mwv : ident) => {
+        #[doc(hidden)]
+        pub struct $mwv;
+        #[doc = " Bit-wise write field proxy"]
+        pub type $writer<'a, U, REG, FI, const O: u8> = BitWriterRaw<'a, U, REG, FI, $mwv, O>;
+        impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = U>,
+            bool: From<FI>,
+        {
+            #[doc = " Field width"]
+            pub const WIDTH: u8 = 1;
+        }
+    };
+}
+macro_rules! impl_bit_proxy {
+    ($ writer : ident) => {
+        impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = U>,
+            U: RawReg,
+            bool: From<FI>,
+        {
+            #[doc = " Writes bit to the field"]
+            #[inline(always)]
+            pub fn bit(self, value: bool) -> &'a mut REG::Writer {
+                self.w.bits &= !(U::one() << OF);
+                self.w.bits |= (U::from(value) & U::one()) << OF;
+                self.w
+            }
+            #[doc = " Writes `variant` to the field"]
+            #[inline(always)]
+            pub fn variant(self, variant: FI) -> &'a mut REG::Writer {
+                self.bit(bool::from(variant))
+            }
+        }
+    };
+}
+bit_proxy!(BitWriter, BitM);
+bit_proxy!(BitWriter1S, Bit1S);
+bit_proxy!(BitWriter0C, Bit0C);
+bit_proxy!(BitWriter1C, Bit1C);
+bit_proxy!(BitWriter0S, Bit0S);
+bit_proxy!(BitWriter1T, Bit1T);
+bit_proxy!(BitWriter0T, Bit0T);
+impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    U: RawReg + From<N>,
+    N: From<FI>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
+    #[inline(always)]
+    pub unsafe fn bits(self, value: N) -> &'a mut REG::Writer {
+        self.w.bits &= !(U::mask::<WI>() << OF);
+        self.w.bits |= (U::from(value) & U::mask::<WI>()) << OF;
+        self.w
+    }
+    #[doc = " Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FI) -> &'a mut REG::Writer {
+        unsafe { self.bits(N::from(variant)) }
+    }
+}
+impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    U: RawReg + From<N>,
+    N: From<FI>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bits(self, value: N) -> &'a mut REG::Writer {
+        self.w.bits &= !(U::mask::<WI>() << OF);
+        self.w.bits |= (U::from(value) & U::mask::<WI>()) << OF;
+        self.w
+    }
+    #[doc = " Writes `variant` to the field"]
+    #[inline(always)]
+    pub fn variant(self, variant: FI) -> &'a mut REG::Writer {
+        self.bits(N::from(variant))
+    }
+}
+impl_bit_proxy!(BitWriter);
+impl_bit_proxy!(BitWriter1S);
+impl_bit_proxy!(BitWriter0C);
+impl_bit_proxy!(BitWriter1C);
+impl_bit_proxy!(BitWriter0S);
+impl_bit_proxy!(BitWriter1T);
+impl_bit_proxy!(BitWriter0T);
+impl<'a, U, REG, FI, const OF: u8> BitWriter<'a, U, REG, FI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    U: RawReg,
+    bool: From<FI>,
+{
+    #[doc = " Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut REG::Writer {
+        self.w.bits |= U::one() << OF;
+        self.w
+    }
+    #[doc = " Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut REG::Writer {
+        self.w.bits &= !(U::one() << OF);
+        self.w
+    }
+}
+impl<'a, U, REG, FI, const OF: u8> BitWriter1S<'a, U, REG, FI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    U: RawReg,
+    bool: From<FI>,
+{
+    #[doc = " Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut REG::Writer {
+        self.w.bits |= U::one() << OF;
+        self.w
+    }
+}
+impl<'a, U, REG, FI, const OF: u8> BitWriter0C<'a, U, REG, FI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    U: RawReg,
+    bool: From<FI>,
+{
+    #[doc = " Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut REG::Writer {
+        self.w.bits &= !(U::one() << OF);
+        self.w
+    }
+}
+impl<'a, U, REG, FI, const OF: u8> BitWriter1C<'a, U, REG, FI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    U: RawReg,
+    bool: From<FI>,
+{
+    #[doc = "Clears the field bit by passing one"]
+    #[inline(always)]
+    pub fn clear_bit_by_one(self) -> &'a mut REG::Writer {
+        self.w.bits |= U::one() << OF;
+        self.w
+    }
+}
+impl<'a, U, REG, FI, const OF: u8> BitWriter0S<'a, U, REG, FI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    U: RawReg,
+    bool: From<FI>,
+{
+    #[doc = "Sets the field bit by passing zero"]
+    #[inline(always)]
+    pub fn set_bit_by_zero(self) -> &'a mut REG::Writer {
+        self.w.bits &= !(U::one() << OF);
+        self.w
+    }
+}
+impl<'a, U, REG, FI, const OF: u8> BitWriter1T<'a, U, REG, FI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    U: RawReg,
+    bool: From<FI>,
+{
+    #[doc = "Toggle the field bit by passing one"]
+    #[inline(always)]
+    pub fn toggle_bit(self) -> &'a mut REG::Writer {
+        self.w.bits |= U::one() << OF;
+        self.w
+    }
+}
+impl<'a, U, REG, FI, const OF: u8> BitWriter0T<'a, U, REG, FI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    U: RawReg,
+    bool: From<FI>,
+{
+    #[doc = "Toggle the field bit by passing zero"]
+    #[inline(always)]
+    pub fn toggle_bit(self) -> &'a mut REG::Writer {
+        self.w.bits &= !(U::one() << OF);
+        self.w
+    }
+}

src/lcd.rs

@@ -0,0 +1,29 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - R8_LCD_CTRL_MOD"]
+    pub r8_lcd_ctrl_mod: R8_LCD_CTRL_MOD,
+    _reserved1: [u8; 0x03],
+    #[doc = "0x04 - RW, LCD driver data0, address 0-3"]
+    pub r32_lcd_ram0: R32_LCD_RAM0,
+    #[doc = "0x08 - RW, LCD driver data1, address 4-7"]
+    pub r32_lcd_ram1: R32_LCD_RAM1,
+    #[doc = "0x0c - RW, LCD driver data2, address 8-12"]
+    pub r32_lcd_ram2: R32_LCD_RAM2,
+}
+#[doc = "R8_LCD_CTRL_MOD (rw) register accessor: an alias for `Reg<R8_LCD_CTRL_MOD_SPEC>`"]
+pub type R8_LCD_CTRL_MOD = crate::Reg<r8_lcd_ctrl_mod::R8_LCD_CTRL_MOD_SPEC>;
+#[doc = "R8_LCD_CTRL_MOD"]
+pub mod r8_lcd_ctrl_mod;
+#[doc = "R32_LCD_RAM0 (rw) register accessor: an alias for `Reg<R32_LCD_RAM0_SPEC>`"]
+pub type R32_LCD_RAM0 = crate::Reg<r32_lcd_ram0::R32_LCD_RAM0_SPEC>;
+#[doc = "RW, LCD driver data0, address 0-3"]
+pub mod r32_lcd_ram0;
+#[doc = "R32_LCD_RAM1 (rw) register accessor: an alias for `Reg<R32_LCD_RAM1_SPEC>`"]
+pub type R32_LCD_RAM1 = crate::Reg<r32_lcd_ram1::R32_LCD_RAM1_SPEC>;
+#[doc = "RW, LCD driver data1, address 4-7"]
+pub mod r32_lcd_ram1;
+#[doc = "R32_LCD_RAM2 (rw) register accessor: an alias for `Reg<R32_LCD_RAM2_SPEC>`"]
+pub type R32_LCD_RAM2 = crate::Reg<r32_lcd_ram2::R32_LCD_RAM2_SPEC>;
+#[doc = "RW, LCD driver data2, address 8-12"]
+pub mod r32_lcd_ram2;

src/lcd/r32_lcd_ram0.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R32_LCD_RAM0` reader"]
+pub struct R(crate::R<R32_LCD_RAM0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R32_LCD_RAM0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R32_LCD_RAM0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R32_LCD_RAM0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R32_LCD_RAM0` writer"]
+pub struct W(crate::W<R32_LCD_RAM0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R32_LCD_RAM0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R32_LCD_RAM0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R32_LCD_RAM0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, LCD driver data0, address 0-3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r32_lcd_ram0](index.html) module"]
+pub struct R32_LCD_RAM0_SPEC;
+impl crate::RegisterSpec for R32_LCD_RAM0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [r32_lcd_ram0::R](R) reader structure"]
+impl crate::Readable for R32_LCD_RAM0_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r32_lcd_ram0::W](W) writer structure"]
+impl crate::Writable for R32_LCD_RAM0_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R32_LCD_RAM0 to value 0"]
+impl crate::Resettable for R32_LCD_RAM0_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/lcd/r32_lcd_ram1.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R32_LCD_RAM1` reader"]
+pub struct R(crate::R<R32_LCD_RAM1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R32_LCD_RAM1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R32_LCD_RAM1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R32_LCD_RAM1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R32_LCD_RAM1` writer"]
+pub struct W(crate::W<R32_LCD_RAM1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R32_LCD_RAM1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R32_LCD_RAM1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R32_LCD_RAM1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, LCD driver data1, address 4-7\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r32_lcd_ram1](index.html) module"]
+pub struct R32_LCD_RAM1_SPEC;
+impl crate::RegisterSpec for R32_LCD_RAM1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [r32_lcd_ram1::R](R) reader structure"]
+impl crate::Readable for R32_LCD_RAM1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r32_lcd_ram1::W](W) writer structure"]
+impl crate::Writable for R32_LCD_RAM1_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R32_LCD_RAM1 to value 0"]
+impl crate::Resettable for R32_LCD_RAM1_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/lcd/r32_lcd_ram2.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R32_LCD_RAM2` reader"]
+pub struct R(crate::R<R32_LCD_RAM2_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R32_LCD_RAM2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R32_LCD_RAM2_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R32_LCD_RAM2_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R32_LCD_RAM2` writer"]
+pub struct W(crate::W<R32_LCD_RAM2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R32_LCD_RAM2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R32_LCD_RAM2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R32_LCD_RAM2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, LCD driver data2, address 8-12\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r32_lcd_ram2](index.html) module"]
+pub struct R32_LCD_RAM2_SPEC;
+impl crate::RegisterSpec for R32_LCD_RAM2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [r32_lcd_ram2::R](R) reader structure"]
+impl crate::Readable for R32_LCD_RAM2_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r32_lcd_ram2::W](W) writer structure"]
+impl crate::Writable for R32_LCD_RAM2_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R32_LCD_RAM2 to value 0"]
+impl crate::Resettable for R32_LCD_RAM2_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/lcd/r8_lcd_ctrl_mod.rs

@@ -0,0 +1,159 @@
+#[doc = "Register `R8_LCD_CTRL_MOD` reader"]
+pub struct R(crate::R<R8_LCD_CTRL_MOD_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_LCD_CTRL_MOD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_LCD_CTRL_MOD_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_LCD_CTRL_MOD_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_LCD_CTRL_MOD` writer"]
+pub struct W(crate::W<R8_LCD_CTRL_MOD_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_LCD_CTRL_MOD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_LCD_CTRL_MOD_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_LCD_CTRL_MOD_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_SYS_POWER_ON` reader - RW, LCD digital system enable"]
+pub type RB_SYS_POWER_ON_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SYS_POWER_ON` writer - RW, LCD digital system enable"]
+pub type RB_SYS_POWER_ON_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_LCD_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_LCD_POWER_ON` reader - RW, LCD analog system enable"]
+pub type RB_LCD_POWER_ON_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LCD_POWER_ON` writer - RW, LCD analog system enable"]
+pub type RB_LCD_POWER_ON_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_LCD_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_LCD_BIAS` reader - RW, LCD bias select: 0=1/2 bias, 1=1/3 bias"]
+pub type RB_LCD_BIAS_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LCD_BIAS` writer - RW, LCD bias select: 0=1/2 bias, 1=1/3 bias"]
+pub type RB_LCD_BIAS_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_LCD_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_LCD_DUTY` reader - RW, LCD duty select: 00=1/2 duty, 01=1/3 duty, 10=1/4 duty"]
+pub type RB_LCD_DUTY_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_LCD_DUTY` writer - RW, LCD duty select: 00=1/2 duty, 01=1/3 duty, 10=1/4 duty"]
+pub type RB_LCD_DUTY_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u8, R8_LCD_CTRL_MOD_SPEC, u8, u8, 2, O>;
+#[doc = "Field `RB_LCD_SCAN_CLK` reader - RW, LCD scan clock select: 00=256Hz, 01=512Hz, 10=1KHz, 11=128Hz"]
+pub type RB_LCD_SCAN_CLK_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_LCD_SCAN_CLK` writer - RW, LCD scan clock select: 00=256Hz, 01=512Hz, 10=1KHz, 11=128Hz"]
+pub type RB_LCD_SCAN_CLK_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u8, R8_LCD_CTRL_MOD_SPEC, u8, u8, 2, O>;
+#[doc = "Field `RB_LCD_V_SEL` reader - RW, LCD drive voltage:0=VIO33*100%(3.3V),1=VIO33*76%(2.5V)"]
+pub type RB_LCD_V_SEL_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LCD_V_SEL` writer - RW, LCD drive voltage:0=VIO33*100%(3.3V),1=VIO33*76%(2.5V)"]
+pub type RB_LCD_V_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_LCD_CTRL_MOD_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - RW, LCD digital system enable"]
+    #[inline(always)]
+    pub fn rb_sys_power_on(&self) -> RB_SYS_POWER_ON_R {
+        RB_SYS_POWER_ON_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RW, LCD analog system enable"]
+    #[inline(always)]
+    pub fn rb_lcd_power_on(&self) -> RB_LCD_POWER_ON_R {
+        RB_LCD_POWER_ON_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RW, LCD bias select: 0=1/2 bias, 1=1/3 bias"]
+    #[inline(always)]
+    pub fn rb_lcd_bias(&self) -> RB_LCD_BIAS_R {
+        RB_LCD_BIAS_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bits 3:4 - RW, LCD duty select: 00=1/2 duty, 01=1/3 duty, 10=1/4 duty"]
+    #[inline(always)]
+    pub fn rb_lcd_duty(&self) -> RB_LCD_DUTY_R {
+        RB_LCD_DUTY_R::new((self.bits >> 3) & 3)
+    }
+    #[doc = "Bits 5:6 - RW, LCD scan clock select: 00=256Hz, 01=512Hz, 10=1KHz, 11=128Hz"]
+    #[inline(always)]
+    pub fn rb_lcd_scan_clk(&self) -> RB_LCD_SCAN_CLK_R {
+        RB_LCD_SCAN_CLK_R::new((self.bits >> 5) & 3)
+    }
+    #[doc = "Bit 7 - RW, LCD drive voltage:0=VIO33*100%(3.3V),1=VIO33*76%(2.5V)"]
+    #[inline(always)]
+    pub fn rb_lcd_v_sel(&self) -> RB_LCD_V_SEL_R {
+        RB_LCD_V_SEL_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW, LCD digital system enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_sys_power_on(&mut self) -> RB_SYS_POWER_ON_W<0> {
+        RB_SYS_POWER_ON_W::new(self)
+    }
+    #[doc = "Bit 1 - RW, LCD analog system enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_lcd_power_on(&mut self) -> RB_LCD_POWER_ON_W<1> {
+        RB_LCD_POWER_ON_W::new(self)
+    }
+    #[doc = "Bit 2 - RW, LCD bias select: 0=1/2 bias, 1=1/3 bias"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_lcd_bias(&mut self) -> RB_LCD_BIAS_W<2> {
+        RB_LCD_BIAS_W::new(self)
+    }
+    #[doc = "Bits 3:4 - RW, LCD duty select: 00=1/2 duty, 01=1/3 duty, 10=1/4 duty"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_lcd_duty(&mut self) -> RB_LCD_DUTY_W<3> {
+        RB_LCD_DUTY_W::new(self)
+    }
+    #[doc = "Bits 5:6 - RW, LCD scan clock select: 00=256Hz, 01=512Hz, 10=1KHz, 11=128Hz"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_lcd_scan_clk(&mut self) -> RB_LCD_SCAN_CLK_W<5> {
+        RB_LCD_SCAN_CLK_W::new(self)
+    }
+    #[doc = "Bit 7 - RW, LCD drive voltage:0=VIO33*100%(3.3V),1=VIO33*76%(2.5V)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_lcd_v_sel(&mut self) -> RB_LCD_V_SEL_W<7> {
+        RB_LCD_V_SEL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "R8_LCD_CTRL_MOD\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_lcd_ctrl_mod](index.html) module"]
+pub struct R8_LCD_CTRL_MOD_SPEC;
+impl crate::RegisterSpec for R8_LCD_CTRL_MOD_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_lcd_ctrl_mod::R](R) reader structure"]
+impl crate::Readable for R8_LCD_CTRL_MOD_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_lcd_ctrl_mod::W](W) writer structure"]
+impl crate::Writable for R8_LCD_CTRL_MOD_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_LCD_CTRL_MOD to value 0"]
+impl crate::Resettable for R8_LCD_CTRL_MOD_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/led.rs

@@ -0,0 +1,51 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - RW, LED mode control"]
+    pub r8_led_ctrl_mod: R8_LED_CTRL_MOD,
+    #[doc = "0x01 - RW, LED serial clock divisor"]
+    pub r8_led_clock_div: R8_LED_CLOCK_DIV,
+    _reserved2: [u8; 0x02],
+    #[doc = "0x04 - RO, LED status"]
+    pub r8_led_status: R8_LED_STATUS,
+    _reserved3: [u8; 0x03],
+    #[doc = "0x08 - WO, LED FIFO register, width is half-word"]
+    pub r16_led_fifo: R16_LED_FIFO,
+    _reserved4: [u8; 0x06],
+    #[doc = "0x10 - RW, LED DMA main buffer remainder half-word count, exclude auxiliary buffer, automatic decreasing after DMA, only low 12 bit"]
+    pub r16_led_dma_cnt: R16_LED_DMA_CNT,
+    _reserved5: [u8; 0x02],
+    #[doc = "0x14 - RW, LED main buffer DMA begin and current address, automatic increasing after DMA"]
+    pub r16_led_dma_main: R16_LED_DMA_MAIN,
+    _reserved6: [u8; 0x02],
+    #[doc = "0x18 - RW, LED auxiliary buffer DMA begin and current address, automatic increasing after DMA"]
+    pub r16_led_dma_aux: R16_LED_DMA_AUX,
+}
+#[doc = "R8_LED_CTRL_MOD (rw) register accessor: an alias for `Reg<R8_LED_CTRL_MOD_SPEC>`"]
+pub type R8_LED_CTRL_MOD = crate::Reg<r8_led_ctrl_mod::R8_LED_CTRL_MOD_SPEC>;
+#[doc = "RW, LED mode control"]
+pub mod r8_led_ctrl_mod;
+#[doc = "R8_LED_CLOCK_DIV (rw) register accessor: an alias for `Reg<R8_LED_CLOCK_DIV_SPEC>`"]
+pub type R8_LED_CLOCK_DIV = crate::Reg<r8_led_clock_div::R8_LED_CLOCK_DIV_SPEC>;
+#[doc = "RW, LED serial clock divisor"]
+pub mod r8_led_clock_div;
+#[doc = "R8_LED_STATUS (rw) register accessor: an alias for `Reg<R8_LED_STATUS_SPEC>`"]
+pub type R8_LED_STATUS = crate::Reg<r8_led_status::R8_LED_STATUS_SPEC>;
+#[doc = "RO, LED status"]
+pub mod r8_led_status;
+#[doc = "R16_LED_FIFO (w) register accessor: an alias for `Reg<R16_LED_FIFO_SPEC>`"]
+pub type R16_LED_FIFO = crate::Reg<r16_led_fifo::R16_LED_FIFO_SPEC>;
+#[doc = "WO, LED FIFO register, width is half-word"]
+pub mod r16_led_fifo;
+#[doc = "R16_LED_DMA_CNT (rw) register accessor: an alias for `Reg<R16_LED_DMA_CNT_SPEC>`"]
+pub type R16_LED_DMA_CNT = crate::Reg<r16_led_dma_cnt::R16_LED_DMA_CNT_SPEC>;
+#[doc = "RW, LED DMA main buffer remainder half-word count, exclude auxiliary buffer, automatic decreasing after DMA, only low 12 bit"]
+pub mod r16_led_dma_cnt;
+#[doc = "R16_LED_DMA_MAIN (rw) register accessor: an alias for `Reg<R16_LED_DMA_MAIN_SPEC>`"]
+pub type R16_LED_DMA_MAIN = crate::Reg<r16_led_dma_main::R16_LED_DMA_MAIN_SPEC>;
+#[doc = "RW, LED main buffer DMA begin and current address, automatic increasing after DMA"]
+pub mod r16_led_dma_main;
+#[doc = "R16_LED_DMA_AUX (rw) register accessor: an alias for `Reg<R16_LED_DMA_AUX_SPEC>`"]
+pub type R16_LED_DMA_AUX = crate::Reg<r16_led_dma_aux::R16_LED_DMA_AUX_SPEC>;
+#[doc = "RW, LED auxiliary buffer DMA begin and current address, automatic increasing after DMA"]
+pub mod r16_led_dma_aux;

src/led/r16_led_dma_aux.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_LED_DMA_AUX` reader"]
+pub struct R(crate::R<R16_LED_DMA_AUX_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_LED_DMA_AUX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_LED_DMA_AUX_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_LED_DMA_AUX_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_LED_DMA_AUX` writer"]
+pub struct W(crate::W<R16_LED_DMA_AUX_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_LED_DMA_AUX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_LED_DMA_AUX_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_LED_DMA_AUX_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, LED auxiliary buffer DMA begin and current address, automatic increasing after DMA\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_led_dma_aux](index.html) module"]
+pub struct R16_LED_DMA_AUX_SPEC;
+impl crate::RegisterSpec for R16_LED_DMA_AUX_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_led_dma_aux::R](R) reader structure"]
+impl crate::Readable for R16_LED_DMA_AUX_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_led_dma_aux::W](W) writer structure"]
+impl crate::Writable for R16_LED_DMA_AUX_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_LED_DMA_AUX to value 0"]
+impl crate::Resettable for R16_LED_DMA_AUX_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/led/r16_led_dma_cnt.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_LED_DMA_CNT` reader"]
+pub struct R(crate::R<R16_LED_DMA_CNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_LED_DMA_CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_LED_DMA_CNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_LED_DMA_CNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_LED_DMA_CNT` writer"]
+pub struct W(crate::W<R16_LED_DMA_CNT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_LED_DMA_CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_LED_DMA_CNT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_LED_DMA_CNT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, LED DMA main buffer remainder half-word count, exclude auxiliary buffer, automatic decreasing after DMA, only low 12 bit\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_led_dma_cnt](index.html) module"]
+pub struct R16_LED_DMA_CNT_SPEC;
+impl crate::RegisterSpec for R16_LED_DMA_CNT_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_led_dma_cnt::R](R) reader structure"]
+impl crate::Readable for R16_LED_DMA_CNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_led_dma_cnt::W](W) writer structure"]
+impl crate::Writable for R16_LED_DMA_CNT_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_LED_DMA_CNT to value 0"]
+impl crate::Resettable for R16_LED_DMA_CNT_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/led/r16_led_dma_main.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_LED_DMA_MAIN` reader"]
+pub struct R(crate::R<R16_LED_DMA_MAIN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_LED_DMA_MAIN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_LED_DMA_MAIN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_LED_DMA_MAIN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_LED_DMA_MAIN` writer"]
+pub struct W(crate::W<R16_LED_DMA_MAIN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_LED_DMA_MAIN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_LED_DMA_MAIN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_LED_DMA_MAIN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, LED main buffer DMA begin and current address, automatic increasing after DMA\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_led_dma_main](index.html) module"]
+pub struct R16_LED_DMA_MAIN_SPEC;
+impl crate::RegisterSpec for R16_LED_DMA_MAIN_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_led_dma_main::R](R) reader structure"]
+impl crate::Readable for R16_LED_DMA_MAIN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_led_dma_main::W](W) writer structure"]
+impl crate::Writable for R16_LED_DMA_MAIN_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_LED_DMA_MAIN to value 0"]
+impl crate::Resettable for R16_LED_DMA_MAIN_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/led/r16_led_fifo.rs

@@ -0,0 +1,44 @@
+#[doc = "Register `R16_LED_FIFO` writer"]
+pub struct W(crate::W<R16_LED_FIFO_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_LED_FIFO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_LED_FIFO_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_LED_FIFO_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "WO, LED FIFO register, width is half-word\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_led_fifo](index.html) module"]
+pub struct R16_LED_FIFO_SPEC;
+impl crate::RegisterSpec for R16_LED_FIFO_SPEC {
+    type Ux = u16;
+}
+#[doc = "`write(|w| ..)` method takes [r16_led_fifo::W](W) writer structure"]
+impl crate::Writable for R16_LED_FIFO_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_LED_FIFO to value 0"]
+impl crate::Resettable for R16_LED_FIFO_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/led/r8_led_clock_div.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_LED_CLOCK_DIV` reader"]
+pub struct R(crate::R<R8_LED_CLOCK_DIV_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_LED_CLOCK_DIV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_LED_CLOCK_DIV_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_LED_CLOCK_DIV_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_LED_CLOCK_DIV` writer"]
+pub struct W(crate::W<R8_LED_CLOCK_DIV_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_LED_CLOCK_DIV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_LED_CLOCK_DIV_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_LED_CLOCK_DIV_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, LED serial clock divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_led_clock_div](index.html) module"]
+pub struct R8_LED_CLOCK_DIV_SPEC;
+impl crate::RegisterSpec for R8_LED_CLOCK_DIV_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_led_clock_div::R](R) reader structure"]
+impl crate::Readable for R8_LED_CLOCK_DIV_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_led_clock_div::W](W) writer structure"]
+impl crate::Writable for R8_LED_CLOCK_DIV_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_LED_CLOCK_DIV to value 0"]
+impl crate::Resettable for R8_LED_CLOCK_DIV_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/led/r8_led_ctrl_mod.rs

@@ -0,0 +1,175 @@
+#[doc = "Register `R8_LED_CTRL_MOD` reader"]
+pub struct R(crate::R<R8_LED_CTRL_MOD_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_LED_CTRL_MOD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_LED_CTRL_MOD_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_LED_CTRL_MOD_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_LED_CTRL_MOD` writer"]
+pub struct W(crate::W<R8_LED_CTRL_MOD_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_LED_CTRL_MOD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_LED_CTRL_MOD_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_LED_CTRL_MOD_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_LED_BIT_ORDER` reader - RW, LED bit data order: 0=LSB first, 1=MSB first"]
+pub type RB_LED_BIT_ORDER_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LED_BIT_ORDER` writer - RW, LED bit data order: 0=LSB first, 1=MSB first"]
+pub type RB_LED_BIT_ORDER_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_LED_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_LED_ALL_CLEAR` reader - RW, force clear LED FIFO and count"]
+pub type RB_LED_ALL_CLEAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LED_ALL_CLEAR` writer - RW, force clear LED FIFO and count"]
+pub type RB_LED_ALL_CLEAR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_LED_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_LED_OUT_POLAR` reader - RW, LED output polarity: 0=pass, 1=invert"]
+pub type RB_LED_OUT_POLAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LED_OUT_POLAR` writer - RW, LED output polarity: 0=pass, 1=invert"]
+pub type RB_LED_OUT_POLAR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_LED_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_LED_OUT_EN` reader - RW, LED output enable"]
+pub type RB_LED_OUT_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LED_OUT_EN` writer - RW, LED output enable"]
+pub type RB_LED_OUT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_LED_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_LED_DMA_EN` reader - RW, LED DMA enable and DMA interrupt enable"]
+pub type RB_LED_DMA_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LED_DMA_EN` writer - RW, LED DMA enable and DMA interrupt enable"]
+pub type RB_LED_DMA_EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_LED_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_LED_IE_FIFO` reader - RW, enable interrupt for LED FIFO less than 2"]
+pub type RB_LED_IE_FIFO_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LED_IE_FIFO` writer - RW, enable interrupt for LED FIFO less than 2"]
+pub type RB_LED_IE_FIFO_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_LED_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_LED_CHAN_MOD` reader - RW, LED channel mode: 00=LED0, 01=LED0/1, 10=LED0~3, 11=LED0~3 and LED2/3 from auxiliary buffer"]
+pub type RB_LED_CHAN_MOD_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_LED_CHAN_MOD` writer - RW, LED channel mode: 00=LED0, 01=LED0/1, 10=LED0~3, 11=LED0~3 and LED2/3 from auxiliary buffer"]
+pub type RB_LED_CHAN_MOD_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u8, R8_LED_CTRL_MOD_SPEC, u8, u8, 2, O>;
+impl R {
+    #[doc = "Bit 0 - RW, LED bit data order: 0=LSB first, 1=MSB first"]
+    #[inline(always)]
+    pub fn rb_led_bit_order(&self) -> RB_LED_BIT_ORDER_R {
+        RB_LED_BIT_ORDER_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RW, force clear LED FIFO and count"]
+    #[inline(always)]
+    pub fn rb_led_all_clear(&self) -> RB_LED_ALL_CLEAR_R {
+        RB_LED_ALL_CLEAR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RW, LED output polarity: 0=pass, 1=invert"]
+    #[inline(always)]
+    pub fn rb_led_out_polar(&self) -> RB_LED_OUT_POLAR_R {
+        RB_LED_OUT_POLAR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RW, LED output enable"]
+    #[inline(always)]
+    pub fn rb_led_out_en(&self) -> RB_LED_OUT_EN_R {
+        RB_LED_OUT_EN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RW, LED DMA enable and DMA interrupt enable"]
+    #[inline(always)]
+    pub fn rb_led_dma_en(&self) -> RB_LED_DMA_EN_R {
+        RB_LED_DMA_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RW, enable interrupt for LED FIFO less than 2"]
+    #[inline(always)]
+    pub fn rb_led_ie_fifo(&self) -> RB_LED_IE_FIFO_R {
+        RB_LED_IE_FIFO_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bits 6:7 - RW, LED channel mode: 00=LED0, 01=LED0/1, 10=LED0~3, 11=LED0~3 and LED2/3 from auxiliary buffer"]
+    #[inline(always)]
+    pub fn rb_led_chan_mod(&self) -> RB_LED_CHAN_MOD_R {
+        RB_LED_CHAN_MOD_R::new((self.bits >> 6) & 3)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW, LED bit data order: 0=LSB first, 1=MSB first"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_led_bit_order(&mut self) -> RB_LED_BIT_ORDER_W<0> {
+        RB_LED_BIT_ORDER_W::new(self)
+    }
+    #[doc = "Bit 1 - RW, force clear LED FIFO and count"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_led_all_clear(&mut self) -> RB_LED_ALL_CLEAR_W<1> {
+        RB_LED_ALL_CLEAR_W::new(self)
+    }
+    #[doc = "Bit 2 - RW, LED output polarity: 0=pass, 1=invert"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_led_out_polar(&mut self) -> RB_LED_OUT_POLAR_W<2> {
+        RB_LED_OUT_POLAR_W::new(self)
+    }
+    #[doc = "Bit 3 - RW, LED output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_led_out_en(&mut self) -> RB_LED_OUT_EN_W<3> {
+        RB_LED_OUT_EN_W::new(self)
+    }
+    #[doc = "Bit 4 - RW, LED DMA enable and DMA interrupt enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_led_dma_en(&mut self) -> RB_LED_DMA_EN_W<4> {
+        RB_LED_DMA_EN_W::new(self)
+    }
+    #[doc = "Bit 5 - RW, enable interrupt for LED FIFO less than 2"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_led_ie_fifo(&mut self) -> RB_LED_IE_FIFO_W<5> {
+        RB_LED_IE_FIFO_W::new(self)
+    }
+    #[doc = "Bits 6:7 - RW, LED channel mode: 00=LED0, 01=LED0/1, 10=LED0~3, 11=LED0~3 and LED2/3 from auxiliary buffer"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_led_chan_mod(&mut self) -> RB_LED_CHAN_MOD_W<6> {
+        RB_LED_CHAN_MOD_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, LED mode control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_led_ctrl_mod](index.html) module"]
+pub struct R8_LED_CTRL_MOD_SPEC;
+impl crate::RegisterSpec for R8_LED_CTRL_MOD_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_led_ctrl_mod::R](R) reader structure"]
+impl crate::Readable for R8_LED_CTRL_MOD_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_led_ctrl_mod::W](W) writer structure"]
+impl crate::Writable for R8_LED_CTRL_MOD_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_LED_CTRL_MOD to value 0"]
+impl crate::Resettable for R8_LED_CTRL_MOD_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/led/r8_led_status.rs

@@ -0,0 +1,117 @@
+#[doc = "Register `R8_LED_STATUS` reader"]
+pub struct R(crate::R<R8_LED_STATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_LED_STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_LED_STATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_LED_STATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_LED_STATUS` writer"]
+pub struct W(crate::W<R8_LED_STATUS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_LED_STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_LED_STATUS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_LED_STATUS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_LED_FIFO_COUNT` reader - RO, LED FIFO byte count status, must divided by 2 for width half-word"]
+pub type RB_LED_FIFO_COUNT_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_LED_CLOCK` reader - RO, current LED clock level"]
+pub type RB_LED_CLOCK_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LED_IF_FIFO` reader - RW1, interrupt flag for LED FIFO less than 2, cleared by RW1 or write R32/R16_LED_FIFO"]
+pub type RB_LED_IF_FIFO_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LED_IF_FIFO` writer - RW1, interrupt flag for LED FIFO less than 2, cleared by RW1 or write R32/R16_LED_FIFO"]
+pub type RB_LED_IF_FIFO_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_LED_STATUS_SPEC, bool, O>;
+#[doc = "Field `RB_LED_FIFO_EMPTY` reader - RO: indicate FIFO empty status"]
+pub type RB_LED_FIFO_EMPTY_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LED_IF_DMA_END` reader - RW1, interrupt flag for LED DMA completion, cleared by RW1 or write R32/R16_LED_DMA_CNT"]
+pub type RB_LED_IF_DMA_END_R = crate::BitReader<bool>;
+#[doc = "Field `RB_LED_IF_DMA_END` writer - RW1, interrupt flag for LED DMA completion, cleared by RW1 or write R32/R16_LED_DMA_CNT"]
+pub type RB_LED_IF_DMA_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_LED_STATUS_SPEC, bool, O>;
+impl R {
+    #[doc = "Bits 0:2 - RO, LED FIFO byte count status, must divided by 2 for width half-word"]
+    #[inline(always)]
+    pub fn rb_led_fifo_count(&self) -> RB_LED_FIFO_COUNT_R {
+        RB_LED_FIFO_COUNT_R::new(self.bits & 7)
+    }
+    #[doc = "Bit 4 - RO, current LED clock level"]
+    #[inline(always)]
+    pub fn rb_led_clock(&self) -> RB_LED_CLOCK_R {
+        RB_LED_CLOCK_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RW1, interrupt flag for LED FIFO less than 2, cleared by RW1 or write R32/R16_LED_FIFO"]
+    #[inline(always)]
+    pub fn rb_led_if_fifo(&self) -> RB_LED_IF_FIFO_R {
+        RB_LED_IF_FIFO_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RO: indicate FIFO empty status"]
+    #[inline(always)]
+    pub fn rb_led_fifo_empty(&self) -> RB_LED_FIFO_EMPTY_R {
+        RB_LED_FIFO_EMPTY_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - RW1, interrupt flag for LED DMA completion, cleared by RW1 or write R32/R16_LED_DMA_CNT"]
+    #[inline(always)]
+    pub fn rb_led_if_dma_end(&self) -> RB_LED_IF_DMA_END_R {
+        RB_LED_IF_DMA_END_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 5 - RW1, interrupt flag for LED FIFO less than 2, cleared by RW1 or write R32/R16_LED_FIFO"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_led_if_fifo(&mut self) -> RB_LED_IF_FIFO_W<5> {
+        RB_LED_IF_FIFO_W::new(self)
+    }
+    #[doc = "Bit 7 - RW1, interrupt flag for LED DMA completion, cleared by RW1 or write R32/R16_LED_DMA_CNT"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_led_if_dma_end(&mut self) -> RB_LED_IF_DMA_END_W<7> {
+        RB_LED_IF_DMA_END_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RO, LED status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_led_status](index.html) module"]
+pub struct R8_LED_STATUS_SPEC;
+impl crate::RegisterSpec for R8_LED_STATUS_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_led_status::R](R) reader structure"]
+impl crate::Readable for R8_LED_STATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_led_status::W](W) writer structure"]
+impl crate::Writable for R8_LED_STATUS_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_LED_STATUS to value 0"]
+impl crate::Resettable for R8_LED_STATUS_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/lib.rs

@@ -0,0 +1,729 @@
+#![doc = "Peripheral access API for CH579SFR microcontrollers (generated using svd2rust v0.28.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
+svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.28.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![deny(dead_code)]
+#![deny(improper_ctypes)]
+#![deny(missing_docs)]
+#![deny(no_mangle_generic_items)]
+#![deny(non_shorthand_field_patterns)]
+#![deny(overflowing_literals)]
+#![deny(path_statements)]
+#![deny(patterns_in_fns_without_body)]
+#![deny(private_in_public)]
+#![deny(unconditional_recursion)]
+#![deny(unused_allocation)]
+#![deny(unused_comparisons)]
+#![deny(unused_parens)]
+#![deny(while_true)]
+#![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
+#![no_std]
+use core::marker::PhantomData;
+use core::ops::Deref;
+#[doc = r"Number available in the NVIC for configuring priority"]
+pub const NVIC_PRIO_BITS: u8 = 2;
+#[cfg(feature = "rt")]
+pub use self::Interrupt as interrupt;
+pub use cortex_m::peripheral::Peripherals as CorePeripherals;
+pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU};
+#[cfg(feature = "rt")]
+pub use cortex_m_rt::interrupt;
+#[allow(unused_imports)]
+use generic::*;
+#[doc = r"Common register and bit access and modify traits"]
+pub mod generic;
+#[cfg(feature = "rt")]
+extern "C" {
+    fn TMR0();
+    fn GPIO();
+    fn SLAVE();
+    fn SPI0();
+    fn BB();
+    fn LLE();
+    fn USB();
+    fn ETH();
+    fn TMR1();
+    fn TMR2();
+    fn UART0();
+    fn UART1();
+    fn RTC();
+    fn ADC();
+    fn SPI1();
+    fn LED();
+    fn TMR3();
+    fn UART2();
+    fn UART3();
+    fn WDOG_BAT();
+}
+#[doc(hidden)]
+pub union Vector {
+    _handler: unsafe extern "C" fn(),
+    _reserved: u32,
+}
+#[cfg(feature = "rt")]
+#[doc(hidden)]
+#[link_section = ".vector_table.interrupts"]
+#[no_mangle]
+pub static __INTERRUPTS: [Vector; 20] = [
+    Vector { _handler: TMR0 },
+    Vector { _handler: GPIO },
+    Vector { _handler: SLAVE },
+    Vector { _handler: SPI0 },
+    Vector { _handler: BB },
+    Vector { _handler: LLE },
+    Vector { _handler: USB },
+    Vector { _handler: ETH },
+    Vector { _handler: TMR1 },
+    Vector { _handler: TMR2 },
+    Vector { _handler: UART0 },
+    Vector { _handler: UART1 },
+    Vector { _handler: RTC },
+    Vector { _handler: ADC },
+    Vector { _handler: SPI1 },
+    Vector { _handler: LED },
+    Vector { _handler: TMR3 },
+    Vector { _handler: UART2 },
+    Vector { _handler: UART3 },
+    Vector { _handler: WDOG_BAT },
+];
+#[doc = r"Enumeration of all the interrupts."]
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[repr(u16)]
+pub enum Interrupt {
+    #[doc = "0 - TMR0_IRQHandler"]
+    TMR0 = 0,
+    #[doc = "1 - GPIO_IRQHandler"]
+    GPIO = 1,
+    #[doc = "2 - SLAVE_IRQHandler"]
+    SLAVE = 2,
+    #[doc = "3 - SPI0_IRQHandler"]
+    SPI0 = 3,
+    #[doc = "4 - BB_IRQHandler"]
+    BB = 4,
+    #[doc = "5 - LLE_IRQHandler"]
+    LLE = 5,
+    #[doc = "6 - USB_IRQHandler"]
+    USB = 6,
+    #[doc = "7 - ETH_IRQHandler"]
+    ETH = 7,
+    #[doc = "8 - TMR1_IRQHandler"]
+    TMR1 = 8,
+    #[doc = "9 - TMR2_IRQHandler"]
+    TMR2 = 9,
+    #[doc = "10 - UART0_IRQHandler"]
+    UART0 = 10,
+    #[doc = "11 - UART1_IRQHandler"]
+    UART1 = 11,
+    #[doc = "12 - RTC_IRQHandler"]
+    RTC = 12,
+    #[doc = "13 - ADC_IRQHandler"]
+    ADC = 13,
+    #[doc = "14 - SPI1_IRQHandler"]
+    SPI1 = 14,
+    #[doc = "15 - LED_IRQHandler"]
+    LED = 15,
+    #[doc = "16 - TMR3_IRQHandler"]
+    TMR3 = 16,
+    #[doc = "17 - UART1_IRQHandler"]
+    UART2 = 17,
+    #[doc = "18 - UART3_IRQHandler"]
+    UART3 = 18,
+    #[doc = "19 - WDT_IRQHandler"]
+    WDOG_BAT = 19,
+}
+unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
+    #[inline(always)]
+    fn number(self) -> u16 {
+        self as u16
+    }
+}
+#[doc = "System Control Register"]
+pub struct SYS {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for SYS {}
+impl SYS {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const sys::RegisterBlock = 0x4000_1000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const sys::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for SYS {
+    type Target = sys::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for SYS {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SYS").finish()
+    }
+}
+#[doc = "System Control Register"]
+pub mod sys;
+#[doc = "Flash ROM control register"]
+pub struct FLASH {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for FLASH {}
+impl FLASH {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const flash::RegisterBlock = 0x4000_1800 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const flash::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for FLASH {
+    type Target = flash::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for FLASH {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("FLASH").finish()
+    }
+}
+#[doc = "Flash ROM control register"]
+pub mod flash;
+#[doc = "Timer0 register"]
+pub struct TMR0 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for TMR0 {}
+impl TMR0 {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const tmr0::RegisterBlock = 0x4000_2000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const tmr0::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for TMR0 {
+    type Target = tmr0::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for TMR0 {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TMR0").finish()
+    }
+}
+#[doc = "Timer0 register"]
+pub mod tmr0;
+#[doc = "Timer1 register"]
+pub struct TMR1 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for TMR1 {}
+impl TMR1 {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const tmr1::RegisterBlock = 0x4000_2400 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const tmr1::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for TMR1 {
+    type Target = tmr1::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for TMR1 {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TMR1").finish()
+    }
+}
+#[doc = "Timer1 register"]
+pub mod tmr1;
+#[doc = "Timer2 register"]
+pub struct TMR2 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for TMR2 {}
+impl TMR2 {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const tmr2::RegisterBlock = 0x4000_2800 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const tmr2::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for TMR2 {
+    type Target = tmr2::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for TMR2 {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TMR2").finish()
+    }
+}
+#[doc = "Timer2 register"]
+pub mod tmr2;
+#[doc = "Timer3 register"]
+pub struct TMR3 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for TMR3 {}
+impl TMR3 {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const tmr3::RegisterBlock = 0x4000_2c00 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const tmr3::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for TMR3 {
+    type Target = tmr3::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for TMR3 {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TMR3").finish()
+    }
+}
+#[doc = "Timer3 register"]
+pub mod tmr3;
+#[doc = "UART0 register"]
+pub struct UART0 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for UART0 {}
+impl UART0 {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const uart0::RegisterBlock = 0x4000_3000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const uart0::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for UART0 {
+    type Target = uart0::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for UART0 {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("UART0").finish()
+    }
+}
+#[doc = "UART0 register"]
+pub mod uart0;
+#[doc = "UART1 register"]
+pub struct UART1 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for UART1 {}
+impl UART1 {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const uart1::RegisterBlock = 0x4000_3400 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const uart1::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for UART1 {
+    type Target = uart1::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for UART1 {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("UART1").finish()
+    }
+}
+#[doc = "UART1 register"]
+pub mod uart1;
+#[doc = "UART2 register"]
+pub struct UART2 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for UART2 {}
+impl UART2 {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const uart2::RegisterBlock = 0x4000_3800 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const uart2::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for UART2 {
+    type Target = uart2::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for UART2 {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("UART2").finish()
+    }
+}
+#[doc = "UART2 register"]
+pub mod uart2;
+#[doc = "UART3 register"]
+pub struct UART3 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for UART3 {}
+impl UART3 {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const uart3::RegisterBlock = 0x4000_3c00 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const uart3::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for UART3 {
+    type Target = uart3::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for UART3 {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("UART3").finish()
+    }
+}
+#[doc = "UART3 register"]
+pub mod uart3;
+#[doc = "SPI0 register"]
+pub struct SPI0 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for SPI0 {}
+impl SPI0 {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const spi0::RegisterBlock = 0x4000_4000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const spi0::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for SPI0 {
+    type Target = spi0::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for SPI0 {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SPI0").finish()
+    }
+}
+#[doc = "SPI0 register"]
+pub mod spi0;
+#[doc = "SPI1 register"]
+pub struct SPI1 {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for SPI1 {}
+impl SPI1 {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const spi1::RegisterBlock = 0x4000_4400 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const spi1::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for SPI1 {
+    type Target = spi1::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for SPI1 {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SPI1").finish()
+    }
+}
+#[doc = "SPI1 register"]
+pub mod spi1;
+#[doc = "PWMx register"]
+pub struct PWMX {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for PWMX {}
+impl PWMX {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const pwmx::RegisterBlock = 0x4000_5000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const pwmx::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for PWMX {
+    type Target = pwmx::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for PWMX {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PWMX").finish()
+    }
+}
+#[doc = "PWMx register"]
+pub mod pwmx;
+#[doc = "LCD register"]
+pub struct LCD {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for LCD {}
+impl LCD {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const lcd::RegisterBlock = 0x4000_6000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const lcd::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for LCD {
+    type Target = lcd::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for LCD {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LCD").finish()
+    }
+}
+#[doc = "LCD register"]
+pub mod lcd;
+#[doc = "LED register"]
+pub struct LED {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for LED {}
+impl LED {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const led::RegisterBlock = 0x4000_6400 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const led::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for LED {
+    type Target = led::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for LED {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LED").finish()
+    }
+}
+#[doc = "LED register"]
+pub mod led;
+#[doc = "USB register"]
+pub struct USB {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for USB {}
+impl USB {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const usb::RegisterBlock = 0x4000_8000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const usb::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for USB {
+    type Target = usb::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for USB {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("USB").finish()
+    }
+}
+#[doc = "USB register"]
+pub mod usb;
+#[doc = "ETH register"]
+pub struct ETH {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for ETH {}
+impl ETH {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const eth::RegisterBlock = 0x4000_9000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const eth::RegisterBlock {
+        Self::PTR
+    }
+}
+impl Deref for ETH {
+    type Target = eth::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for ETH {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ETH").finish()
+    }
+}
+#[doc = "ETH register"]
+pub mod eth;
+#[no_mangle]
+static mut DEVICE_PERIPHERALS: bool = false;
+#[doc = r" All the peripherals."]
+#[allow(non_snake_case)]
+pub struct Peripherals {
+    #[doc = "SYS"]
+    pub SYS: SYS,
+    #[doc = "FLASH"]
+    pub FLASH: FLASH,
+    #[doc = "TMR0"]
+    pub TMR0: TMR0,
+    #[doc = "TMR1"]
+    pub TMR1: TMR1,
+    #[doc = "TMR2"]
+    pub TMR2: TMR2,
+    #[doc = "TMR3"]
+    pub TMR3: TMR3,
+    #[doc = "UART0"]
+    pub UART0: UART0,
+    #[doc = "UART1"]
+    pub UART1: UART1,
+    #[doc = "UART2"]
+    pub UART2: UART2,
+    #[doc = "UART3"]
+    pub UART3: UART3,
+    #[doc = "SPI0"]
+    pub SPI0: SPI0,
+    #[doc = "SPI1"]
+    pub SPI1: SPI1,
+    #[doc = "PWMX"]
+    pub PWMX: PWMX,
+    #[doc = "LCD"]
+    pub LCD: LCD,
+    #[doc = "LED"]
+    pub LED: LED,
+    #[doc = "USB"]
+    pub USB: USB,
+    #[doc = "ETH"]
+    pub ETH: ETH,
+}
+impl Peripherals {
+    #[doc = r" Returns all the peripherals *once*."]
+    #[cfg(feature = "critical-section")]
+    #[inline]
+    pub fn take() -> Option<Self> {
+        critical_section::with(|_| {
+            if unsafe { DEVICE_PERIPHERALS } {
+                return None;
+            }
+            Some(unsafe { Peripherals::steal() })
+        })
+    }
+    #[doc = r" Unchecked version of `Peripherals::take`."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Each of the returned peripherals must be used at most once."]
+    #[inline]
+    pub unsafe fn steal() -> Self {
+        DEVICE_PERIPHERALS = true;
+        Peripherals {
+            SYS: SYS {
+                _marker: PhantomData,
+            },
+            FLASH: FLASH {
+                _marker: PhantomData,
+            },
+            TMR0: TMR0 {
+                _marker: PhantomData,
+            },
+            TMR1: TMR1 {
+                _marker: PhantomData,
+            },
+            TMR2: TMR2 {
+                _marker: PhantomData,
+            },
+            TMR3: TMR3 {
+                _marker: PhantomData,
+            },
+            UART0: UART0 {
+                _marker: PhantomData,
+            },
+            UART1: UART1 {
+                _marker: PhantomData,
+            },
+            UART2: UART2 {
+                _marker: PhantomData,
+            },
+            UART3: UART3 {
+                _marker: PhantomData,
+            },
+            SPI0: SPI0 {
+                _marker: PhantomData,
+            },
+            SPI1: SPI1 {
+                _marker: PhantomData,
+            },
+            PWMX: PWMX {
+                _marker: PhantomData,
+            },
+            LCD: LCD {
+                _marker: PhantomData,
+            },
+            LED: LED {
+                _marker: PhantomData,
+            },
+            USB: USB {
+                _marker: PhantomData,
+            },
+            ETH: ETH {
+                _marker: PhantomData,
+            },
+        }
+    }
+}

src/pwmx.rs

@@ -0,0 +1,76 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - RW, PWM output enable control"]
+    pub r8_pwm_out_en: R8_PWM_OUT_EN,
+    #[doc = "0x01 - RW, PWM output polarity control"]
+    pub r8_pwm_polar: R8_PWM_POLAR,
+    #[doc = "0x02 - RW, PWM configuration"]
+    pub r8_pwm_config: R8_PWM_CONFIG,
+    #[doc = "0x03 - RW, PWM clock divisor"]
+    pub r8_pwm_clock_div: R8_PWM_CLOCK_DIV,
+    #[doc = "0x04 - RW, PWM4 data holding"]
+    pub r8_pwm4_data: R8_PWM4_DATA,
+    #[doc = "0x05 - RW, PWM5 data holding"]
+    pub r8_pwm5_data: R8_PWM5_DATA,
+    #[doc = "0x06 - RW, PWM6 data holding"]
+    pub r8_pwm6_data: R8_PWM6_DATA,
+    #[doc = "0x07 - RW, PWM7 data holding"]
+    pub r8_pwm7_data: R8_PWM7_DATA,
+    #[doc = "0x08 - RW, PWM8 data holding"]
+    pub r8_pwm8_data: R8_PWM8_DATA,
+    #[doc = "0x09 - RW, PWM9 data holding"]
+    pub r8_pwm9_data: R8_PWM9_DATA,
+    #[doc = "0x0a - RW, PWM10 data holding"]
+    pub r8_pwm10_data: R8_PWM10_DATA,
+    #[doc = "0x0b - RW, PWM11 data holding"]
+    pub r8_pwm11_data: R8_PWM11_DATA,
+}
+#[doc = "R8_PWM_OUT_EN (rw) register accessor: an alias for `Reg<R8_PWM_OUT_EN_SPEC>`"]
+pub type R8_PWM_OUT_EN = crate::Reg<r8_pwm_out_en::R8_PWM_OUT_EN_SPEC>;
+#[doc = "RW, PWM output enable control"]
+pub mod r8_pwm_out_en;
+#[doc = "R8_PWM_POLAR (rw) register accessor: an alias for `Reg<R8_PWM_POLAR_SPEC>`"]
+pub type R8_PWM_POLAR = crate::Reg<r8_pwm_polar::R8_PWM_POLAR_SPEC>;
+#[doc = "RW, PWM output polarity control"]
+pub mod r8_pwm_polar;
+#[doc = "R8_PWM_CONFIG (rw) register accessor: an alias for `Reg<R8_PWM_CONFIG_SPEC>`"]
+pub type R8_PWM_CONFIG = crate::Reg<r8_pwm_config::R8_PWM_CONFIG_SPEC>;
+#[doc = "RW, PWM configuration"]
+pub mod r8_pwm_config;
+#[doc = "R8_PWM_CLOCK_DIV (rw) register accessor: an alias for `Reg<R8_PWM_CLOCK_DIV_SPEC>`"]
+pub type R8_PWM_CLOCK_DIV = crate::Reg<r8_pwm_clock_div::R8_PWM_CLOCK_DIV_SPEC>;
+#[doc = "RW, PWM clock divisor"]
+pub mod r8_pwm_clock_div;
+#[doc = "R8_PWM4_DATA (rw) register accessor: an alias for `Reg<R8_PWM4_DATA_SPEC>`"]
+pub type R8_PWM4_DATA = crate::Reg<r8_pwm4_data::R8_PWM4_DATA_SPEC>;
+#[doc = "RW, PWM4 data holding"]
+pub mod r8_pwm4_data;
+#[doc = "R8_PWM5_DATA (rw) register accessor: an alias for `Reg<R8_PWM5_DATA_SPEC>`"]
+pub type R8_PWM5_DATA = crate::Reg<r8_pwm5_data::R8_PWM5_DATA_SPEC>;
+#[doc = "RW, PWM5 data holding"]
+pub mod r8_pwm5_data;
+#[doc = "R8_PWM6_DATA (rw) register accessor: an alias for `Reg<R8_PWM6_DATA_SPEC>`"]
+pub type R8_PWM6_DATA = crate::Reg<r8_pwm6_data::R8_PWM6_DATA_SPEC>;
+#[doc = "RW, PWM6 data holding"]
+pub mod r8_pwm6_data;
+#[doc = "R8_PWM7_DATA (rw) register accessor: an alias for `Reg<R8_PWM7_DATA_SPEC>`"]
+pub type R8_PWM7_DATA = crate::Reg<r8_pwm7_data::R8_PWM7_DATA_SPEC>;
+#[doc = "RW, PWM7 data holding"]
+pub mod r8_pwm7_data;
+#[doc = "R8_PWM8_DATA (rw) register accessor: an alias for `Reg<R8_PWM8_DATA_SPEC>`"]
+pub type R8_PWM8_DATA = crate::Reg<r8_pwm8_data::R8_PWM8_DATA_SPEC>;
+#[doc = "RW, PWM8 data holding"]
+pub mod r8_pwm8_data;
+#[doc = "R8_PWM9_DATA (rw) register accessor: an alias for `Reg<R8_PWM9_DATA_SPEC>`"]
+pub type R8_PWM9_DATA = crate::Reg<r8_pwm9_data::R8_PWM9_DATA_SPEC>;
+#[doc = "RW, PWM9 data holding"]
+pub mod r8_pwm9_data;
+#[doc = "R8_PWM10_DATA (rw) register accessor: an alias for `Reg<R8_PWM10_DATA_SPEC>`"]
+pub type R8_PWM10_DATA = crate::Reg<r8_pwm10_data::R8_PWM10_DATA_SPEC>;
+#[doc = "RW, PWM10 data holding"]
+pub mod r8_pwm10_data;
+#[doc = "R8_PWM11_DATA (rw) register accessor: an alias for `Reg<R8_PWM11_DATA_SPEC>`"]
+pub type R8_PWM11_DATA = crate::Reg<r8_pwm11_data::R8_PWM11_DATA_SPEC>;
+#[doc = "RW, PWM11 data holding"]
+pub mod r8_pwm11_data;

src/pwmx/r8_pwm10_data.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_PWM10_DATA` reader"]
+pub struct R(crate::R<R8_PWM10_DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM10_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM10_DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM10_DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM10_DATA` writer"]
+pub struct W(crate::W<R8_PWM10_DATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM10_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM10_DATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM10_DATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM10 data holding\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm10_data](index.html) module"]
+pub struct R8_PWM10_DATA_SPEC;
+impl crate::RegisterSpec for R8_PWM10_DATA_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm10_data::R](R) reader structure"]
+impl crate::Readable for R8_PWM10_DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm10_data::W](W) writer structure"]
+impl crate::Writable for R8_PWM10_DATA_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM10_DATA to value 0"]
+impl crate::Resettable for R8_PWM10_DATA_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/pwmx/r8_pwm11_data.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_PWM11_DATA` reader"]
+pub struct R(crate::R<R8_PWM11_DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM11_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM11_DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM11_DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM11_DATA` writer"]
+pub struct W(crate::W<R8_PWM11_DATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM11_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM11_DATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM11_DATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM11 data holding\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm11_data](index.html) module"]
+pub struct R8_PWM11_DATA_SPEC;
+impl crate::RegisterSpec for R8_PWM11_DATA_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm11_data::R](R) reader structure"]
+impl crate::Readable for R8_PWM11_DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm11_data::W](W) writer structure"]
+impl crate::Writable for R8_PWM11_DATA_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM11_DATA to value 0"]
+impl crate::Resettable for R8_PWM11_DATA_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/pwmx/r8_pwm4_data.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_PWM4_DATA` reader"]
+pub struct R(crate::R<R8_PWM4_DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM4_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM4_DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM4_DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM4_DATA` writer"]
+pub struct W(crate::W<R8_PWM4_DATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM4_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM4_DATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM4_DATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM4 data holding\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm4_data](index.html) module"]
+pub struct R8_PWM4_DATA_SPEC;
+impl crate::RegisterSpec for R8_PWM4_DATA_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm4_data::R](R) reader structure"]
+impl crate::Readable for R8_PWM4_DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm4_data::W](W) writer structure"]
+impl crate::Writable for R8_PWM4_DATA_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM4_DATA to value 0"]
+impl crate::Resettable for R8_PWM4_DATA_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/pwmx/r8_pwm5_data.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_PWM5_DATA` reader"]
+pub struct R(crate::R<R8_PWM5_DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM5_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM5_DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM5_DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM5_DATA` writer"]
+pub struct W(crate::W<R8_PWM5_DATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM5_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM5_DATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM5_DATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM5 data holding\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm5_data](index.html) module"]
+pub struct R8_PWM5_DATA_SPEC;
+impl crate::RegisterSpec for R8_PWM5_DATA_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm5_data::R](R) reader structure"]
+impl crate::Readable for R8_PWM5_DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm5_data::W](W) writer structure"]
+impl crate::Writable for R8_PWM5_DATA_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM5_DATA to value 0"]
+impl crate::Resettable for R8_PWM5_DATA_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/pwmx/r8_pwm6_data.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_PWM6_DATA` reader"]
+pub struct R(crate::R<R8_PWM6_DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM6_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM6_DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM6_DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM6_DATA` writer"]
+pub struct W(crate::W<R8_PWM6_DATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM6_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM6_DATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM6_DATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM6 data holding\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm6_data](index.html) module"]
+pub struct R8_PWM6_DATA_SPEC;
+impl crate::RegisterSpec for R8_PWM6_DATA_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm6_data::R](R) reader structure"]
+impl crate::Readable for R8_PWM6_DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm6_data::W](W) writer structure"]
+impl crate::Writable for R8_PWM6_DATA_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM6_DATA to value 0"]
+impl crate::Resettable for R8_PWM6_DATA_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/pwmx/r8_pwm7_data.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_PWM7_DATA` reader"]
+pub struct R(crate::R<R8_PWM7_DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM7_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM7_DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM7_DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM7_DATA` writer"]
+pub struct W(crate::W<R8_PWM7_DATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM7_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM7_DATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM7_DATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM7 data holding\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm7_data](index.html) module"]
+pub struct R8_PWM7_DATA_SPEC;
+impl crate::RegisterSpec for R8_PWM7_DATA_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm7_data::R](R) reader structure"]
+impl crate::Readable for R8_PWM7_DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm7_data::W](W) writer structure"]
+impl crate::Writable for R8_PWM7_DATA_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM7_DATA to value 0"]
+impl crate::Resettable for R8_PWM7_DATA_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/pwmx/r8_pwm8_data.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_PWM8_DATA` reader"]
+pub struct R(crate::R<R8_PWM8_DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM8_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM8_DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM8_DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM8_DATA` writer"]
+pub struct W(crate::W<R8_PWM8_DATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM8_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM8_DATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM8_DATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM8 data holding\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm8_data](index.html) module"]
+pub struct R8_PWM8_DATA_SPEC;
+impl crate::RegisterSpec for R8_PWM8_DATA_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm8_data::R](R) reader structure"]
+impl crate::Readable for R8_PWM8_DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm8_data::W](W) writer structure"]
+impl crate::Writable for R8_PWM8_DATA_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM8_DATA to value 0"]
+impl crate::Resettable for R8_PWM8_DATA_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/pwmx/r8_pwm9_data.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_PWM9_DATA` reader"]
+pub struct R(crate::R<R8_PWM9_DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM9_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM9_DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM9_DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM9_DATA` writer"]
+pub struct W(crate::W<R8_PWM9_DATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM9_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM9_DATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM9_DATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM9 data holding\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm9_data](index.html) module"]
+pub struct R8_PWM9_DATA_SPEC;
+impl crate::RegisterSpec for R8_PWM9_DATA_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm9_data::R](R) reader structure"]
+impl crate::Readable for R8_PWM9_DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm9_data::W](W) writer structure"]
+impl crate::Writable for R8_PWM9_DATA_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM9_DATA to value 0"]
+impl crate::Resettable for R8_PWM9_DATA_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/pwmx/r8_pwm_clock_div.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_PWM_CLOCK_DIV` reader"]
+pub struct R(crate::R<R8_PWM_CLOCK_DIV_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM_CLOCK_DIV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM_CLOCK_DIV_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM_CLOCK_DIV_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM_CLOCK_DIV` writer"]
+pub struct W(crate::W<R8_PWM_CLOCK_DIV_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM_CLOCK_DIV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM_CLOCK_DIV_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM_CLOCK_DIV_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM clock divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm_clock_div](index.html) module"]
+pub struct R8_PWM_CLOCK_DIV_SPEC;
+impl crate::RegisterSpec for R8_PWM_CLOCK_DIV_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm_clock_div::R](R) reader structure"]
+impl crate::Readable for R8_PWM_CLOCK_DIV_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm_clock_div::W](W) writer structure"]
+impl crate::Writable for R8_PWM_CLOCK_DIV_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM_CLOCK_DIV to value 0"]
+impl crate::Resettable for R8_PWM_CLOCK_DIV_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/pwmx/r8_pwm_config.rs

@@ -0,0 +1,168 @@
+#[doc = "Register `R8_PWM_CONFIG` reader"]
+pub struct R(crate::R<R8_PWM_CONFIG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM_CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM_CONFIG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM_CONFIG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM_CONFIG` writer"]
+pub struct W(crate::W<R8_PWM_CONFIG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM_CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM_CONFIG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM_CONFIG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_PWM_CYCLE_SEL` reader - RW, PWM cycle selection: 0=256/128/64/32 clocks, 1=255/127/63/31 clocks"]
+pub type RB_PWM_CYCLE_SEL_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM_CYCLE_SEL` writer - RW, PWM cycle selection: 0=256/128/64/32 clocks, 1=255/127/63/31 clocks"]
+pub type RB_PWM_CYCLE_SEL_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_PWM_CONFIG_SPEC, bool, O>;
+#[doc = "Field `RB_PWM_STAG_ST` reader - RO, PWM stagger cycle status"]
+pub type RB_PWM_STAG_ST_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM_CYC_MOD` reader - RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=5 bits data"]
+pub type RB_PWM_CYC_MOD_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_PWM_CYC_MOD` writer - RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=5 bits data"]
+pub type RB_PWM_CYC_MOD_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u8, R8_PWM_CONFIG_SPEC, u8, u8, 2, O>;
+#[doc = "Field `RB_PWM4_5_STAG_EN` reader - RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output"]
+pub type RB_PWM4_5_STAG_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM4_5_STAG_EN` writer - RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output"]
+pub type RB_PWM4_5_STAG_EN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_PWM_CONFIG_SPEC, bool, O>;
+#[doc = "Field `RB_PWM6_7_STAG_EN` reader - RW, PWM6/7 stagger output enable: 0=independent output, 1=stagger output"]
+pub type RB_PWM6_7_STAG_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM6_7_STAG_EN` writer - RW, PWM6/7 stagger output enable: 0=independent output, 1=stagger output"]
+pub type RB_PWM6_7_STAG_EN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_PWM_CONFIG_SPEC, bool, O>;
+#[doc = "Field `RB_PWM8_9_STAG_EN` reader - RW, PWM8/9 stagger output enable: 0=independent output, 1=stagger output"]
+pub type RB_PWM8_9_STAG_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM8_9_STAG_EN` writer - RW, PWM8/9 stagger output enable: 0=independent output, 1=stagger output"]
+pub type RB_PWM8_9_STAG_EN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_PWM_CONFIG_SPEC, bool, O>;
+#[doc = "Field `RB_PWM10_11_STAG_EN` reader - RW, PWM10/11 stagger output enable: 0=independent output, 1=stagger output"]
+pub type RB_PWM10_11_STAG_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM10_11_STAG_EN` writer - RW, PWM10/11 stagger output enable: 0=independent output, 1=stagger output"]
+pub type RB_PWM10_11_STAG_EN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_PWM_CONFIG_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - RW, PWM cycle selection: 0=256/128/64/32 clocks, 1=255/127/63/31 clocks"]
+    #[inline(always)]
+    pub fn rb_pwm_cycle_sel(&self) -> RB_PWM_CYCLE_SEL_R {
+        RB_PWM_CYCLE_SEL_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RO, PWM stagger cycle status"]
+    #[inline(always)]
+    pub fn rb_pwm_stag_st(&self) -> RB_PWM_STAG_ST_R {
+        RB_PWM_STAG_ST_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 2:3 - RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=5 bits data"]
+    #[inline(always)]
+    pub fn rb_pwm_cyc_mod(&self) -> RB_PWM_CYC_MOD_R {
+        RB_PWM_CYC_MOD_R::new((self.bits >> 2) & 3)
+    }
+    #[doc = "Bit 4 - RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output"]
+    #[inline(always)]
+    pub fn rb_pwm4_5_stag_en(&self) -> RB_PWM4_5_STAG_EN_R {
+        RB_PWM4_5_STAG_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RW, PWM6/7 stagger output enable: 0=independent output, 1=stagger output"]
+    #[inline(always)]
+    pub fn rb_pwm6_7_stag_en(&self) -> RB_PWM6_7_STAG_EN_R {
+        RB_PWM6_7_STAG_EN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RW, PWM8/9 stagger output enable: 0=independent output, 1=stagger output"]
+    #[inline(always)]
+    pub fn rb_pwm8_9_stag_en(&self) -> RB_PWM8_9_STAG_EN_R {
+        RB_PWM8_9_STAG_EN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - RW, PWM10/11 stagger output enable: 0=independent output, 1=stagger output"]
+    #[inline(always)]
+    pub fn rb_pwm10_11_stag_en(&self) -> RB_PWM10_11_STAG_EN_R {
+        RB_PWM10_11_STAG_EN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW, PWM cycle selection: 0=256/128/64/32 clocks, 1=255/127/63/31 clocks"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm_cycle_sel(&mut self) -> RB_PWM_CYCLE_SEL_W<0> {
+        RB_PWM_CYCLE_SEL_W::new(self)
+    }
+    #[doc = "Bits 2:3 - RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=5 bits data"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm_cyc_mod(&mut self) -> RB_PWM_CYC_MOD_W<2> {
+        RB_PWM_CYC_MOD_W::new(self)
+    }
+    #[doc = "Bit 4 - RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm4_5_stag_en(&mut self) -> RB_PWM4_5_STAG_EN_W<4> {
+        RB_PWM4_5_STAG_EN_W::new(self)
+    }
+    #[doc = "Bit 5 - RW, PWM6/7 stagger output enable: 0=independent output, 1=stagger output"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm6_7_stag_en(&mut self) -> RB_PWM6_7_STAG_EN_W<5> {
+        RB_PWM6_7_STAG_EN_W::new(self)
+    }
+    #[doc = "Bit 6 - RW, PWM8/9 stagger output enable: 0=independent output, 1=stagger output"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm8_9_stag_en(&mut self) -> RB_PWM8_9_STAG_EN_W<6> {
+        RB_PWM8_9_STAG_EN_W::new(self)
+    }
+    #[doc = "Bit 7 - RW, PWM10/11 stagger output enable: 0=independent output, 1=stagger output"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm10_11_stag_en(&mut self) -> RB_PWM10_11_STAG_EN_W<7> {
+        RB_PWM10_11_STAG_EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm_config](index.html) module"]
+pub struct R8_PWM_CONFIG_SPEC;
+impl crate::RegisterSpec for R8_PWM_CONFIG_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm_config::R](R) reader structure"]
+impl crate::Readable for R8_PWM_CONFIG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm_config::W](W) writer structure"]
+impl crate::Writable for R8_PWM_CONFIG_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM_CONFIG to value 0"]
+impl crate::Resettable for R8_PWM_CONFIG_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/pwmx/r8_pwm_out_en.rs

@@ -0,0 +1,185 @@
+#[doc = "Register `R8_PWM_OUT_EN` reader"]
+pub struct R(crate::R<R8_PWM_OUT_EN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM_OUT_EN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM_OUT_EN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM_OUT_EN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM_OUT_EN` writer"]
+pub struct W(crate::W<R8_PWM_OUT_EN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM_OUT_EN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM_OUT_EN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM_OUT_EN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_PWM4_OUT_EN` reader - RW, PWM4 output enable"]
+pub type RB_PWM4_OUT_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM4_OUT_EN` writer - RW, PWM4 output enable"]
+pub type RB_PWM4_OUT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_OUT_EN_SPEC, bool, O>;
+#[doc = "Field `RB_PWM5_OUT_EN` reader - RW, PWM5 output enable"]
+pub type RB_PWM5_OUT_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM5_OUT_EN` writer - RW, PWM5 output enable"]
+pub type RB_PWM5_OUT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_OUT_EN_SPEC, bool, O>;
+#[doc = "Field `RB_PWM6_OUT_EN` reader - RW, PWM6 output enable"]
+pub type RB_PWM6_OUT_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM6_OUT_EN` writer - RW, PWM6 output enable"]
+pub type RB_PWM6_OUT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_OUT_EN_SPEC, bool, O>;
+#[doc = "Field `RB_PWM7_OUT_EN` reader - RW, PWM7 output enable"]
+pub type RB_PWM7_OUT_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM7_OUT_EN` writer - RW, PWM7 output enable"]
+pub type RB_PWM7_OUT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_OUT_EN_SPEC, bool, O>;
+#[doc = "Field `RB_PWM8_OUT_EN` reader - RW, PWM8 output enable"]
+pub type RB_PWM8_OUT_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM8_OUT_EN` writer - RW, PWM8 output enable"]
+pub type RB_PWM8_OUT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_OUT_EN_SPEC, bool, O>;
+#[doc = "Field `RB_PWM9_OUT_EN` reader - RW, PWM9 output enable"]
+pub type RB_PWM9_OUT_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM9_OUT_EN` writer - RW, PWM9 output enable"]
+pub type RB_PWM9_OUT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_OUT_EN_SPEC, bool, O>;
+#[doc = "Field `RB_PWM10_OUT_EN` reader - RW, PWM10 output enable"]
+pub type RB_PWM10_OUT_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM10_OUT_EN` writer - RW, PWM10 output enable"]
+pub type RB_PWM10_OUT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_OUT_EN_SPEC, bool, O>;
+#[doc = "Field `RB_PWM11_OUT_EN` reader - RW, PWM11 output enable"]
+pub type RB_PWM11_OUT_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM11_OUT_EN` writer - RW, PWM11 output enable"]
+pub type RB_PWM11_OUT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_OUT_EN_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - RW, PWM4 output enable"]
+    #[inline(always)]
+    pub fn rb_pwm4_out_en(&self) -> RB_PWM4_OUT_EN_R {
+        RB_PWM4_OUT_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RW, PWM5 output enable"]
+    #[inline(always)]
+    pub fn rb_pwm5_out_en(&self) -> RB_PWM5_OUT_EN_R {
+        RB_PWM5_OUT_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RW, PWM6 output enable"]
+    #[inline(always)]
+    pub fn rb_pwm6_out_en(&self) -> RB_PWM6_OUT_EN_R {
+        RB_PWM6_OUT_EN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RW, PWM7 output enable"]
+    #[inline(always)]
+    pub fn rb_pwm7_out_en(&self) -> RB_PWM7_OUT_EN_R {
+        RB_PWM7_OUT_EN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RW, PWM8 output enable"]
+    #[inline(always)]
+    pub fn rb_pwm8_out_en(&self) -> RB_PWM8_OUT_EN_R {
+        RB_PWM8_OUT_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RW, PWM9 output enable"]
+    #[inline(always)]
+    pub fn rb_pwm9_out_en(&self) -> RB_PWM9_OUT_EN_R {
+        RB_PWM9_OUT_EN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RW, PWM10 output enable"]
+    #[inline(always)]
+    pub fn rb_pwm10_out_en(&self) -> RB_PWM10_OUT_EN_R {
+        RB_PWM10_OUT_EN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - RW, PWM11 output enable"]
+    #[inline(always)]
+    pub fn rb_pwm11_out_en(&self) -> RB_PWM11_OUT_EN_R {
+        RB_PWM11_OUT_EN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW, PWM4 output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm4_out_en(&mut self) -> RB_PWM4_OUT_EN_W<0> {
+        RB_PWM4_OUT_EN_W::new(self)
+    }
+    #[doc = "Bit 1 - RW, PWM5 output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm5_out_en(&mut self) -> RB_PWM5_OUT_EN_W<1> {
+        RB_PWM5_OUT_EN_W::new(self)
+    }
+    #[doc = "Bit 2 - RW, PWM6 output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm6_out_en(&mut self) -> RB_PWM6_OUT_EN_W<2> {
+        RB_PWM6_OUT_EN_W::new(self)
+    }
+    #[doc = "Bit 3 - RW, PWM7 output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm7_out_en(&mut self) -> RB_PWM7_OUT_EN_W<3> {
+        RB_PWM7_OUT_EN_W::new(self)
+    }
+    #[doc = "Bit 4 - RW, PWM8 output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm8_out_en(&mut self) -> RB_PWM8_OUT_EN_W<4> {
+        RB_PWM8_OUT_EN_W::new(self)
+    }
+    #[doc = "Bit 5 - RW, PWM9 output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm9_out_en(&mut self) -> RB_PWM9_OUT_EN_W<5> {
+        RB_PWM9_OUT_EN_W::new(self)
+    }
+    #[doc = "Bit 6 - RW, PWM10 output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm10_out_en(&mut self) -> RB_PWM10_OUT_EN_W<6> {
+        RB_PWM10_OUT_EN_W::new(self)
+    }
+    #[doc = "Bit 7 - RW, PWM11 output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm11_out_en(&mut self) -> RB_PWM11_OUT_EN_W<7> {
+        RB_PWM11_OUT_EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM output enable control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm_out_en](index.html) module"]
+pub struct R8_PWM_OUT_EN_SPEC;
+impl crate::RegisterSpec for R8_PWM_OUT_EN_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm_out_en::R](R) reader structure"]
+impl crate::Readable for R8_PWM_OUT_EN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm_out_en::W](W) writer structure"]
+impl crate::Writable for R8_PWM_OUT_EN_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM_OUT_EN to value 0"]
+impl crate::Resettable for R8_PWM_OUT_EN_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/pwmx/r8_pwm_polar.rs

@@ -0,0 +1,185 @@
+#[doc = "Register `R8_PWM_POLAR` reader"]
+pub struct R(crate::R<R8_PWM_POLAR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_PWM_POLAR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_PWM_POLAR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_PWM_POLAR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_PWM_POLAR` writer"]
+pub struct W(crate::W<R8_PWM_POLAR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_PWM_POLAR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_PWM_POLAR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_PWM_POLAR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_PWM4_POLAR` reader - RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM4_POLAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM4_POLAR` writer - RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM4_POLAR_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_POLAR_SPEC, bool, O>;
+#[doc = "Field `RB_PWM5_POLAR` reader - RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM5_POLAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM5_POLAR` writer - RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM5_POLAR_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_POLAR_SPEC, bool, O>;
+#[doc = "Field `RB_PWM6_POLAR` reader - RW, PWM6 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM6_POLAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM6_POLAR` writer - RW, PWM6 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM6_POLAR_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_POLAR_SPEC, bool, O>;
+#[doc = "Field `RB_PWM7_POLAR` reader - RW, PWM7 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM7_POLAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM7_POLAR` writer - RW, PWM7 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM7_POLAR_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_POLAR_SPEC, bool, O>;
+#[doc = "Field `RB_PWM8_POLAR` reader - RW, PWM8 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM8_POLAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM8_POLAR` writer - RW, PWM8 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM8_POLAR_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_POLAR_SPEC, bool, O>;
+#[doc = "Field `RB_PWM9_POLAR` reader - RW, PWM9 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM9_POLAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM9_POLAR` writer - RW, PWM9 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM9_POLAR_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_POLAR_SPEC, bool, O>;
+#[doc = "Field `RB_PWM10_POLAR` reader - RW, PWM10 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM10_POLAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM10_POLAR` writer - RW, PWM10 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM10_POLAR_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_POLAR_SPEC, bool, O>;
+#[doc = "Field `RB_PWM11_POLAR` reader - RW, PWM11 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM11_POLAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_PWM11_POLAR` writer - RW, PWM11 output polarity: 0=default low and high action, 1=default high and low action"]
+pub type RB_PWM11_POLAR_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_PWM_POLAR_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    pub fn rb_pwm4_polar(&self) -> RB_PWM4_POLAR_R {
+        RB_PWM4_POLAR_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    pub fn rb_pwm5_polar(&self) -> RB_PWM5_POLAR_R {
+        RB_PWM5_POLAR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RW, PWM6 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    pub fn rb_pwm6_polar(&self) -> RB_PWM6_POLAR_R {
+        RB_PWM6_POLAR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RW, PWM7 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    pub fn rb_pwm7_polar(&self) -> RB_PWM7_POLAR_R {
+        RB_PWM7_POLAR_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RW, PWM8 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    pub fn rb_pwm8_polar(&self) -> RB_PWM8_POLAR_R {
+        RB_PWM8_POLAR_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RW, PWM9 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    pub fn rb_pwm9_polar(&self) -> RB_PWM9_POLAR_R {
+        RB_PWM9_POLAR_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RW, PWM10 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    pub fn rb_pwm10_polar(&self) -> RB_PWM10_POLAR_R {
+        RB_PWM10_POLAR_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - RW, PWM11 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    pub fn rb_pwm11_polar(&self) -> RB_PWM11_POLAR_R {
+        RB_PWM11_POLAR_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm4_polar(&mut self) -> RB_PWM4_POLAR_W<0> {
+        RB_PWM4_POLAR_W::new(self)
+    }
+    #[doc = "Bit 1 - RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm5_polar(&mut self) -> RB_PWM5_POLAR_W<1> {
+        RB_PWM5_POLAR_W::new(self)
+    }
+    #[doc = "Bit 2 - RW, PWM6 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm6_polar(&mut self) -> RB_PWM6_POLAR_W<2> {
+        RB_PWM6_POLAR_W::new(self)
+    }
+    #[doc = "Bit 3 - RW, PWM7 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm7_polar(&mut self) -> RB_PWM7_POLAR_W<3> {
+        RB_PWM7_POLAR_W::new(self)
+    }
+    #[doc = "Bit 4 - RW, PWM8 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm8_polar(&mut self) -> RB_PWM8_POLAR_W<4> {
+        RB_PWM8_POLAR_W::new(self)
+    }
+    #[doc = "Bit 5 - RW, PWM9 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm9_polar(&mut self) -> RB_PWM9_POLAR_W<5> {
+        RB_PWM9_POLAR_W::new(self)
+    }
+    #[doc = "Bit 6 - RW, PWM10 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm10_polar(&mut self) -> RB_PWM10_POLAR_W<6> {
+        RB_PWM10_POLAR_W::new(self)
+    }
+    #[doc = "Bit 7 - RW, PWM11 output polarity: 0=default low and high action, 1=default high and low action"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_pwm11_polar(&mut self) -> RB_PWM11_POLAR_W<7> {
+        RB_PWM11_POLAR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, PWM output polarity control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_pwm_polar](index.html) module"]
+pub struct R8_PWM_POLAR_SPEC;
+impl crate::RegisterSpec for R8_PWM_POLAR_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_pwm_polar::R](R) reader structure"]
+impl crate::Readable for R8_PWM_POLAR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_pwm_polar::W](W) writer structure"]
+impl crate::Writable for R8_PWM_POLAR_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_PWM_POLAR to value 0"]
+impl crate::Resettable for R8_PWM_POLAR_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0.rs

@@ -0,0 +1,94 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - RW, SPI0 mode control"]
+    pub r8_spi0_ctrl_mod: R8_SPI0_CTRL_MOD,
+    #[doc = "0x01 - RW, SPI0 configuration control"]
+    pub r8_spi0_ctrl_cfg: R8_SPI0_CTRL_CFG,
+    #[doc = "0x02 - RW, SPI0 interrupt enable"]
+    pub r8_spi0_inter_en: R8_SPI0_INTER_EN,
+    #[doc = "0x03 - RW, SPI0 master clock divisor;RW, SPI0 slave preset value"]
+    pub r8_spi0_clock_div__r8_spi0_slave_pre: R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE,
+    #[doc = "0x04 - RW, SPI0 data buffer"]
+    pub r8_spi0_buffer: R8_SPI0_BUFFER,
+    #[doc = "0x05 - RO, SPI0 work flag"]
+    pub r8_spi0_run_flag: R8_SPI0_RUN_FLAG,
+    #[doc = "0x06 - RW1, SPI0 interrupt flag"]
+    pub r8_spi0_int_flag: R8_SPI0_INT_FLAG,
+    #[doc = "0x07 - RO, SPI0 FIFO count status"]
+    pub r8_spi0_fifo_count: R8_SPI0_FIFO_COUNT,
+    _reserved8: [u8; 0x04],
+    #[doc = "0x0c - RW, SPI0 total byte count, only low 12 bit"]
+    pub r16_spi0_total_cnt: R16_SPI0_TOTAL_CNT,
+    _reserved9: [u8; 0x02],
+    #[doc = "0x10 - RO/WO, SPI0 FIFO register"]
+    pub r8_spi0_fifo: R8_SPI0_FIFO,
+    _reserved10: [u8; 0x02],
+    #[doc = "0x13 - RO, SPI0 FIFO count status"]
+    pub r8_spi0_fifo_count1: R8_SPI0_FIFO_COUNT1,
+    #[doc = "0x14 - RW, SPI0 DMA current address"]
+    pub r16_spi0_dma_now: R16_SPI0_DMA_NOW,
+    _reserved12: [u8; 0x02],
+    #[doc = "0x18 - RW, SPI0 DMA begin address"]
+    pub r16_spi0_dma_beg: R16_SPI0_DMA_BEG,
+    _reserved13: [u8; 0x02],
+    #[doc = "0x1c - RW, SPI0 DMA end address"]
+    pub r16_spi0_dma_end: R16_SPI0_DMA_END,
+}
+#[doc = "R8_SPI0_CTRL_MOD (rw) register accessor: an alias for `Reg<R8_SPI0_CTRL_MOD_SPEC>`"]
+pub type R8_SPI0_CTRL_MOD = crate::Reg<r8_spi0_ctrl_mod::R8_SPI0_CTRL_MOD_SPEC>;
+#[doc = "RW, SPI0 mode control"]
+pub mod r8_spi0_ctrl_mod;
+#[doc = "R8_SPI0_CTRL_CFG (rw) register accessor: an alias for `Reg<R8_SPI0_CTRL_CFG_SPEC>`"]
+pub type R8_SPI0_CTRL_CFG = crate::Reg<r8_spi0_ctrl_cfg::R8_SPI0_CTRL_CFG_SPEC>;
+#[doc = "RW, SPI0 configuration control"]
+pub mod r8_spi0_ctrl_cfg;
+#[doc = "R8_SPI0_INTER_EN (rw) register accessor: an alias for `Reg<R8_SPI0_INTER_EN_SPEC>`"]
+pub type R8_SPI0_INTER_EN = crate::Reg<r8_spi0_inter_en::R8_SPI0_INTER_EN_SPEC>;
+#[doc = "RW, SPI0 interrupt enable"]
+pub mod r8_spi0_inter_en;
+#[doc = "R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE (rw) register accessor: an alias for `Reg<R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC>`"]
+pub type R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE =
+    crate::Reg<r8_spi0_clock_div__r8_spi0_slave_pre::R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC>;
+#[doc = "RW, SPI0 master clock divisor;RW, SPI0 slave preset value"]
+pub mod r8_spi0_clock_div__r8_spi0_slave_pre;
+#[doc = "R8_SPI0_BUFFER (rw) register accessor: an alias for `Reg<R8_SPI0_BUFFER_SPEC>`"]
+pub type R8_SPI0_BUFFER = crate::Reg<r8_spi0_buffer::R8_SPI0_BUFFER_SPEC>;
+#[doc = "RW, SPI0 data buffer"]
+pub mod r8_spi0_buffer;
+#[doc = "R8_SPI0_RUN_FLAG (r) register accessor: an alias for `Reg<R8_SPI0_RUN_FLAG_SPEC>`"]
+pub type R8_SPI0_RUN_FLAG = crate::Reg<r8_spi0_run_flag::R8_SPI0_RUN_FLAG_SPEC>;
+#[doc = "RO, SPI0 work flag"]
+pub mod r8_spi0_run_flag;
+#[doc = "R8_SPI0_INT_FLAG (rw) register accessor: an alias for `Reg<R8_SPI0_INT_FLAG_SPEC>`"]
+pub type R8_SPI0_INT_FLAG = crate::Reg<r8_spi0_int_flag::R8_SPI0_INT_FLAG_SPEC>;
+#[doc = "RW1, SPI0 interrupt flag"]
+pub mod r8_spi0_int_flag;
+#[doc = "R8_SPI0_FIFO_COUNT (r) register accessor: an alias for `Reg<R8_SPI0_FIFO_COUNT_SPEC>`"]
+pub type R8_SPI0_FIFO_COUNT = crate::Reg<r8_spi0_fifo_count::R8_SPI0_FIFO_COUNT_SPEC>;
+#[doc = "RO, SPI0 FIFO count status"]
+pub mod r8_spi0_fifo_count;
+#[doc = "R16_SPI0_TOTAL_CNT (rw) register accessor: an alias for `Reg<R16_SPI0_TOTAL_CNT_SPEC>`"]
+pub type R16_SPI0_TOTAL_CNT = crate::Reg<r16_spi0_total_cnt::R16_SPI0_TOTAL_CNT_SPEC>;
+#[doc = "RW, SPI0 total byte count, only low 12 bit"]
+pub mod r16_spi0_total_cnt;
+#[doc = "R8_SPI0_FIFO (rw) register accessor: an alias for `Reg<R8_SPI0_FIFO_SPEC>`"]
+pub type R8_SPI0_FIFO = crate::Reg<r8_spi0_fifo::R8_SPI0_FIFO_SPEC>;
+#[doc = "RO/WO, SPI0 FIFO register"]
+pub mod r8_spi0_fifo;
+#[doc = "R8_SPI0_FIFO_COUNT1 (r) register accessor: an alias for `Reg<R8_SPI0_FIFO_COUNT1_SPEC>`"]
+pub type R8_SPI0_FIFO_COUNT1 = crate::Reg<r8_spi0_fifo_count1::R8_SPI0_FIFO_COUNT1_SPEC>;
+#[doc = "RO, SPI0 FIFO count status"]
+pub mod r8_spi0_fifo_count1;
+#[doc = "R16_SPI0_DMA_NOW (rw) register accessor: an alias for `Reg<R16_SPI0_DMA_NOW_SPEC>`"]
+pub type R16_SPI0_DMA_NOW = crate::Reg<r16_spi0_dma_now::R16_SPI0_DMA_NOW_SPEC>;
+#[doc = "RW, SPI0 DMA current address"]
+pub mod r16_spi0_dma_now;
+#[doc = "R16_SPI0_DMA_BEG (rw) register accessor: an alias for `Reg<R16_SPI0_DMA_BEG_SPEC>`"]
+pub type R16_SPI0_DMA_BEG = crate::Reg<r16_spi0_dma_beg::R16_SPI0_DMA_BEG_SPEC>;
+#[doc = "RW, SPI0 DMA begin address"]
+pub mod r16_spi0_dma_beg;
+#[doc = "R16_SPI0_DMA_END (rw) register accessor: an alias for `Reg<R16_SPI0_DMA_END_SPEC>`"]
+pub type R16_SPI0_DMA_END = crate::Reg<r16_spi0_dma_end::R16_SPI0_DMA_END_SPEC>;
+#[doc = "RW, SPI0 DMA end address"]
+pub mod r16_spi0_dma_end;

src/spi0/r16_spi0_dma_beg.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_SPI0_DMA_BEG` reader"]
+pub struct R(crate::R<R16_SPI0_DMA_BEG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_SPI0_DMA_BEG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_SPI0_DMA_BEG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_SPI0_DMA_BEG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_SPI0_DMA_BEG` writer"]
+pub struct W(crate::W<R16_SPI0_DMA_BEG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_SPI0_DMA_BEG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_SPI0_DMA_BEG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_SPI0_DMA_BEG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI0 DMA begin address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_spi0_dma_beg](index.html) module"]
+pub struct R16_SPI0_DMA_BEG_SPEC;
+impl crate::RegisterSpec for R16_SPI0_DMA_BEG_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_spi0_dma_beg::R](R) reader structure"]
+impl crate::Readable for R16_SPI0_DMA_BEG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_spi0_dma_beg::W](W) writer structure"]
+impl crate::Writable for R16_SPI0_DMA_BEG_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_SPI0_DMA_BEG to value 0"]
+impl crate::Resettable for R16_SPI0_DMA_BEG_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r16_spi0_dma_end.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_SPI0_DMA_END` reader"]
+pub struct R(crate::R<R16_SPI0_DMA_END_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_SPI0_DMA_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_SPI0_DMA_END_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_SPI0_DMA_END_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_SPI0_DMA_END` writer"]
+pub struct W(crate::W<R16_SPI0_DMA_END_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_SPI0_DMA_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_SPI0_DMA_END_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_SPI0_DMA_END_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI0 DMA end address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_spi0_dma_end](index.html) module"]
+pub struct R16_SPI0_DMA_END_SPEC;
+impl crate::RegisterSpec for R16_SPI0_DMA_END_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_spi0_dma_end::R](R) reader structure"]
+impl crate::Readable for R16_SPI0_DMA_END_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_spi0_dma_end::W](W) writer structure"]
+impl crate::Writable for R16_SPI0_DMA_END_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_SPI0_DMA_END to value 0"]
+impl crate::Resettable for R16_SPI0_DMA_END_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r16_spi0_dma_now.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_SPI0_DMA_NOW` reader"]
+pub struct R(crate::R<R16_SPI0_DMA_NOW_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_SPI0_DMA_NOW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_SPI0_DMA_NOW_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_SPI0_DMA_NOW_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_SPI0_DMA_NOW` writer"]
+pub struct W(crate::W<R16_SPI0_DMA_NOW_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_SPI0_DMA_NOW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_SPI0_DMA_NOW_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_SPI0_DMA_NOW_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI0 DMA current address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_spi0_dma_now](index.html) module"]
+pub struct R16_SPI0_DMA_NOW_SPEC;
+impl crate::RegisterSpec for R16_SPI0_DMA_NOW_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_spi0_dma_now::R](R) reader structure"]
+impl crate::Readable for R16_SPI0_DMA_NOW_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_spi0_dma_now::W](W) writer structure"]
+impl crate::Writable for R16_SPI0_DMA_NOW_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_SPI0_DMA_NOW to value 0"]
+impl crate::Resettable for R16_SPI0_DMA_NOW_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r16_spi0_total_cnt.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_SPI0_TOTAL_CNT` reader"]
+pub struct R(crate::R<R16_SPI0_TOTAL_CNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_SPI0_TOTAL_CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_SPI0_TOTAL_CNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_SPI0_TOTAL_CNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_SPI0_TOTAL_CNT` writer"]
+pub struct W(crate::W<R16_SPI0_TOTAL_CNT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_SPI0_TOTAL_CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_SPI0_TOTAL_CNT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_SPI0_TOTAL_CNT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI0 total byte count, only low 12 bit\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_spi0_total_cnt](index.html) module"]
+pub struct R16_SPI0_TOTAL_CNT_SPEC;
+impl crate::RegisterSpec for R16_SPI0_TOTAL_CNT_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_spi0_total_cnt::R](R) reader structure"]
+impl crate::Readable for R16_SPI0_TOTAL_CNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_spi0_total_cnt::W](W) writer structure"]
+impl crate::Writable for R16_SPI0_TOTAL_CNT_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_SPI0_TOTAL_CNT to value 0"]
+impl crate::Resettable for R16_SPI0_TOTAL_CNT_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r8_spi0_buffer.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_SPI0_BUFFER` reader"]
+pub struct R(crate::R<R8_SPI0_BUFFER_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI0_BUFFER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI0_BUFFER_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI0_BUFFER_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI0_BUFFER` writer"]
+pub struct W(crate::W<R8_SPI0_BUFFER_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI0_BUFFER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI0_BUFFER_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI0_BUFFER_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI0 data buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi0_buffer](index.html) module"]
+pub struct R8_SPI0_BUFFER_SPEC;
+impl crate::RegisterSpec for R8_SPI0_BUFFER_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi0_buffer::R](R) reader structure"]
+impl crate::Readable for R8_SPI0_BUFFER_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi0_buffer::W](W) writer structure"]
+impl crate::Writable for R8_SPI0_BUFFER_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI0_BUFFER to value 0"]
+impl crate::Resettable for R8_SPI0_BUFFER_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r8_spi0_clock_div__r8_spi0_slave_pre.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE` reader"]
+pub struct R(crate::R<R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE` writer"]
+pub struct W(crate::W<R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI0 master clock divisor;RW, SPI0 slave preset value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi0_clock_div__r8_spi0_slave_pre](index.html) module"]
+pub struct R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC;
+impl crate::RegisterSpec for R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi0_clock_div__r8_spi0_slave_pre::R](R) reader structure"]
+impl crate::Readable for R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi0_clock_div__r8_spi0_slave_pre::W](W) writer structure"]
+impl crate::Writable for R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE to value 0"]
+impl crate::Resettable for R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r8_spi0_ctrl_cfg.rs

@@ -0,0 +1,145 @@
+#[doc = "Register `R8_SPI0_CTRL_CFG` reader"]
+pub struct R(crate::R<R8_SPI0_CTRL_CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI0_CTRL_CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI0_CTRL_CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI0_CTRL_CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI0_CTRL_CFG` writer"]
+pub struct W(crate::W<R8_SPI0_CTRL_CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI0_CTRL_CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI0_CTRL_CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI0_CTRL_CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_SPI_DMA_ENABLE` reader - RW, SPI0 DMA enable"]
+pub type RB_SPI_DMA_ENABLE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_DMA_ENABLE` writer - RW, SPI0 DMA enable"]
+pub type RB_SPI_DMA_ENABLE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_CFG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_DMA_LOOP` reader - RW, SPI0 DMA address loop enable"]
+pub type RB_SPI_DMA_LOOP_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_DMA_LOOP` writer - RW, SPI0 DMA address loop enable"]
+pub type RB_SPI_DMA_LOOP_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_CFG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_AUTO_IF` reader - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
+pub type RB_SPI_AUTO_IF_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_AUTO_IF` writer - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
+pub type RB_SPI_AUTO_IF_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_CFG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_BIT_ORDER` reader - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
+pub type RB_SPI_BIT_ORDER_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_BIT_ORDER` writer - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
+pub type RB_SPI_BIT_ORDER_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_CFG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_MST_DLY_EN` reader - RW, SPI master input delay enable"]
+pub type RB_SPI_MST_DLY_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_MST_DLY_EN` writer - RW, SPI master input delay enable"]
+pub type RB_SPI_MST_DLY_EN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_CFG_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - RW, SPI0 DMA enable"]
+    #[inline(always)]
+    pub fn rb_spi_dma_enable(&self) -> RB_SPI_DMA_ENABLE_R {
+        RB_SPI_DMA_ENABLE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 2 - RW, SPI0 DMA address loop enable"]
+    #[inline(always)]
+    pub fn rb_spi_dma_loop(&self) -> RB_SPI_DMA_LOOP_R {
+        RB_SPI_DMA_LOOP_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
+    #[inline(always)]
+    pub fn rb_spi_auto_if(&self) -> RB_SPI_AUTO_IF_R {
+        RB_SPI_AUTO_IF_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
+    #[inline(always)]
+    pub fn rb_spi_bit_order(&self) -> RB_SPI_BIT_ORDER_R {
+        RB_SPI_BIT_ORDER_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RW, SPI master input delay enable"]
+    #[inline(always)]
+    pub fn rb_spi_mst_dly_en(&self) -> RB_SPI_MST_DLY_EN_R {
+        RB_SPI_MST_DLY_EN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW, SPI0 DMA enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_dma_enable(&mut self) -> RB_SPI_DMA_ENABLE_W<0> {
+        RB_SPI_DMA_ENABLE_W::new(self)
+    }
+    #[doc = "Bit 2 - RW, SPI0 DMA address loop enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_dma_loop(&mut self) -> RB_SPI_DMA_LOOP_W<2> {
+        RB_SPI_DMA_LOOP_W::new(self)
+    }
+    #[doc = "Bit 4 - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_auto_if(&mut self) -> RB_SPI_AUTO_IF_W<4> {
+        RB_SPI_AUTO_IF_W::new(self)
+    }
+    #[doc = "Bit 5 - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_bit_order(&mut self) -> RB_SPI_BIT_ORDER_W<5> {
+        RB_SPI_BIT_ORDER_W::new(self)
+    }
+    #[doc = "Bit 6 - RW, SPI master input delay enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_mst_dly_en(&mut self) -> RB_SPI_MST_DLY_EN_W<6> {
+        RB_SPI_MST_DLY_EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI0 configuration control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi0_ctrl_cfg](index.html) module"]
+pub struct R8_SPI0_CTRL_CFG_SPEC;
+impl crate::RegisterSpec for R8_SPI0_CTRL_CFG_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi0_ctrl_cfg::R](R) reader structure"]
+impl crate::Readable for R8_SPI0_CTRL_CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi0_ctrl_cfg::W](W) writer structure"]
+impl crate::Writable for R8_SPI0_CTRL_CFG_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI0_CTRL_CFG to value 0"]
+impl crate::Resettable for R8_SPI0_CTRL_CFG_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r8_spi0_ctrl_mod.rs

@@ -0,0 +1,197 @@
+#[doc = "Register `R8_SPI0_CTRL_MOD` reader"]
+pub struct R(crate::R<R8_SPI0_CTRL_MOD_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI0_CTRL_MOD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI0_CTRL_MOD_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI0_CTRL_MOD_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI0_CTRL_MOD` writer"]
+pub struct W(crate::W<R8_SPI0_CTRL_MOD_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI0_CTRL_MOD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI0_CTRL_MOD_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI0_CTRL_MOD_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_SPI_MODE_SLAVE` reader - RW, SPI0 slave mode: 0=master/host, 1=slave/device"]
+pub type RB_SPI_MODE_SLAVE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_MODE_SLAVE` writer - RW, SPI0 slave mode: 0=master/host, 1=slave/device"]
+pub type RB_SPI_MODE_SLAVE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_ALL_CLEAR` reader - RW, force clear SPI FIFO and count"]
+pub type RB_SPI_ALL_CLEAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_ALL_CLEAR` writer - RW, force clear SPI FIFO and count"]
+pub type RB_SPI_ALL_CLEAR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_2WIRE_MOD` reader - RW, SPI0 enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX)"]
+pub type RB_SPI_2WIRE_MOD_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_2WIRE_MOD` writer - RW, SPI0 enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX)"]
+pub type RB_SPI_2WIRE_MOD_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD` reader - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI0 slave command mode: 0=byte stream, 1=first byte command"]
+pub type RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD` writer - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI0 slave command mode: 0=byte stream, 1=first byte command"]
+pub type RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_FIFO_DIR` reader - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
+pub type RB_SPI_FIFO_DIR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_FIFO_DIR` writer - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
+pub type RB_SPI_FIFO_DIR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_SCK_OE` reader - RW, SPI SCK output enable"]
+pub type RB_SPI_SCK_OE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_SCK_OE` writer - RW, SPI SCK output enable"]
+pub type RB_SPI_SCK_OE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_MOSI_OE` reader - RW, SPI MOSI output enable"]
+pub type RB_SPI_MOSI_OE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_MOSI_OE` writer - RW, SPI MOSI output enable"]
+pub type RB_SPI_MOSI_OE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_MISO_OE` reader - RW, SPI MISO output enable"]
+pub type RB_SPI_MISO_OE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_MISO_OE` writer - RW, SPI MISO output enable"]
+pub type RB_SPI_MISO_OE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_CTRL_MOD_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - RW, SPI0 slave mode: 0=master/host, 1=slave/device"]
+    #[inline(always)]
+    pub fn rb_spi_mode_slave(&self) -> RB_SPI_MODE_SLAVE_R {
+        RB_SPI_MODE_SLAVE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RW, force clear SPI FIFO and count"]
+    #[inline(always)]
+    pub fn rb_spi_all_clear(&self) -> RB_SPI_ALL_CLEAR_R {
+        RB_SPI_ALL_CLEAR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RW, SPI0 enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX)"]
+    #[inline(always)]
+    pub fn rb_spi_2wire_mod(&self) -> RB_SPI_2WIRE_MOD_R {
+        RB_SPI_2WIRE_MOD_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI0 slave command mode: 0=byte stream, 1=first byte command"]
+    #[inline(always)]
+    pub fn rb_spi_mst_sck_mod__rb_spi_slv_cmd_mod(
+        &self,
+    ) -> RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_R {
+        RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
+    #[inline(always)]
+    pub fn rb_spi_fifo_dir(&self) -> RB_SPI_FIFO_DIR_R {
+        RB_SPI_FIFO_DIR_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RW, SPI SCK output enable"]
+    #[inline(always)]
+    pub fn rb_spi_sck_oe(&self) -> RB_SPI_SCK_OE_R {
+        RB_SPI_SCK_OE_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RW, SPI MOSI output enable"]
+    #[inline(always)]
+    pub fn rb_spi_mosi_oe(&self) -> RB_SPI_MOSI_OE_R {
+        RB_SPI_MOSI_OE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - RW, SPI MISO output enable"]
+    #[inline(always)]
+    pub fn rb_spi_miso_oe(&self) -> RB_SPI_MISO_OE_R {
+        RB_SPI_MISO_OE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW, SPI0 slave mode: 0=master/host, 1=slave/device"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_mode_slave(&mut self) -> RB_SPI_MODE_SLAVE_W<0> {
+        RB_SPI_MODE_SLAVE_W::new(self)
+    }
+    #[doc = "Bit 1 - RW, force clear SPI FIFO and count"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_all_clear(&mut self) -> RB_SPI_ALL_CLEAR_W<1> {
+        RB_SPI_ALL_CLEAR_W::new(self)
+    }
+    #[doc = "Bit 2 - RW, SPI0 enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_2wire_mod(&mut self) -> RB_SPI_2WIRE_MOD_W<2> {
+        RB_SPI_2WIRE_MOD_W::new(self)
+    }
+    #[doc = "Bit 3 - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI0 slave command mode: 0=byte stream, 1=first byte command"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_mst_sck_mod__rb_spi_slv_cmd_mod(
+        &mut self,
+    ) -> RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_W<3> {
+        RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_W::new(self)
+    }
+    #[doc = "Bit 4 - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_fifo_dir(&mut self) -> RB_SPI_FIFO_DIR_W<4> {
+        RB_SPI_FIFO_DIR_W::new(self)
+    }
+    #[doc = "Bit 5 - RW, SPI SCK output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_sck_oe(&mut self) -> RB_SPI_SCK_OE_W<5> {
+        RB_SPI_SCK_OE_W::new(self)
+    }
+    #[doc = "Bit 6 - RW, SPI MOSI output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_mosi_oe(&mut self) -> RB_SPI_MOSI_OE_W<6> {
+        RB_SPI_MOSI_OE_W::new(self)
+    }
+    #[doc = "Bit 7 - RW, SPI MISO output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_miso_oe(&mut self) -> RB_SPI_MISO_OE_W<7> {
+        RB_SPI_MISO_OE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI0 mode control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi0_ctrl_mod](index.html) module"]
+pub struct R8_SPI0_CTRL_MOD_SPEC;
+impl crate::RegisterSpec for R8_SPI0_CTRL_MOD_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi0_ctrl_mod::R](R) reader structure"]
+impl crate::Readable for R8_SPI0_CTRL_MOD_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi0_ctrl_mod::W](W) writer structure"]
+impl crate::Writable for R8_SPI0_CTRL_MOD_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI0_CTRL_MOD to value 0"]
+impl crate::Resettable for R8_SPI0_CTRL_MOD_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r8_spi0_fifo.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_SPI0_FIFO` reader"]
+pub struct R(crate::R<R8_SPI0_FIFO_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI0_FIFO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI0_FIFO_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI0_FIFO_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI0_FIFO` writer"]
+pub struct W(crate::W<R8_SPI0_FIFO_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI0_FIFO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI0_FIFO_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI0_FIFO_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RO/WO, SPI0 FIFO register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi0_fifo](index.html) module"]
+pub struct R8_SPI0_FIFO_SPEC;
+impl crate::RegisterSpec for R8_SPI0_FIFO_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi0_fifo::R](R) reader structure"]
+impl crate::Readable for R8_SPI0_FIFO_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi0_fifo::W](W) writer structure"]
+impl crate::Writable for R8_SPI0_FIFO_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI0_FIFO to value 0"]
+impl crate::Resettable for R8_SPI0_FIFO_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r8_spi0_fifo_count.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `R8_SPI0_FIFO_COUNT` reader"]
+pub struct R(crate::R<R8_SPI0_FIFO_COUNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI0_FIFO_COUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI0_FIFO_COUNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI0_FIFO_COUNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "RO, SPI0 FIFO count status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi0_fifo_count](index.html) module"]
+pub struct R8_SPI0_FIFO_COUNT_SPEC;
+impl crate::RegisterSpec for R8_SPI0_FIFO_COUNT_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi0_fifo_count::R](R) reader structure"]
+impl crate::Readable for R8_SPI0_FIFO_COUNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets R8_SPI0_FIFO_COUNT to value 0"]
+impl crate::Resettable for R8_SPI0_FIFO_COUNT_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r8_spi0_fifo_count1.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `R8_SPI0_FIFO_COUNT1` reader"]
+pub struct R(crate::R<R8_SPI0_FIFO_COUNT1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI0_FIFO_COUNT1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI0_FIFO_COUNT1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI0_FIFO_COUNT1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "RO, SPI0 FIFO count status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi0_fifo_count1](index.html) module"]
+pub struct R8_SPI0_FIFO_COUNT1_SPEC;
+impl crate::RegisterSpec for R8_SPI0_FIFO_COUNT1_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi0_fifo_count1::R](R) reader structure"]
+impl crate::Readable for R8_SPI0_FIFO_COUNT1_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets R8_SPI0_FIFO_COUNT1 to value 0"]
+impl crate::Resettable for R8_SPI0_FIFO_COUNT1_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r8_spi0_int_flag.rs

@@ -0,0 +1,176 @@
+#[doc = "Register `R8_SPI0_INT_FLAG` reader"]
+pub struct R(crate::R<R8_SPI0_INT_FLAG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI0_INT_FLAG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI0_INT_FLAG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI0_INT_FLAG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI0_INT_FLAG` writer"]
+pub struct W(crate::W<R8_SPI0_INT_FLAG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI0_INT_FLAG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI0_INT_FLAG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI0_INT_FLAG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_SPI_IF_CNT_END` reader - RW1, interrupt flag for SPI total byte count end"]
+pub type RB_SPI_IF_CNT_END_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IF_CNT_END` writer - RW1, interrupt flag for SPI total byte count end"]
+pub type RB_SPI_IF_CNT_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INT_FLAG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IF_BYTE_END` reader - RW1, interrupt flag for SPI byte exchanged"]
+pub type RB_SPI_IF_BYTE_END_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IF_BYTE_END` writer - RW1, interrupt flag for SPI byte exchanged"]
+pub type RB_SPI_IF_BYTE_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INT_FLAG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IF_FIFO_HF` reader - RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : less than 4bytes)"]
+pub type RB_SPI_IF_FIFO_HF_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IF_FIFO_HF` writer - RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : less than 4bytes)"]
+pub type RB_SPI_IF_FIFO_HF_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INT_FLAG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IF_DMA_END` reader - RW1, interrupt flag for SPI0 DMA completion"]
+pub type RB_SPI_IF_DMA_END_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IF_DMA_END` writer - RW1, interrupt flag for SPI0 DMA completion"]
+pub type RB_SPI_IF_DMA_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INT_FLAG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IF_FIFO_OV` reader - RW1, interrupt flag for SPI0 FIFO overflow"]
+pub type RB_SPI_IF_FIFO_OV_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IF_FIFO_OV` writer - RW1, interrupt flag for SPI0 FIFO overflow"]
+pub type RB_SPI_IF_FIFO_OV_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INT_FLAG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_FREE` reader - RO, current SPI free status"]
+pub type RB_SPI_FREE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_FREE` writer - RO, current SPI free status"]
+pub type RB_SPI_FREE_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_SPI0_INT_FLAG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IF_FST_BYTE` reader - RW1, interrupt flag for SPI0 slave mode first byte received"]
+pub type RB_SPI_IF_FST_BYTE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IF_FST_BYTE` writer - RW1, interrupt flag for SPI0 slave mode first byte received"]
+pub type RB_SPI_IF_FST_BYTE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INT_FLAG_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - RW1, interrupt flag for SPI total byte count end"]
+    #[inline(always)]
+    pub fn rb_spi_if_cnt_end(&self) -> RB_SPI_IF_CNT_END_R {
+        RB_SPI_IF_CNT_END_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RW1, interrupt flag for SPI byte exchanged"]
+    #[inline(always)]
+    pub fn rb_spi_if_byte_end(&self) -> RB_SPI_IF_BYTE_END_R {
+        RB_SPI_IF_BYTE_END_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : less than 4bytes)"]
+    #[inline(always)]
+    pub fn rb_spi_if_fifo_hf(&self) -> RB_SPI_IF_FIFO_HF_R {
+        RB_SPI_IF_FIFO_HF_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RW1, interrupt flag for SPI0 DMA completion"]
+    #[inline(always)]
+    pub fn rb_spi_if_dma_end(&self) -> RB_SPI_IF_DMA_END_R {
+        RB_SPI_IF_DMA_END_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RW1, interrupt flag for SPI0 FIFO overflow"]
+    #[inline(always)]
+    pub fn rb_spi_if_fifo_ov(&self) -> RB_SPI_IF_FIFO_OV_R {
+        RB_SPI_IF_FIFO_OV_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RO, current SPI free status"]
+    #[inline(always)]
+    pub fn rb_spi_free(&self) -> RB_SPI_FREE_R {
+        RB_SPI_FREE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - RW1, interrupt flag for SPI0 slave mode first byte received"]
+    #[inline(always)]
+    pub fn rb_spi_if_fst_byte(&self) -> RB_SPI_IF_FST_BYTE_R {
+        RB_SPI_IF_FST_BYTE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW1, interrupt flag for SPI total byte count end"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_if_cnt_end(&mut self) -> RB_SPI_IF_CNT_END_W<0> {
+        RB_SPI_IF_CNT_END_W::new(self)
+    }
+    #[doc = "Bit 1 - RW1, interrupt flag for SPI byte exchanged"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_if_byte_end(&mut self) -> RB_SPI_IF_BYTE_END_W<1> {
+        RB_SPI_IF_BYTE_END_W::new(self)
+    }
+    #[doc = "Bit 2 - RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : less than 4bytes)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_if_fifo_hf(&mut self) -> RB_SPI_IF_FIFO_HF_W<2> {
+        RB_SPI_IF_FIFO_HF_W::new(self)
+    }
+    #[doc = "Bit 3 - RW1, interrupt flag for SPI0 DMA completion"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_if_dma_end(&mut self) -> RB_SPI_IF_DMA_END_W<3> {
+        RB_SPI_IF_DMA_END_W::new(self)
+    }
+    #[doc = "Bit 4 - RW1, interrupt flag for SPI0 FIFO overflow"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_if_fifo_ov(&mut self) -> RB_SPI_IF_FIFO_OV_W<4> {
+        RB_SPI_IF_FIFO_OV_W::new(self)
+    }
+    #[doc = "Bit 6 - RO, current SPI free status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_free(&mut self) -> RB_SPI_FREE_W<6> {
+        RB_SPI_FREE_W::new(self)
+    }
+    #[doc = "Bit 7 - RW1, interrupt flag for SPI0 slave mode first byte received"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_if_fst_byte(&mut self) -> RB_SPI_IF_FST_BYTE_W<7> {
+        RB_SPI_IF_FST_BYTE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW1, SPI0 interrupt flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi0_int_flag](index.html) module"]
+pub struct R8_SPI0_INT_FLAG_SPEC;
+impl crate::RegisterSpec for R8_SPI0_INT_FLAG_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi0_int_flag::R](R) reader structure"]
+impl crate::Readable for R8_SPI0_INT_FLAG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi0_int_flag::W](W) writer structure"]
+impl crate::Writable for R8_SPI0_INT_FLAG_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI0_INT_FLAG to value 0"]
+impl crate::Resettable for R8_SPI0_INT_FLAG_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r8_spi0_inter_en.rs

@@ -0,0 +1,161 @@
+#[doc = "Register `R8_SPI0_INTER_EN` reader"]
+pub struct R(crate::R<R8_SPI0_INTER_EN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI0_INTER_EN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI0_INTER_EN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI0_INTER_EN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI0_INTER_EN` writer"]
+pub struct W(crate::W<R8_SPI0_INTER_EN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI0_INTER_EN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI0_INTER_EN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI0_INTER_EN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_SPI_IE_CNT_END` reader - RW, enable interrupt for SPI total byte count end"]
+pub type RB_SPI_IE_CNT_END_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IE_CNT_END` writer - RW, enable interrupt for SPI total byte count end"]
+pub type RB_SPI_IE_CNT_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INTER_EN_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IE_BYTE_END` reader - RW, enable interrupt for SPI byte exchanged"]
+pub type RB_SPI_IE_BYTE_END_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IE_BYTE_END` writer - RW, enable interrupt for SPI byte exchanged"]
+pub type RB_SPI_IE_BYTE_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INTER_EN_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IE_FIFO_HF` reader - RW, enable interrupt for SPI FIFO half"]
+pub type RB_SPI_IE_FIFO_HF_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IE_FIFO_HF` writer - RW, enable interrupt for SPI FIFO half"]
+pub type RB_SPI_IE_FIFO_HF_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INTER_EN_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IE_DMA_END` reader - RW, enable interrupt for SPI0 DMA completion"]
+pub type RB_SPI_IE_DMA_END_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IE_DMA_END` writer - RW, enable interrupt for SPI0 DMA completion"]
+pub type RB_SPI_IE_DMA_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INTER_EN_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IE_FIFO_OV` reader - RW, enable interrupt for SPI0 FIFO overflow"]
+pub type RB_SPI_IE_FIFO_OV_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IE_FIFO_OV` writer - RW, enable interrupt for SPI0 FIFO overflow"]
+pub type RB_SPI_IE_FIFO_OV_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INTER_EN_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IE_FST_BYTE` reader - RW, enable interrupt for SPI0 slave mode first byte received"]
+pub type RB_SPI_IE_FST_BYTE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IE_FST_BYTE` writer - RW, enable interrupt for SPI0 slave mode first byte received"]
+pub type RB_SPI_IE_FST_BYTE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI0_INTER_EN_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - RW, enable interrupt for SPI total byte count end"]
+    #[inline(always)]
+    pub fn rb_spi_ie_cnt_end(&self) -> RB_SPI_IE_CNT_END_R {
+        RB_SPI_IE_CNT_END_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RW, enable interrupt for SPI byte exchanged"]
+    #[inline(always)]
+    pub fn rb_spi_ie_byte_end(&self) -> RB_SPI_IE_BYTE_END_R {
+        RB_SPI_IE_BYTE_END_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RW, enable interrupt for SPI FIFO half"]
+    #[inline(always)]
+    pub fn rb_spi_ie_fifo_hf(&self) -> RB_SPI_IE_FIFO_HF_R {
+        RB_SPI_IE_FIFO_HF_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RW, enable interrupt for SPI0 DMA completion"]
+    #[inline(always)]
+    pub fn rb_spi_ie_dma_end(&self) -> RB_SPI_IE_DMA_END_R {
+        RB_SPI_IE_DMA_END_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RW, enable interrupt for SPI0 FIFO overflow"]
+    #[inline(always)]
+    pub fn rb_spi_ie_fifo_ov(&self) -> RB_SPI_IE_FIFO_OV_R {
+        RB_SPI_IE_FIFO_OV_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 7 - RW, enable interrupt for SPI0 slave mode first byte received"]
+    #[inline(always)]
+    pub fn rb_spi_ie_fst_byte(&self) -> RB_SPI_IE_FST_BYTE_R {
+        RB_SPI_IE_FST_BYTE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW, enable interrupt for SPI total byte count end"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_ie_cnt_end(&mut self) -> RB_SPI_IE_CNT_END_W<0> {
+        RB_SPI_IE_CNT_END_W::new(self)
+    }
+    #[doc = "Bit 1 - RW, enable interrupt for SPI byte exchanged"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_ie_byte_end(&mut self) -> RB_SPI_IE_BYTE_END_W<1> {
+        RB_SPI_IE_BYTE_END_W::new(self)
+    }
+    #[doc = "Bit 2 - RW, enable interrupt for SPI FIFO half"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_ie_fifo_hf(&mut self) -> RB_SPI_IE_FIFO_HF_W<2> {
+        RB_SPI_IE_FIFO_HF_W::new(self)
+    }
+    #[doc = "Bit 3 - RW, enable interrupt for SPI0 DMA completion"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_ie_dma_end(&mut self) -> RB_SPI_IE_DMA_END_W<3> {
+        RB_SPI_IE_DMA_END_W::new(self)
+    }
+    #[doc = "Bit 4 - RW, enable interrupt for SPI0 FIFO overflow"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_ie_fifo_ov(&mut self) -> RB_SPI_IE_FIFO_OV_W<4> {
+        RB_SPI_IE_FIFO_OV_W::new(self)
+    }
+    #[doc = "Bit 7 - RW, enable interrupt for SPI0 slave mode first byte received"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_ie_fst_byte(&mut self) -> RB_SPI_IE_FST_BYTE_W<7> {
+        RB_SPI_IE_FST_BYTE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI0 interrupt enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi0_inter_en](index.html) module"]
+pub struct R8_SPI0_INTER_EN_SPEC;
+impl crate::RegisterSpec for R8_SPI0_INTER_EN_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi0_inter_en::R](R) reader structure"]
+impl crate::Readable for R8_SPI0_INTER_EN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi0_inter_en::W](W) writer structure"]
+impl crate::Writable for R8_SPI0_INTER_EN_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI0_INTER_EN to value 0"]
+impl crate::Resettable for R8_SPI0_INTER_EN_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi0/r8_spi0_run_flag.rs

@@ -0,0 +1,58 @@
+#[doc = "Register `R8_SPI0_RUN_FLAG` reader"]
+pub struct R(crate::R<R8_SPI0_RUN_FLAG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI0_RUN_FLAG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI0_RUN_FLAG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI0_RUN_FLAG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `RB_SPI_SLV_CMD_ACT` reader - RO, SPI0 slave first byte / command flag"]
+pub type RB_SPI_SLV_CMD_ACT_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_FIFO_READY` reader - RO, SPI FIFO ready status"]
+pub type RB_SPI_FIFO_READY_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_SLV_CS_LOAD` reader - RO, SPI0 slave chip-select loading status"]
+pub type RB_SPI_SLV_CS_LOAD_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_SLV_SELECT` reader - RO, SPI0 slave selection status"]
+pub type RB_SPI_SLV_SELECT_R = crate::BitReader<bool>;
+impl R {
+    #[doc = "Bit 4 - RO, SPI0 slave first byte / command flag"]
+    #[inline(always)]
+    pub fn rb_spi_slv_cmd_act(&self) -> RB_SPI_SLV_CMD_ACT_R {
+        RB_SPI_SLV_CMD_ACT_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RO, SPI FIFO ready status"]
+    #[inline(always)]
+    pub fn rb_spi_fifo_ready(&self) -> RB_SPI_FIFO_READY_R {
+        RB_SPI_FIFO_READY_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RO, SPI0 slave chip-select loading status"]
+    #[inline(always)]
+    pub fn rb_spi_slv_cs_load(&self) -> RB_SPI_SLV_CS_LOAD_R {
+        RB_SPI_SLV_CS_LOAD_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - RO, SPI0 slave selection status"]
+    #[inline(always)]
+    pub fn rb_spi_slv_select(&self) -> RB_SPI_SLV_SELECT_R {
+        RB_SPI_SLV_SELECT_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[doc = "RO, SPI0 work flag\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi0_run_flag](index.html) module"]
+pub struct R8_SPI0_RUN_FLAG_SPEC;
+impl crate::RegisterSpec for R8_SPI0_RUN_FLAG_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi0_run_flag::R](R) reader structure"]
+impl crate::Readable for R8_SPI0_RUN_FLAG_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets R8_SPI0_RUN_FLAG to value 0"]
+impl crate::Resettable for R8_SPI0_RUN_FLAG_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi1.rs

@@ -0,0 +1,73 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - RW, SPI1 mode control"]
+    pub r8_spi1_ctrl_mod: R8_SPI1_CTRL_MOD,
+    #[doc = "0x01 - RW, SPI1 configuration control"]
+    pub r8_spi1_ctrl_cfg: R8_SPI1_CTRL_CFG,
+    #[doc = "0x02 - RW, SPI1 interrupt enable"]
+    pub r8_spi1_inter_en: R8_SPI1_INTER_EN,
+    #[doc = "0x03 - RW, SPI1 master clock divisor"]
+    pub r8_spi1_clock_div: R8_SPI1_CLOCK_DIV,
+    #[doc = "0x04 - RW, SPI1 data buffer"]
+    pub r8_spi1_buffer: R8_SPI1_BUFFER,
+    #[doc = "0x05 - RO, SPI1 work flag"]
+    pub r8_spi1_run_flag: R8_SPI1_RUN_FLAG,
+    #[doc = "0x06 - RW1, SPI1 interrupt flag"]
+    pub r8_spi1_int_flag: R8_SPI1_INT_FLAG,
+    #[doc = "0x07 - RO, SPI1 FIFO count status"]
+    pub r8_spi1_fifo_count: R8_SPI1_FIFO_COUNT,
+    _reserved8: [u8; 0x04],
+    #[doc = "0x0c - RW, SPI1 total byte count, only low 12 bit"]
+    pub r16_spi1_total_cnt: R16_SPI1_TOTAL_CNT,
+    _reserved9: [u8; 0x02],
+    #[doc = "0x10 - RO/WO, SPI1 FIFO register"]
+    pub r8_spi1_fifo: R8_SPI1_FIFO,
+    _reserved10: [u8; 0x02],
+    #[doc = "0x13 - RO, SPI1 FIFO count status"]
+    pub r8_spi1_fifo_count1: R8_SPI1_FIFO_COUNT1,
+}
+#[doc = "R8_SPI1_CTRL_MOD (rw) register accessor: an alias for `Reg<R8_SPI1_CTRL_MOD_SPEC>`"]
+pub type R8_SPI1_CTRL_MOD = crate::Reg<r8_spi1_ctrl_mod::R8_SPI1_CTRL_MOD_SPEC>;
+#[doc = "RW, SPI1 mode control"]
+pub mod r8_spi1_ctrl_mod;
+#[doc = "R8_SPI1_CTRL_CFG (rw) register accessor: an alias for `Reg<R8_SPI1_CTRL_CFG_SPEC>`"]
+pub type R8_SPI1_CTRL_CFG = crate::Reg<r8_spi1_ctrl_cfg::R8_SPI1_CTRL_CFG_SPEC>;
+#[doc = "RW, SPI1 configuration control"]
+pub mod r8_spi1_ctrl_cfg;
+#[doc = "R8_SPI1_INTER_EN (rw) register accessor: an alias for `Reg<R8_SPI1_INTER_EN_SPEC>`"]
+pub type R8_SPI1_INTER_EN = crate::Reg<r8_spi1_inter_en::R8_SPI1_INTER_EN_SPEC>;
+#[doc = "RW, SPI1 interrupt enable"]
+pub mod r8_spi1_inter_en;
+#[doc = "R8_SPI1_CLOCK_DIV (rw) register accessor: an alias for `Reg<R8_SPI1_CLOCK_DIV_SPEC>`"]
+pub type R8_SPI1_CLOCK_DIV = crate::Reg<r8_spi1_clock_div::R8_SPI1_CLOCK_DIV_SPEC>;
+#[doc = "RW, SPI1 master clock divisor"]
+pub mod r8_spi1_clock_div;
+#[doc = "R8_SPI1_BUFFER (rw) register accessor: an alias for `Reg<R8_SPI1_BUFFER_SPEC>`"]
+pub type R8_SPI1_BUFFER = crate::Reg<r8_spi1_buffer::R8_SPI1_BUFFER_SPEC>;
+#[doc = "RW, SPI1 data buffer"]
+pub mod r8_spi1_buffer;
+#[doc = "R8_SPI1_RUN_FLAG (r) register accessor: an alias for `Reg<R8_SPI1_RUN_FLAG_SPEC>`"]
+pub type R8_SPI1_RUN_FLAG = crate::Reg<r8_spi1_run_flag::R8_SPI1_RUN_FLAG_SPEC>;
+#[doc = "RO, SPI1 work flag"]
+pub mod r8_spi1_run_flag;
+#[doc = "R8_SPI1_INT_FLAG (rw) register accessor: an alias for `Reg<R8_SPI1_INT_FLAG_SPEC>`"]
+pub type R8_SPI1_INT_FLAG = crate::Reg<r8_spi1_int_flag::R8_SPI1_INT_FLAG_SPEC>;
+#[doc = "RW1, SPI1 interrupt flag"]
+pub mod r8_spi1_int_flag;
+#[doc = "R8_SPI1_FIFO_COUNT (r) register accessor: an alias for `Reg<R8_SPI1_FIFO_COUNT_SPEC>`"]
+pub type R8_SPI1_FIFO_COUNT = crate::Reg<r8_spi1_fifo_count::R8_SPI1_FIFO_COUNT_SPEC>;
+#[doc = "RO, SPI1 FIFO count status"]
+pub mod r8_spi1_fifo_count;
+#[doc = "R16_SPI1_TOTAL_CNT (rw) register accessor: an alias for `Reg<R16_SPI1_TOTAL_CNT_SPEC>`"]
+pub type R16_SPI1_TOTAL_CNT = crate::Reg<r16_spi1_total_cnt::R16_SPI1_TOTAL_CNT_SPEC>;
+#[doc = "RW, SPI1 total byte count, only low 12 bit"]
+pub mod r16_spi1_total_cnt;
+#[doc = "R8_SPI1_FIFO (rw) register accessor: an alias for `Reg<R8_SPI1_FIFO_SPEC>`"]
+pub type R8_SPI1_FIFO = crate::Reg<r8_spi1_fifo::R8_SPI1_FIFO_SPEC>;
+#[doc = "RO/WO, SPI1 FIFO register"]
+pub mod r8_spi1_fifo;
+#[doc = "R8_SPI1_FIFO_COUNT1 (r) register accessor: an alias for `Reg<R8_SPI1_FIFO_COUNT1_SPEC>`"]
+pub type R8_SPI1_FIFO_COUNT1 = crate::Reg<r8_spi1_fifo_count1::R8_SPI1_FIFO_COUNT1_SPEC>;
+#[doc = "RO, SPI1 FIFO count status"]
+pub mod r8_spi1_fifo_count1;

src/spi1/r16_spi1_total_cnt.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_SPI1_TOTAL_CNT` reader"]
+pub struct R(crate::R<R16_SPI1_TOTAL_CNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_SPI1_TOTAL_CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_SPI1_TOTAL_CNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_SPI1_TOTAL_CNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_SPI1_TOTAL_CNT` writer"]
+pub struct W(crate::W<R16_SPI1_TOTAL_CNT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_SPI1_TOTAL_CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_SPI1_TOTAL_CNT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_SPI1_TOTAL_CNT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI1 total byte count, only low 12 bit\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_spi1_total_cnt](index.html) module"]
+pub struct R16_SPI1_TOTAL_CNT_SPEC;
+impl crate::RegisterSpec for R16_SPI1_TOTAL_CNT_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_spi1_total_cnt::R](R) reader structure"]
+impl crate::Readable for R16_SPI1_TOTAL_CNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_spi1_total_cnt::W](W) writer structure"]
+impl crate::Writable for R16_SPI1_TOTAL_CNT_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_SPI1_TOTAL_CNT to value 0"]
+impl crate::Resettable for R16_SPI1_TOTAL_CNT_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi1/r8_spi1_buffer.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_SPI1_BUFFER` reader"]
+pub struct R(crate::R<R8_SPI1_BUFFER_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI1_BUFFER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI1_BUFFER_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI1_BUFFER_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI1_BUFFER` writer"]
+pub struct W(crate::W<R8_SPI1_BUFFER_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI1_BUFFER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI1_BUFFER_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI1_BUFFER_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI1 data buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi1_buffer](index.html) module"]
+pub struct R8_SPI1_BUFFER_SPEC;
+impl crate::RegisterSpec for R8_SPI1_BUFFER_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi1_buffer::R](R) reader structure"]
+impl crate::Readable for R8_SPI1_BUFFER_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi1_buffer::W](W) writer structure"]
+impl crate::Writable for R8_SPI1_BUFFER_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI1_BUFFER to value 0"]
+impl crate::Resettable for R8_SPI1_BUFFER_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi1/r8_spi1_clock_div.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_SPI1_CLOCK_DIV` reader"]
+pub struct R(crate::R<R8_SPI1_CLOCK_DIV_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI1_CLOCK_DIV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI1_CLOCK_DIV_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI1_CLOCK_DIV_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI1_CLOCK_DIV` writer"]
+pub struct W(crate::W<R8_SPI1_CLOCK_DIV_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI1_CLOCK_DIV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI1_CLOCK_DIV_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI1_CLOCK_DIV_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI1 master clock divisor\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi1_clock_div](index.html) module"]
+pub struct R8_SPI1_CLOCK_DIV_SPEC;
+impl crate::RegisterSpec for R8_SPI1_CLOCK_DIV_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi1_clock_div::R](R) reader structure"]
+impl crate::Readable for R8_SPI1_CLOCK_DIV_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi1_clock_div::W](W) writer structure"]
+impl crate::Writable for R8_SPI1_CLOCK_DIV_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI1_CLOCK_DIV to value 0"]
+impl crate::Resettable for R8_SPI1_CLOCK_DIV_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi1/r8_spi1_ctrl_cfg.rs

@@ -0,0 +1,129 @@
+#[doc = "Register `R8_SPI1_CTRL_CFG` reader"]
+pub struct R(crate::R<R8_SPI1_CTRL_CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI1_CTRL_CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI1_CTRL_CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI1_CTRL_CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI1_CTRL_CFG` writer"]
+pub struct W(crate::W<R8_SPI1_CTRL_CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI1_CTRL_CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI1_CTRL_CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI1_CTRL_CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_SPI_DMA_ENABLE` reader - RW, SPI0 DMA enable"]
+pub type RB_SPI_DMA_ENABLE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_DMA_ENABLE` writer - RW, SPI0 DMA enable"]
+pub type RB_SPI_DMA_ENABLE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_CTRL_CFG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_AUTO_IF` reader - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
+pub type RB_SPI_AUTO_IF_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_AUTO_IF` writer - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
+pub type RB_SPI_AUTO_IF_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_CTRL_CFG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_BIT_ORDER` reader - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
+pub type RB_SPI_BIT_ORDER_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_BIT_ORDER` writer - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
+pub type RB_SPI_BIT_ORDER_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_CTRL_CFG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_MST_DLY_EN` reader - RW, SPI master input delay enable"]
+pub type RB_SPI_MST_DLY_EN_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_MST_DLY_EN` writer - RW, SPI master input delay enable"]
+pub type RB_SPI_MST_DLY_EN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_CTRL_CFG_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - RW, SPI0 DMA enable"]
+    #[inline(always)]
+    pub fn rb_spi_dma_enable(&self) -> RB_SPI_DMA_ENABLE_R {
+        RB_SPI_DMA_ENABLE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 4 - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
+    #[inline(always)]
+    pub fn rb_spi_auto_if(&self) -> RB_SPI_AUTO_IF_R {
+        RB_SPI_AUTO_IF_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
+    #[inline(always)]
+    pub fn rb_spi_bit_order(&self) -> RB_SPI_BIT_ORDER_R {
+        RB_SPI_BIT_ORDER_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RW, SPI master input delay enable"]
+    #[inline(always)]
+    pub fn rb_spi_mst_dly_en(&self) -> RB_SPI_MST_DLY_EN_R {
+        RB_SPI_MST_DLY_EN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW, SPI0 DMA enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_dma_enable(&mut self) -> RB_SPI_DMA_ENABLE_W<0> {
+        RB_SPI_DMA_ENABLE_W::new(self)
+    }
+    #[doc = "Bit 4 - RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_auto_if(&mut self) -> RB_SPI_AUTO_IF_W<4> {
+        RB_SPI_AUTO_IF_W::new(self)
+    }
+    #[doc = "Bit 5 - RW, SPI bit data order: 0=MSB first, 1=LSB first"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_bit_order(&mut self) -> RB_SPI_BIT_ORDER_W<5> {
+        RB_SPI_BIT_ORDER_W::new(self)
+    }
+    #[doc = "Bit 6 - RW, SPI master input delay enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_mst_dly_en(&mut self) -> RB_SPI_MST_DLY_EN_W<6> {
+        RB_SPI_MST_DLY_EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI1 configuration control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi1_ctrl_cfg](index.html) module"]
+pub struct R8_SPI1_CTRL_CFG_SPEC;
+impl crate::RegisterSpec for R8_SPI1_CTRL_CFG_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi1_ctrl_cfg::R](R) reader structure"]
+impl crate::Readable for R8_SPI1_CTRL_CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi1_ctrl_cfg::W](W) writer structure"]
+impl crate::Writable for R8_SPI1_CTRL_CFG_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI1_CTRL_CFG to value 0"]
+impl crate::Resettable for R8_SPI1_CTRL_CFG_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi1/r8_spi1_ctrl_mod.rs

@@ -0,0 +1,165 @@
+#[doc = "Register `R8_SPI1_CTRL_MOD` reader"]
+pub struct R(crate::R<R8_SPI1_CTRL_MOD_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI1_CTRL_MOD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI1_CTRL_MOD_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI1_CTRL_MOD_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI1_CTRL_MOD` writer"]
+pub struct W(crate::W<R8_SPI1_CTRL_MOD_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI1_CTRL_MOD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI1_CTRL_MOD_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI1_CTRL_MOD_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_SPI_ALL_CLEAR` reader - RW, force clear SPI FIFO and count"]
+pub type RB_SPI_ALL_CLEAR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_ALL_CLEAR` writer - RW, force clear SPI FIFO and count"]
+pub type RB_SPI_ALL_CLEAR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD` reader - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI0 slave command mode: 0=byte stream, 1=first byte command"]
+pub type RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD` writer - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI0 slave command mode: 0=byte stream, 1=first byte command"]
+pub type RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_FIFO_DIR` reader - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
+pub type RB_SPI_FIFO_DIR_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_FIFO_DIR` writer - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
+pub type RB_SPI_FIFO_DIR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_SCK_OE` reader - RW, SPI SCK output enable"]
+pub type RB_SPI_SCK_OE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_SCK_OE` writer - RW, SPI SCK output enable"]
+pub type RB_SPI_SCK_OE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_MOSI_OE` reader - RW, SPI MOSI output enable"]
+pub type RB_SPI_MOSI_OE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_MOSI_OE` writer - RW, SPI MOSI output enable"]
+pub type RB_SPI_MOSI_OE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_CTRL_MOD_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_MISO_OE` reader - RW, SPI MISO output enable"]
+pub type RB_SPI_MISO_OE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_MISO_OE` writer - RW, SPI MISO output enable"]
+pub type RB_SPI_MISO_OE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_CTRL_MOD_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 1 - RW, force clear SPI FIFO and count"]
+    #[inline(always)]
+    pub fn rb_spi_all_clear(&self) -> RB_SPI_ALL_CLEAR_R {
+        RB_SPI_ALL_CLEAR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI0 slave command mode: 0=byte stream, 1=first byte command"]
+    #[inline(always)]
+    pub fn rb_spi_mst_sck_mod__rb_spi_slv_cmd_mod(
+        &self,
+    ) -> RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_R {
+        RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
+    #[inline(always)]
+    pub fn rb_spi_fifo_dir(&self) -> RB_SPI_FIFO_DIR_R {
+        RB_SPI_FIFO_DIR_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RW, SPI SCK output enable"]
+    #[inline(always)]
+    pub fn rb_spi_sck_oe(&self) -> RB_SPI_SCK_OE_R {
+        RB_SPI_SCK_OE_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RW, SPI MOSI output enable"]
+    #[inline(always)]
+    pub fn rb_spi_mosi_oe(&self) -> RB_SPI_MOSI_OE_R {
+        RB_SPI_MOSI_OE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - RW, SPI MISO output enable"]
+    #[inline(always)]
+    pub fn rb_spi_miso_oe(&self) -> RB_SPI_MISO_OE_R {
+        RB_SPI_MISO_OE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 1 - RW, force clear SPI FIFO and count"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_all_clear(&mut self) -> RB_SPI_ALL_CLEAR_W<1> {
+        RB_SPI_ALL_CLEAR_W::new(self)
+    }
+    #[doc = "Bit 3 - RW, SPI master clock mode: 0=mode 0, 1=mode 3;RW, SPI0 slave command mode: 0=byte stream, 1=first byte command"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_mst_sck_mod__rb_spi_slv_cmd_mod(
+        &mut self,
+    ) -> RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_W<3> {
+        RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD_W::new(self)
+    }
+    #[doc = "Bit 4 - RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_fifo_dir(&mut self) -> RB_SPI_FIFO_DIR_W<4> {
+        RB_SPI_FIFO_DIR_W::new(self)
+    }
+    #[doc = "Bit 5 - RW, SPI SCK output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_sck_oe(&mut self) -> RB_SPI_SCK_OE_W<5> {
+        RB_SPI_SCK_OE_W::new(self)
+    }
+    #[doc = "Bit 6 - RW, SPI MOSI output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_mosi_oe(&mut self) -> RB_SPI_MOSI_OE_W<6> {
+        RB_SPI_MOSI_OE_W::new(self)
+    }
+    #[doc = "Bit 7 - RW, SPI MISO output enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_miso_oe(&mut self) -> RB_SPI_MISO_OE_W<7> {
+        RB_SPI_MISO_OE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI1 mode control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi1_ctrl_mod](index.html) module"]
+pub struct R8_SPI1_CTRL_MOD_SPEC;
+impl crate::RegisterSpec for R8_SPI1_CTRL_MOD_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi1_ctrl_mod::R](R) reader structure"]
+impl crate::Readable for R8_SPI1_CTRL_MOD_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi1_ctrl_mod::W](W) writer structure"]
+impl crate::Writable for R8_SPI1_CTRL_MOD_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI1_CTRL_MOD to value 0"]
+impl crate::Resettable for R8_SPI1_CTRL_MOD_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi1/r8_spi1_fifo.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R8_SPI1_FIFO` reader"]
+pub struct R(crate::R<R8_SPI1_FIFO_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI1_FIFO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI1_FIFO_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI1_FIFO_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI1_FIFO` writer"]
+pub struct W(crate::W<R8_SPI1_FIFO_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI1_FIFO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI1_FIFO_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI1_FIFO_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RO/WO, SPI1 FIFO register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi1_fifo](index.html) module"]
+pub struct R8_SPI1_FIFO_SPEC;
+impl crate::RegisterSpec for R8_SPI1_FIFO_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi1_fifo::R](R) reader structure"]
+impl crate::Readable for R8_SPI1_FIFO_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi1_fifo::W](W) writer structure"]
+impl crate::Writable for R8_SPI1_FIFO_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI1_FIFO to value 0"]
+impl crate::Resettable for R8_SPI1_FIFO_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi1/r8_spi1_fifo_count.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `R8_SPI1_FIFO_COUNT` reader"]
+pub struct R(crate::R<R8_SPI1_FIFO_COUNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI1_FIFO_COUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI1_FIFO_COUNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI1_FIFO_COUNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "RO, SPI1 FIFO count status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi1_fifo_count](index.html) module"]
+pub struct R8_SPI1_FIFO_COUNT_SPEC;
+impl crate::RegisterSpec for R8_SPI1_FIFO_COUNT_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi1_fifo_count::R](R) reader structure"]
+impl crate::Readable for R8_SPI1_FIFO_COUNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets R8_SPI1_FIFO_COUNT to value 0"]
+impl crate::Resettable for R8_SPI1_FIFO_COUNT_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi1/r8_spi1_fifo_count1.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `R8_SPI1_FIFO_COUNT1` reader"]
+pub struct R(crate::R<R8_SPI1_FIFO_COUNT1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI1_FIFO_COUNT1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI1_FIFO_COUNT1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI1_FIFO_COUNT1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "RO, SPI1 FIFO count status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi1_fifo_count1](index.html) module"]
+pub struct R8_SPI1_FIFO_COUNT1_SPEC;
+impl crate::RegisterSpec for R8_SPI1_FIFO_COUNT1_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi1_fifo_count1::R](R) reader structure"]
+impl crate::Readable for R8_SPI1_FIFO_COUNT1_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets R8_SPI1_FIFO_COUNT1 to value 0"]
+impl crate::Resettable for R8_SPI1_FIFO_COUNT1_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi1/r8_spi1_int_flag.rs

@@ -0,0 +1,144 @@
+#[doc = "Register `R8_SPI1_INT_FLAG` reader"]
+pub struct R(crate::R<R8_SPI1_INT_FLAG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI1_INT_FLAG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI1_INT_FLAG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI1_INT_FLAG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI1_INT_FLAG` writer"]
+pub struct W(crate::W<R8_SPI1_INT_FLAG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI1_INT_FLAG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI1_INT_FLAG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI1_INT_FLAG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_SPI_IF_CNT_END` reader - RW1, interrupt flag for SPI total byte count end"]
+pub type RB_SPI_IF_CNT_END_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IF_CNT_END` writer - RW1, interrupt flag for SPI total byte count end"]
+pub type RB_SPI_IF_CNT_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_INT_FLAG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IF_BYTE_END` reader - RW1, interrupt flag for SPI byte exchanged"]
+pub type RB_SPI_IF_BYTE_END_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IF_BYTE_END` writer - RW1, interrupt flag for SPI byte exchanged"]
+pub type RB_SPI_IF_BYTE_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_INT_FLAG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IF_FIFO_HF` reader - RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : less than 4bytes)"]
+pub type RB_SPI_IF_FIFO_HF_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IF_FIFO_HF` writer - RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : less than 4bytes)"]
+pub type RB_SPI_IF_FIFO_HF_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_INT_FLAG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IF_FIFO_OV` reader - RW1, interrupt flag for SPI FIFO overflow"]
+pub type RB_SPI_IF_FIFO_OV_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IF_FIFO_OV` writer - RW1, interrupt flag for SPI FIFO overflow"]
+pub type RB_SPI_IF_FIFO_OV_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_INT_FLAG_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_FREE` reader - RO, current SPI free status"]
+pub type RB_SPI_FREE_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_FREE` writer - RO, current SPI free status"]
+pub type RB_SPI_FREE_W<'a, const O: u8> = crate::BitWriter<'a, u8, R8_SPI1_INT_FLAG_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - RW1, interrupt flag for SPI total byte count end"]
+    #[inline(always)]
+    pub fn rb_spi_if_cnt_end(&self) -> RB_SPI_IF_CNT_END_R {
+        RB_SPI_IF_CNT_END_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RW1, interrupt flag for SPI byte exchanged"]
+    #[inline(always)]
+    pub fn rb_spi_if_byte_end(&self) -> RB_SPI_IF_BYTE_END_R {
+        RB_SPI_IF_BYTE_END_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : less than 4bytes)"]
+    #[inline(always)]
+    pub fn rb_spi_if_fifo_hf(&self) -> RB_SPI_IF_FIFO_HF_R {
+        RB_SPI_IF_FIFO_HF_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 4 - RW1, interrupt flag for SPI FIFO overflow"]
+    #[inline(always)]
+    pub fn rb_spi_if_fifo_ov(&self) -> RB_SPI_IF_FIFO_OV_R {
+        RB_SPI_IF_FIFO_OV_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RO, current SPI free status"]
+    #[inline(always)]
+    pub fn rb_spi_free(&self) -> RB_SPI_FREE_R {
+        RB_SPI_FREE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW1, interrupt flag for SPI total byte count end"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_if_cnt_end(&mut self) -> RB_SPI_IF_CNT_END_W<0> {
+        RB_SPI_IF_CNT_END_W::new(self)
+    }
+    #[doc = "Bit 1 - RW1, interrupt flag for SPI byte exchanged"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_if_byte_end(&mut self) -> RB_SPI_IF_BYTE_END_W<1> {
+        RB_SPI_IF_BYTE_END_W::new(self)
+    }
+    #[doc = "Bit 2 - RW1, interrupt flag for SPI FIFO half (RB_SPI_FIFO_DIR ? >=4bytes : less than 4bytes)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_if_fifo_hf(&mut self) -> RB_SPI_IF_FIFO_HF_W<2> {
+        RB_SPI_IF_FIFO_HF_W::new(self)
+    }
+    #[doc = "Bit 4 - RW1, interrupt flag for SPI FIFO overflow"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_if_fifo_ov(&mut self) -> RB_SPI_IF_FIFO_OV_W<4> {
+        RB_SPI_IF_FIFO_OV_W::new(self)
+    }
+    #[doc = "Bit 6 - RO, current SPI free status"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_free(&mut self) -> RB_SPI_FREE_W<6> {
+        RB_SPI_FREE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW1, SPI1 interrupt flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi1_int_flag](index.html) module"]
+pub struct R8_SPI1_INT_FLAG_SPEC;
+impl crate::RegisterSpec for R8_SPI1_INT_FLAG_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi1_int_flag::R](R) reader structure"]
+impl crate::Readable for R8_SPI1_INT_FLAG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi1_int_flag::W](W) writer structure"]
+impl crate::Writable for R8_SPI1_INT_FLAG_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI1_INT_FLAG to value 0"]
+impl crate::Resettable for R8_SPI1_INT_FLAG_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi1/r8_spi1_inter_en.rs

@@ -0,0 +1,113 @@
+#[doc = "Register `R8_SPI1_INTER_EN` reader"]
+pub struct R(crate::R<R8_SPI1_INTER_EN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI1_INTER_EN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI1_INTER_EN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI1_INTER_EN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R8_SPI1_INTER_EN` writer"]
+pub struct W(crate::W<R8_SPI1_INTER_EN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R8_SPI1_INTER_EN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R8_SPI1_INTER_EN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R8_SPI1_INTER_EN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_SPI_IE_CNT_END` reader - RW, enable interrupt for SPI total byte count end"]
+pub type RB_SPI_IE_CNT_END_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IE_CNT_END` writer - RW, enable interrupt for SPI total byte count end"]
+pub type RB_SPI_IE_CNT_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_INTER_EN_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IE_BYTE_END` reader - RW, enable interrupt for SPI byte exchanged"]
+pub type RB_SPI_IE_BYTE_END_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IE_BYTE_END` writer - RW, enable interrupt for SPI byte exchanged"]
+pub type RB_SPI_IE_BYTE_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_INTER_EN_SPEC, bool, O>;
+#[doc = "Field `RB_SPI_IE_FIFO_HF` reader - RW, enable interrupt for SPI FIFO half"]
+pub type RB_SPI_IE_FIFO_HF_R = crate::BitReader<bool>;
+#[doc = "Field `RB_SPI_IE_FIFO_HF` writer - RW, enable interrupt for SPI FIFO half"]
+pub type RB_SPI_IE_FIFO_HF_W<'a, const O: u8> =
+    crate::BitWriter<'a, u8, R8_SPI1_INTER_EN_SPEC, bool, O>;
+impl R {
+    #[doc = "Bit 0 - RW, enable interrupt for SPI total byte count end"]
+    #[inline(always)]
+    pub fn rb_spi_ie_cnt_end(&self) -> RB_SPI_IE_CNT_END_R {
+        RB_SPI_IE_CNT_END_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RW, enable interrupt for SPI byte exchanged"]
+    #[inline(always)]
+    pub fn rb_spi_ie_byte_end(&self) -> RB_SPI_IE_BYTE_END_R {
+        RB_SPI_IE_BYTE_END_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RW, enable interrupt for SPI FIFO half"]
+    #[inline(always)]
+    pub fn rb_spi_ie_fifo_hf(&self) -> RB_SPI_IE_FIFO_HF_R {
+        RB_SPI_IE_FIFO_HF_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RW, enable interrupt for SPI total byte count end"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_ie_cnt_end(&mut self) -> RB_SPI_IE_CNT_END_W<0> {
+        RB_SPI_IE_CNT_END_W::new(self)
+    }
+    #[doc = "Bit 1 - RW, enable interrupt for SPI byte exchanged"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_ie_byte_end(&mut self) -> RB_SPI_IE_BYTE_END_W<1> {
+        RB_SPI_IE_BYTE_END_W::new(self)
+    }
+    #[doc = "Bit 2 - RW, enable interrupt for SPI FIFO half"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_spi_ie_fifo_hf(&mut self) -> RB_SPI_IE_FIFO_HF_W<2> {
+        RB_SPI_IE_FIFO_HF_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RW, SPI1 interrupt enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi1_inter_en](index.html) module"]
+pub struct R8_SPI1_INTER_EN_SPEC;
+impl crate::RegisterSpec for R8_SPI1_INTER_EN_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi1_inter_en::R](R) reader structure"]
+impl crate::Readable for R8_SPI1_INTER_EN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r8_spi1_inter_en::W](W) writer structure"]
+impl crate::Writable for R8_SPI1_INTER_EN_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R8_SPI1_INTER_EN to value 0"]
+impl crate::Resettable for R8_SPI1_INTER_EN_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/spi1/r8_spi1_run_flag.rs

@@ -0,0 +1,37 @@
+#[doc = "Register `R8_SPI1_RUN_FLAG` reader"]
+pub struct R(crate::R<R8_SPI1_RUN_FLAG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R8_SPI1_RUN_FLAG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R8_SPI1_RUN_FLAG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R8_SPI1_RUN_FLAG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `RB_SPI_FIFO_READY` reader - RO, SPI FIFO ready status"]
+pub type RB_SPI_FIFO_READY_R = crate::BitReader<bool>;
+impl R {
+    #[doc = "Bit 5 - RO, SPI FIFO ready status"]
+    #[inline(always)]
+    pub fn rb_spi_fifo_ready(&self) -> RB_SPI_FIFO_READY_R {
+        RB_SPI_FIFO_READY_R::new(((self.bits >> 5) & 1) != 0)
+    }
+}
+#[doc = "RO, SPI1 work flag\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r8_spi1_run_flag](index.html) module"]
+pub struct R8_SPI1_RUN_FLAG_SPEC;
+impl crate::RegisterSpec for R8_SPI1_RUN_FLAG_SPEC {
+    type Ux = u8;
+}
+#[doc = "`read()` method returns [r8_spi1_run_flag::R](R) reader structure"]
+impl crate::Readable for R8_SPI1_RUN_FLAG_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets R8_SPI1_RUN_FLAG to value 0"]
+impl crate::Resettable for R8_SPI1_RUN_FLAG_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/sys.rs

@@ -0,0 +1,419 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 0x08],
+    #[doc = "0x08 - RWA, system clock configuration, SAM"]
+    pub r16_clk_sys_cfg: R16_CLK_SYS_CFG,
+    #[doc = "0x0a - RWA, high frequency clock module power control, SAM"]
+    pub r8_hfck_pwr_ctrl: R8_HFCK_PWR_CTRL,
+    _reserved2: [u8; 0x01],
+    #[doc = "0x0c - RWA, sleep clock off control byte 0, SAM"]
+    pub r8_slp_clk_off0: R8_SLP_CLK_OFF0,
+    #[doc = "0x0d - RWA, sleep clock off control byte 1, SAM"]
+    pub r8_slp_clk_off1: R8_SLP_CLK_OFF1,
+    #[doc = "0x0e - RWA, wake control, SAM"]
+    pub r8_slp_wake_ctrl: R8_SLP_WAKE_CTRL,
+    #[doc = "0x0f - RWA, peripherals power down control, SAM"]
+    pub r8_slp_power_ctrl: R8_SLP_POWER_CTRL,
+    _reserved6: [u8; 0x08],
+    #[doc = "0x18 - RW, function pin alternate configuration"]
+    pub r16_pin_alternate: R16_PIN_ALTERNATE,
+    #[doc = "0x1a - RW, analog pin enable and digital input disable"]
+    pub r16_pin_analog_ie: R16_PIN_ANALOG_IE,
+    #[doc = "0x1c - RW, parallel slave configuration"]
+    pub r8_slv_config: R8_SLV_CONFIG,
+    _reserved9: [u8; 0x03],
+    #[doc = "0x20 - RWA, power plan before sleep instruction, SAM"]
+    pub r16_power_plan: R16_POWER_PLAN,
+    #[doc = "0x22 - RWA, aux power adjust control, SAM"]
+    pub r8_aux_power_adj: R8_AUX_POWER_ADJ,
+    _reserved11: [u8; 0x01],
+    #[doc = "0x24 - RWA, battery voltage detector control, SAM"]
+    pub r8_bat_det_ctrl: R8_BAT_DET_CTRL,
+    #[doc = "0x25 - RWA, battery voltage detector configuration, SAM"]
+    pub r8_bat_det_cfg: R8_BAT_DET_CFG,
+    #[doc = "0x26 - RO, battery status"]
+    pub r8_bat_status: R8_BAT_STATUS,
+    _reserved14: [u8; 0x05],
+    #[doc = "0x2c - RWA, internal 32KHz oscillator tune control, SAM"]
+    pub r16_int32k_tune: R16_INT32K_TUNE,
+    #[doc = "0x2e - RWA, external 32KHz oscillator tune control, SAM"]
+    pub r8_xt32k_tune: R8_XT32K_TUNE,
+    #[doc = "0x2f - RWA, 32KHz oscillator configure"]
+    pub r8_ck32k_config: R8_CK32K_CONFIG,
+    #[doc = "0x30 - RW, RTC flag and clear control"]
+    pub r8_rtc_flag_ctrl: R8_RTC_FLAG_CTRL,
+    #[doc = "0x31 - RWA, RTC mode control, SAM"]
+    pub r8_rtc_mode_ctrl: R8_RTC_MODE_CTRL,
+    _reserved19: [u8; 0x02],
+    #[doc = "0x34 - RWA, RTC trigger value, SAM"]
+    pub r32_rtc_trig: R32_RTC_TRIG,
+    #[doc = "0x38 - RO, RTC count based 32KHz"]
+    pub r16_rtc_cnt_32k: R16_RTC_CNT_32K,
+    #[doc = "0x3a - RO, RTC count based 2 second"]
+    pub r16_rtc_cnt_2s: R16_RTC_CNT_2S,
+    #[doc = "0x3c - RO, RTC count based one day, only low 14 bit"]
+    pub r32_rtc_cnt_day: R32_RTC_CNT_DAY,
+    _reserved_23_r8_safe_access_sig: [u8; 0x01],
+    #[doc = "0x41 - RF, chip ID register, always is ID_CH57*"]
+    pub r8_chip_id: R8_CHIP_ID,
+    #[doc = "0x42 - RF, safe accessing ID register, always 0x04"]
+    pub r8_safe_access_id: R8_SAFE_ACCESS_ID,
+    #[doc = "0x43 - RW, watch-dog count, count by clock frequency Fsys/131072"]
+    pub r8_wdog_count: R8_WDOG_COUNT,
+    #[doc = "0x44 - RWA, reset status, SAM"]
+    pub r8_reset_status: R8_RESET_STATUS,
+    #[doc = "0x45 - RO, global configuration information and status"]
+    pub r8_glob_cfg_info: R8_GLOB_CFG_INFO,
+    #[doc = "0x46 - RWA, reset and watch-dog control, SAM"]
+    pub r8_rst_wdog_ctrl: R8_RST_WDOG_CTRL,
+    #[doc = "0x47 - RW, value keeper during global reset"]
+    pub r8_glob_reset_keep: R8_GLOB_RESET_KEEP,
+    _reserved31: [u8; 0x02],
+    #[doc = "0x4a - RWA, Flash ROM configure register"]
+    pub r8_cfg_flash: R8_CFG_FLASH,
+    #[doc = "0x4b - RWA, PLL configuration control, SAM"]
+    pub r8_pll_config: R8_PLL_CONFIG,
+    #[doc = "0x4c - RWA, internal 32MHz oscillator tune control, SAM"]
+    pub r16_int32m_calib: R16_INT32M_CALIB,
+    #[doc = "0x4e - RWA, external 32MHz oscillator tune control, SAM"]
+    pub r8_xt32m_tune: R8_XT32M_TUNE,
+    _reserved35: [u8; 0x01],
+    #[doc = "0x50 - RO, system clock count value for 32KHz 5 cycles"]
+    pub r16_osc_cal_cnt: R16_OSC_CAL_CNT,
+    #[doc = "0x52 - RWA, oscillator frequency calibration control, SAM"]
+    pub r8_osc_cal_ctrl: R8_OSC_CAL_CTRL,
+    _reserved37: [u8; 0x05],
+    #[doc = "0x58 - RW, ADC input channel selection"]
+    pub r8_adc_channel: R8_ADC_CHANNEL,
+    #[doc = "0x59 - RW, ADC configure"]
+    pub r8_adc_cfg: R8_ADC_CFG,
+    #[doc = "0x5a - RW, ADC convert control"]
+    pub r8_adc_convert: R8_ADC_CONVERT,
+    #[doc = "0x5b - RW, temperature sensor control"]
+    pub r8_tem_sensor: R8_TEM_SENSOR,
+    #[doc = "0x5c - RO, ADC data"]
+    pub r16_adc_data: R16_ADC_DATA,
+    #[doc = "0x5e - RO, ADC interrupt flag register"]
+    pub r8_adc_int_flag: R8_ADC_INT_FLAG,
+    #[doc = "0x5f - WO, Touch-key charge and discharge count"]
+    pub r8_tkey_cnt: R8_TKEY_CNT,
+    _reserved44: [u8; 0x30],
+    #[doc = "0x90 - RW, GPIO PA interrupt enable"]
+    pub r16_pa_int_en: R16_PA_INT_EN,
+    #[doc = "0x92 - RW, GPIO PB interrupt enable"]
+    pub r16_pb_int_en: R16_PB_INT_EN,
+    #[doc = "0x94 - RW, GPIO PA interrupt mode: 0=level action, 1=edge action"]
+    pub r16_pa_int_mode: R16_PA_INT_MODE,
+    _reserved_47_r8_slv_wr_data: [u8; 0x02],
+    _reserved48: [u8; 0x04],
+    #[doc = "0x9c - RW1, GPIO PA interrupt flag"]
+    pub r16_pa_int_if: R16_PA_INT_IF,
+    #[doc = "0x9e - RW1, GPIO PB interrupt flag"]
+    pub r16_pb_int_if: R16_PB_INT_IF,
+    #[doc = "0xa0 - RW, GPIO PA I/O direction: 0=in, 1=out"]
+    pub r32_pa_dir: R32_PA_DIR,
+    #[doc = "0xa4 - RO, GPIO PA input"]
+    pub r32_pa_pin: R32_PA_PIN,
+    #[doc = "0xa8 - RW, GPIO PA output"]
+    pub r32_pa_out: R32_PA_OUT,
+    #[doc = "0xac - WZ, GPIO PA clear output: 0=keep, 1=clear"]
+    pub r32_pa_clr: R32_PA_CLR,
+    #[doc = "0xb0 - RW, GPIO PA pullup resistance enable"]
+    pub r32_pa_pu: R32_PA_PU,
+    #[doc = "0xb4 - RW, PA pulldown for input or PA driving capability for output"]
+    pub r32_pa_pd_drv: R32_PA_PD_DRV,
+    _reserved56: [u8; 0x08],
+    #[doc = "0xc0 - RW, GPIO PB I/O direction: 0=in, 1=out"]
+    pub r32_pb_dir: R32_PB_DIR,
+    #[doc = "0xc4 - RO, GPIO PB input"]
+    pub r32_pb_pin: R32_PB_PIN,
+    #[doc = "0xc8 - RW, GPIO PB output;RW, data for parallel slave read"]
+    pub r32_pb_out__r8_slv_rd_data: R32_PB_OUT__R8_SLV_RD_DATA,
+    #[doc = "0xcc - WZ, GPIO PB clear output: 0=keep, 1=clear"]
+    pub r32_pb_clr: R32_PB_CLR,
+    #[doc = "0xd0 - RW, GPIO PB pullup resistance enable"]
+    pub r32_pb_pu: R32_PB_PU,
+    #[doc = "0xd4 - RW, PB pulldown for input or PB driving capability for output"]
+    pub r32_pb_pd_drv: R32_PB_PD_DRV,
+}
+impl RegisterBlock {
+    #[doc = "0x40 - safe accessing sign register, must write 0x57 then 0xA8 to enter safe accessing mode"]
+    #[inline(always)]
+    pub const fn r8_safe_access_sig_wr(&self) -> &R8_SAFE_ACCESS_SIG_WR {
+        unsafe { &*(self as *const Self).cast::<u8>().add(64usize).cast() }
+    }
+    #[doc = "0x40 - R8_SAFE_ACCESS_SIG_RD Register safe accessing"]
+    #[inline(always)]
+    pub const fn r8_safe_access_sig_rd(&self) -> &R8_SAFE_ACCESS_SIG_RD {
+        unsafe { &*(self as *const Self).cast::<u8>().add(64usize).cast() }
+    }
+    #[doc = "0x96 - RW, GPIO PB interrupt mode: 0=level action, 1=edge action;RW, status for parallel slave read"]
+    #[inline(always)]
+    pub const fn r16_pb_int_mode__r8_slv_rd_stat(&self) -> &R16_PB_INT_MODE__R8_SLV_RD_STAT {
+        unsafe { &*(self as *const Self).cast::<u8>().add(150usize).cast() }
+    }
+    #[doc = "0x97 - RW, data or command from parallel slave write"]
+    #[inline(always)]
+    pub const fn r8_slv_wr_data(&self) -> &R8_SLV_WR_DATA {
+        unsafe { &*(self as *const Self).cast::<u8>().add(151usize).cast() }
+    }
+}
+#[doc = "R16_CLK_SYS_CFG (rw) register accessor: an alias for `Reg<R16_CLK_SYS_CFG_SPEC>`"]
+pub type R16_CLK_SYS_CFG = crate::Reg<r16_clk_sys_cfg::R16_CLK_SYS_CFG_SPEC>;
+#[doc = "RWA, system clock configuration, SAM"]
+pub mod r16_clk_sys_cfg;
+#[doc = "R8_HFCK_PWR_CTRL (rw) register accessor: an alias for `Reg<R8_HFCK_PWR_CTRL_SPEC>`"]
+pub type R8_HFCK_PWR_CTRL = crate::Reg<r8_hfck_pwr_ctrl::R8_HFCK_PWR_CTRL_SPEC>;
+#[doc = "RWA, high frequency clock module power control, SAM"]
+pub mod r8_hfck_pwr_ctrl;
+#[doc = "R8_SLP_CLK_OFF0 (rw) register accessor: an alias for `Reg<R8_SLP_CLK_OFF0_SPEC>`"]
+pub type R8_SLP_CLK_OFF0 = crate::Reg<r8_slp_clk_off0::R8_SLP_CLK_OFF0_SPEC>;
+#[doc = "RWA, sleep clock off control byte 0, SAM"]
+pub mod r8_slp_clk_off0;
+#[doc = "R8_SLP_CLK_OFF1 (rw) register accessor: an alias for `Reg<R8_SLP_CLK_OFF1_SPEC>`"]
+pub type R8_SLP_CLK_OFF1 = crate::Reg<r8_slp_clk_off1::R8_SLP_CLK_OFF1_SPEC>;
+#[doc = "RWA, sleep clock off control byte 1, SAM"]
+pub mod r8_slp_clk_off1;
+#[doc = "R8_SLP_WAKE_CTRL (rw) register accessor: an alias for `Reg<R8_SLP_WAKE_CTRL_SPEC>`"]
+pub type R8_SLP_WAKE_CTRL = crate::Reg<r8_slp_wake_ctrl::R8_SLP_WAKE_CTRL_SPEC>;
+#[doc = "RWA, wake control, SAM"]
+pub mod r8_slp_wake_ctrl;
+#[doc = "R8_SLP_POWER_CTRL (rw) register accessor: an alias for `Reg<R8_SLP_POWER_CTRL_SPEC>`"]
+pub type R8_SLP_POWER_CTRL = crate::Reg<r8_slp_power_ctrl::R8_SLP_POWER_CTRL_SPEC>;
+#[doc = "RWA, peripherals power down control, SAM"]
+pub mod r8_slp_power_ctrl;
+#[doc = "R16_PIN_ALTERNATE (rw) register accessor: an alias for `Reg<R16_PIN_ALTERNATE_SPEC>`"]
+pub type R16_PIN_ALTERNATE = crate::Reg<r16_pin_alternate::R16_PIN_ALTERNATE_SPEC>;
+#[doc = "RW, function pin alternate configuration"]
+pub mod r16_pin_alternate;
+#[doc = "R16_PIN_ANALOG_IE (rw) register accessor: an alias for `Reg<R16_PIN_ANALOG_IE_SPEC>`"]
+pub type R16_PIN_ANALOG_IE = crate::Reg<r16_pin_analog_ie::R16_PIN_ANALOG_IE_SPEC>;
+#[doc = "RW, analog pin enable and digital input disable"]
+pub mod r16_pin_analog_ie;
+#[doc = "R8_SLV_CONFIG (rw) register accessor: an alias for `Reg<R8_SLV_CONFIG_SPEC>`"]
+pub type R8_SLV_CONFIG = crate::Reg<r8_slv_config::R8_SLV_CONFIG_SPEC>;
+#[doc = "RW, parallel slave configuration"]
+pub mod r8_slv_config;
+#[doc = "R16_POWER_PLAN (rw) register accessor: an alias for `Reg<R16_POWER_PLAN_SPEC>`"]
+pub type R16_POWER_PLAN = crate::Reg<r16_power_plan::R16_POWER_PLAN_SPEC>;
+#[doc = "RWA, power plan before sleep instruction, SAM"]
+pub mod r16_power_plan;
+#[doc = "R8_AUX_POWER_ADJ (rw) register accessor: an alias for `Reg<R8_AUX_POWER_ADJ_SPEC>`"]
+pub type R8_AUX_POWER_ADJ = crate::Reg<r8_aux_power_adj::R8_AUX_POWER_ADJ_SPEC>;
+#[doc = "RWA, aux power adjust control, SAM"]
+pub mod r8_aux_power_adj;
+#[doc = "R8_BAT_DET_CTRL (rw) register accessor: an alias for `Reg<R8_BAT_DET_CTRL_SPEC>`"]
+pub type R8_BAT_DET_CTRL = crate::Reg<r8_bat_det_ctrl::R8_BAT_DET_CTRL_SPEC>;
+#[doc = "RWA, battery voltage detector control, SAM"]
+pub mod r8_bat_det_ctrl;
+#[doc = "R8_BAT_DET_CFG (rw) register accessor: an alias for `Reg<R8_BAT_DET_CFG_SPEC>`"]
+pub type R8_BAT_DET_CFG = crate::Reg<r8_bat_det_cfg::R8_BAT_DET_CFG_SPEC>;
+#[doc = "RWA, battery voltage detector configuration, SAM"]
+pub mod r8_bat_det_cfg;
+#[doc = "R8_BAT_STATUS (r) register accessor: an alias for `Reg<R8_BAT_STATUS_SPEC>`"]
+pub type R8_BAT_STATUS = crate::Reg<r8_bat_status::R8_BAT_STATUS_SPEC>;
+#[doc = "RO, battery status"]
+pub mod r8_bat_status;
+#[doc = "R16_INT32K_TUNE (rw) register accessor: an alias for `Reg<R16_INT32K_TUNE_SPEC>`"]
+pub type R16_INT32K_TUNE = crate::Reg<r16_int32k_tune::R16_INT32K_TUNE_SPEC>;
+#[doc = "RWA, internal 32KHz oscillator tune control, SAM"]
+pub mod r16_int32k_tune;
+#[doc = "R8_XT32K_TUNE (rw) register accessor: an alias for `Reg<R8_XT32K_TUNE_SPEC>`"]
+pub type R8_XT32K_TUNE = crate::Reg<r8_xt32k_tune::R8_XT32K_TUNE_SPEC>;
+#[doc = "RWA, external 32KHz oscillator tune control, SAM"]
+pub mod r8_xt32k_tune;
+#[doc = "R8_CK32K_CONFIG (rw) register accessor: an alias for `Reg<R8_CK32K_CONFIG_SPEC>`"]
+pub type R8_CK32K_CONFIG = crate::Reg<r8_ck32k_config::R8_CK32K_CONFIG_SPEC>;
+#[doc = "RWA, 32KHz oscillator configure"]
+pub mod r8_ck32k_config;
+#[doc = "R8_RTC_FLAG_CTRL (rw) register accessor: an alias for `Reg<R8_RTC_FLAG_CTRL_SPEC>`"]
+pub type R8_RTC_FLAG_CTRL = crate::Reg<r8_rtc_flag_ctrl::R8_RTC_FLAG_CTRL_SPEC>;
+#[doc = "RW, RTC flag and clear control"]
+pub mod r8_rtc_flag_ctrl;
+#[doc = "R8_RTC_MODE_CTRL (rw) register accessor: an alias for `Reg<R8_RTC_MODE_CTRL_SPEC>`"]
+pub type R8_RTC_MODE_CTRL = crate::Reg<r8_rtc_mode_ctrl::R8_RTC_MODE_CTRL_SPEC>;
+#[doc = "RWA, RTC mode control, SAM"]
+pub mod r8_rtc_mode_ctrl;
+#[doc = "R32_RTC_TRIG (rw) register accessor: an alias for `Reg<R32_RTC_TRIG_SPEC>`"]
+pub type R32_RTC_TRIG = crate::Reg<r32_rtc_trig::R32_RTC_TRIG_SPEC>;
+#[doc = "RWA, RTC trigger value, SAM"]
+pub mod r32_rtc_trig;
+#[doc = "R16_RTC_CNT_32K (r) register accessor: an alias for `Reg<R16_RTC_CNT_32K_SPEC>`"]
+pub type R16_RTC_CNT_32K = crate::Reg<r16_rtc_cnt_32k::R16_RTC_CNT_32K_SPEC>;
+#[doc = "RO, RTC count based 32KHz"]
+pub mod r16_rtc_cnt_32k;
+#[doc = "R16_RTC_CNT_2S (r) register accessor: an alias for `Reg<R16_RTC_CNT_2S_SPEC>`"]
+pub type R16_RTC_CNT_2S = crate::Reg<r16_rtc_cnt_2s::R16_RTC_CNT_2S_SPEC>;
+#[doc = "RO, RTC count based 2 second"]
+pub mod r16_rtc_cnt_2s;
+#[doc = "R32_RTC_CNT_DAY (r) register accessor: an alias for `Reg<R32_RTC_CNT_DAY_SPEC>`"]
+pub type R32_RTC_CNT_DAY = crate::Reg<r32_rtc_cnt_day::R32_RTC_CNT_DAY_SPEC>;
+#[doc = "RO, RTC count based one day, only low 14 bit"]
+pub mod r32_rtc_cnt_day;
+#[doc = "R8_SAFE_ACCESS_SIG_RD (r) register accessor: an alias for `Reg<R8_SAFE_ACCESS_SIG_RD_SPEC>`"]
+pub type R8_SAFE_ACCESS_SIG_RD = crate::Reg<r8_safe_access_sig_rd::R8_SAFE_ACCESS_SIG_RD_SPEC>;
+#[doc = "R8_SAFE_ACCESS_SIG_RD Register safe accessing"]
+pub mod r8_safe_access_sig_rd;
+#[doc = "R8_SAFE_ACCESS_SIG_WR (w) register accessor: an alias for `Reg<R8_SAFE_ACCESS_SIG_WR_SPEC>`"]
+pub type R8_SAFE_ACCESS_SIG_WR = crate::Reg<r8_safe_access_sig_wr::R8_SAFE_ACCESS_SIG_WR_SPEC>;
+#[doc = "safe accessing sign register, must write 0x57 then 0xA8 to enter safe accessing mode"]
+pub mod r8_safe_access_sig_wr;
+#[doc = "R8_CHIP_ID (r) register accessor: an alias for `Reg<R8_CHIP_ID_SPEC>`"]
+pub type R8_CHIP_ID = crate::Reg<r8_chip_id::R8_CHIP_ID_SPEC>;
+#[doc = "RF, chip ID register, always is ID_CH57*"]
+pub mod r8_chip_id;
+#[doc = "R8_SAFE_ACCESS_ID (r) register accessor: an alias for `Reg<R8_SAFE_ACCESS_ID_SPEC>`"]
+pub type R8_SAFE_ACCESS_ID = crate::Reg<r8_safe_access_id::R8_SAFE_ACCESS_ID_SPEC>;
+#[doc = "RF, safe accessing ID register, always 0x04"]
+pub mod r8_safe_access_id;
+#[doc = "R8_WDOG_COUNT (rw) register accessor: an alias for `Reg<R8_WDOG_COUNT_SPEC>`"]
+pub type R8_WDOG_COUNT = crate::Reg<r8_wdog_count::R8_WDOG_COUNT_SPEC>;
+#[doc = "RW, watch-dog count, count by clock frequency Fsys/131072"]
+pub mod r8_wdog_count;
+#[doc = "R8_RESET_STATUS (rw) register accessor: an alias for `Reg<R8_RESET_STATUS_SPEC>`"]
+pub type R8_RESET_STATUS = crate::Reg<r8_reset_status::R8_RESET_STATUS_SPEC>;
+#[doc = "RWA, reset status, SAM"]
+pub mod r8_reset_status;
+#[doc = "R8_GLOB_CFG_INFO (r) register accessor: an alias for `Reg<R8_GLOB_CFG_INFO_SPEC>`"]
+pub type R8_GLOB_CFG_INFO = crate::Reg<r8_glob_cfg_info::R8_GLOB_CFG_INFO_SPEC>;
+#[doc = "RO, global configuration information and status"]
+pub mod r8_glob_cfg_info;
+#[doc = "R8_RST_WDOG_CTRL (rw) register accessor: an alias for `Reg<R8_RST_WDOG_CTRL_SPEC>`"]
+pub type R8_RST_WDOG_CTRL = crate::Reg<r8_rst_wdog_ctrl::R8_RST_WDOG_CTRL_SPEC>;
+#[doc = "RWA, reset and watch-dog control, SAM"]
+pub mod r8_rst_wdog_ctrl;
+#[doc = "R8_GLOB_RESET_KEEP (rw) register accessor: an alias for `Reg<R8_GLOB_RESET_KEEP_SPEC>`"]
+pub type R8_GLOB_RESET_KEEP = crate::Reg<r8_glob_reset_keep::R8_GLOB_RESET_KEEP_SPEC>;
+#[doc = "RW, value keeper during global reset"]
+pub mod r8_glob_reset_keep;
+#[doc = "R8_CFG_FLASH (rw) register accessor: an alias for `Reg<R8_CFG_FLASH_SPEC>`"]
+pub type R8_CFG_FLASH = crate::Reg<r8_cfg_flash::R8_CFG_FLASH_SPEC>;
+#[doc = "RWA, Flash ROM configure register"]
+pub mod r8_cfg_flash;
+#[doc = "R8_PLL_CONFIG (rw) register accessor: an alias for `Reg<R8_PLL_CONFIG_SPEC>`"]
+pub type R8_PLL_CONFIG = crate::Reg<r8_pll_config::R8_PLL_CONFIG_SPEC>;
+#[doc = "RWA, PLL configuration control, SAM"]
+pub mod r8_pll_config;
+#[doc = "R16_INT32M_CALIB (rw) register accessor: an alias for `Reg<R16_INT32M_CALIB_SPEC>`"]
+pub type R16_INT32M_CALIB = crate::Reg<r16_int32m_calib::R16_INT32M_CALIB_SPEC>;
+#[doc = "RWA, internal 32MHz oscillator tune control, SAM"]
+pub mod r16_int32m_calib;
+#[doc = "R8_XT32M_TUNE (rw) register accessor: an alias for `Reg<R8_XT32M_TUNE_SPEC>`"]
+pub type R8_XT32M_TUNE = crate::Reg<r8_xt32m_tune::R8_XT32M_TUNE_SPEC>;
+#[doc = "RWA, external 32MHz oscillator tune control, SAM"]
+pub mod r8_xt32m_tune;
+#[doc = "R16_OSC_CAL_CNT (r) register accessor: an alias for `Reg<R16_OSC_CAL_CNT_SPEC>`"]
+pub type R16_OSC_CAL_CNT = crate::Reg<r16_osc_cal_cnt::R16_OSC_CAL_CNT_SPEC>;
+#[doc = "RO, system clock count value for 32KHz 5 cycles"]
+pub mod r16_osc_cal_cnt;
+#[doc = "R8_OSC_CAL_CTRL (rw) register accessor: an alias for `Reg<R8_OSC_CAL_CTRL_SPEC>`"]
+pub type R8_OSC_CAL_CTRL = crate::Reg<r8_osc_cal_ctrl::R8_OSC_CAL_CTRL_SPEC>;
+#[doc = "RWA, oscillator frequency calibration control, SAM"]
+pub mod r8_osc_cal_ctrl;
+#[doc = "R8_ADC_CHANNEL (rw) register accessor: an alias for `Reg<R8_ADC_CHANNEL_SPEC>`"]
+pub type R8_ADC_CHANNEL = crate::Reg<r8_adc_channel::R8_ADC_CHANNEL_SPEC>;
+#[doc = "RW, ADC input channel selection"]
+pub mod r8_adc_channel;
+#[doc = "R8_ADC_CFG (rw) register accessor: an alias for `Reg<R8_ADC_CFG_SPEC>`"]
+pub type R8_ADC_CFG = crate::Reg<r8_adc_cfg::R8_ADC_CFG_SPEC>;
+#[doc = "RW, ADC configure"]
+pub mod r8_adc_cfg;
+#[doc = "R8_ADC_CONVERT (rw) register accessor: an alias for `Reg<R8_ADC_CONVERT_SPEC>`"]
+pub type R8_ADC_CONVERT = crate::Reg<r8_adc_convert::R8_ADC_CONVERT_SPEC>;
+#[doc = "RW, ADC convert control"]
+pub mod r8_adc_convert;
+#[doc = "R8_TEM_SENSOR (rw) register accessor: an alias for `Reg<R8_TEM_SENSOR_SPEC>`"]
+pub type R8_TEM_SENSOR = crate::Reg<r8_tem_sensor::R8_TEM_SENSOR_SPEC>;
+#[doc = "RW, temperature sensor control"]
+pub mod r8_tem_sensor;
+#[doc = "R16_ADC_DATA (r) register accessor: an alias for `Reg<R16_ADC_DATA_SPEC>`"]
+pub type R16_ADC_DATA = crate::Reg<r16_adc_data::R16_ADC_DATA_SPEC>;
+#[doc = "RO, ADC data"]
+pub mod r16_adc_data;
+#[doc = "R8_ADC_INT_FLAG (r) register accessor: an alias for `Reg<R8_ADC_INT_FLAG_SPEC>`"]
+pub type R8_ADC_INT_FLAG = crate::Reg<r8_adc_int_flag::R8_ADC_INT_FLAG_SPEC>;
+#[doc = "RO, ADC interrupt flag register"]
+pub mod r8_adc_int_flag;
+#[doc = "R8_TKEY_CNT (w) register accessor: an alias for `Reg<R8_TKEY_CNT_SPEC>`"]
+pub type R8_TKEY_CNT = crate::Reg<r8_tkey_cnt::R8_TKEY_CNT_SPEC>;
+#[doc = "WO, Touch-key charge and discharge count"]
+pub mod r8_tkey_cnt;
+#[doc = "R16_PA_INT_EN (rw) register accessor: an alias for `Reg<R16_PA_INT_EN_SPEC>`"]
+pub type R16_PA_INT_EN = crate::Reg<r16_pa_int_en::R16_PA_INT_EN_SPEC>;
+#[doc = "RW, GPIO PA interrupt enable"]
+pub mod r16_pa_int_en;
+#[doc = "R16_PB_INT_EN (rw) register accessor: an alias for `Reg<R16_PB_INT_EN_SPEC>`"]
+pub type R16_PB_INT_EN = crate::Reg<r16_pb_int_en::R16_PB_INT_EN_SPEC>;
+#[doc = "RW, GPIO PB interrupt enable"]
+pub mod r16_pb_int_en;
+#[doc = "R16_PA_INT_MODE (rw) register accessor: an alias for `Reg<R16_PA_INT_MODE_SPEC>`"]
+pub type R16_PA_INT_MODE = crate::Reg<r16_pa_int_mode::R16_PA_INT_MODE_SPEC>;
+#[doc = "RW, GPIO PA interrupt mode: 0=level action, 1=edge action"]
+pub mod r16_pa_int_mode;
+#[doc = "R16_PB_INT_MODE__R8_SLV_RD_STAT (rw) register accessor: an alias for `Reg<R16_PB_INT_MODE__R8_SLV_RD_STAT_SPEC>`"]
+pub type R16_PB_INT_MODE__R8_SLV_RD_STAT =
+    crate::Reg<r16_pb_int_mode__r8_slv_rd_stat::R16_PB_INT_MODE__R8_SLV_RD_STAT_SPEC>;
+#[doc = "RW, GPIO PB interrupt mode: 0=level action, 1=edge action;RW, status for parallel slave read"]
+pub mod r16_pb_int_mode__r8_slv_rd_stat;
+#[doc = "R8_SLV_WR_DATA (rw) register accessor: an alias for `Reg<R8_SLV_WR_DATA_SPEC>`"]
+pub type R8_SLV_WR_DATA = crate::Reg<r8_slv_wr_data::R8_SLV_WR_DATA_SPEC>;
+#[doc = "RW, data or command from parallel slave write"]
+pub mod r8_slv_wr_data;
+#[doc = "R16_PA_INT_IF (rw) register accessor: an alias for `Reg<R16_PA_INT_IF_SPEC>`"]
+pub type R16_PA_INT_IF = crate::Reg<r16_pa_int_if::R16_PA_INT_IF_SPEC>;
+#[doc = "RW1, GPIO PA interrupt flag"]
+pub mod r16_pa_int_if;
+#[doc = "R16_PB_INT_IF (rw) register accessor: an alias for `Reg<R16_PB_INT_IF_SPEC>`"]
+pub type R16_PB_INT_IF = crate::Reg<r16_pb_int_if::R16_PB_INT_IF_SPEC>;
+#[doc = "RW1, GPIO PB interrupt flag"]
+pub mod r16_pb_int_if;
+#[doc = "R32_PA_DIR (rw) register accessor: an alias for `Reg<R32_PA_DIR_SPEC>`"]
+pub type R32_PA_DIR = crate::Reg<r32_pa_dir::R32_PA_DIR_SPEC>;
+#[doc = "RW, GPIO PA I/O direction: 0=in, 1=out"]
+pub mod r32_pa_dir;
+#[doc = "R32_PA_PIN (r) register accessor: an alias for `Reg<R32_PA_PIN_SPEC>`"]
+pub type R32_PA_PIN = crate::Reg<r32_pa_pin::R32_PA_PIN_SPEC>;
+#[doc = "RO, GPIO PA input"]
+pub mod r32_pa_pin;
+#[doc = "R32_PA_OUT (rw) register accessor: an alias for `Reg<R32_PA_OUT_SPEC>`"]
+pub type R32_PA_OUT = crate::Reg<r32_pa_out::R32_PA_OUT_SPEC>;
+#[doc = "RW, GPIO PA output"]
+pub mod r32_pa_out;
+#[doc = "R32_PA_CLR (rw) register accessor: an alias for `Reg<R32_PA_CLR_SPEC>`"]
+pub type R32_PA_CLR = crate::Reg<r32_pa_clr::R32_PA_CLR_SPEC>;
+#[doc = "WZ, GPIO PA clear output: 0=keep, 1=clear"]
+pub mod r32_pa_clr;
+#[doc = "R32_PA_PU (rw) register accessor: an alias for `Reg<R32_PA_PU_SPEC>`"]
+pub type R32_PA_PU = crate::Reg<r32_pa_pu::R32_PA_PU_SPEC>;
+#[doc = "RW, GPIO PA pullup resistance enable"]
+pub mod r32_pa_pu;
+#[doc = "R32_PA_PD_DRV (rw) register accessor: an alias for `Reg<R32_PA_PD_DRV_SPEC>`"]
+pub type R32_PA_PD_DRV = crate::Reg<r32_pa_pd_drv::R32_PA_PD_DRV_SPEC>;
+#[doc = "RW, PA pulldown for input or PA driving capability for output"]
+pub mod r32_pa_pd_drv;
+#[doc = "R32_PB_DIR (rw) register accessor: an alias for `Reg<R32_PB_DIR_SPEC>`"]
+pub type R32_PB_DIR = crate::Reg<r32_pb_dir::R32_PB_DIR_SPEC>;
+#[doc = "RW, GPIO PB I/O direction: 0=in, 1=out"]
+pub mod r32_pb_dir;
+#[doc = "R32_PB_PIN (r) register accessor: an alias for `Reg<R32_PB_PIN_SPEC>`"]
+pub type R32_PB_PIN = crate::Reg<r32_pb_pin::R32_PB_PIN_SPEC>;
+#[doc = "RO, GPIO PB input"]
+pub mod r32_pb_pin;
+#[doc = "R32_PB_OUT__R8_SLV_RD_DATA (rw) register accessor: an alias for `Reg<R32_PB_OUT__R8_SLV_RD_DATA_SPEC>`"]
+pub type R32_PB_OUT__R8_SLV_RD_DATA =
+    crate::Reg<r32_pb_out__r8_slv_rd_data::R32_PB_OUT__R8_SLV_RD_DATA_SPEC>;
+#[doc = "RW, GPIO PB output;RW, data for parallel slave read"]
+pub mod r32_pb_out__r8_slv_rd_data;
+#[doc = "R32_PB_CLR (rw) register accessor: an alias for `Reg<R32_PB_CLR_SPEC>`"]
+pub type R32_PB_CLR = crate::Reg<r32_pb_clr::R32_PB_CLR_SPEC>;
+#[doc = "WZ, GPIO PB clear output: 0=keep, 1=clear"]
+pub mod r32_pb_clr;
+#[doc = "R32_PB_PU (rw) register accessor: an alias for `Reg<R32_PB_PU_SPEC>`"]
+pub type R32_PB_PU = crate::Reg<r32_pb_pu::R32_PB_PU_SPEC>;
+#[doc = "RW, GPIO PB pullup resistance enable"]
+pub mod r32_pb_pu;
+#[doc = "R32_PB_PD_DRV (rw) register accessor: an alias for `Reg<R32_PB_PD_DRV_SPEC>`"]
+pub type R32_PB_PD_DRV = crate::Reg<r32_pb_pd_drv::R32_PB_PD_DRV_SPEC>;
+#[doc = "RW, PB pulldown for input or PB driving capability for output"]
+pub mod r32_pb_pd_drv;

src/sys/r16_adc_data.rs

@@ -0,0 +1,37 @@
+#[doc = "Register `R16_ADC_DATA` reader"]
+pub struct R(crate::R<R16_ADC_DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_ADC_DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_ADC_DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_ADC_DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `RB_ADC_DATA` reader - RO, ADC conversion data"]
+pub type RB_ADC_DATA_R = crate::FieldReader<u16, u16>;
+impl R {
+    #[doc = "Bits 0:11 - RO, ADC conversion data"]
+    #[inline(always)]
+    pub fn rb_adc_data(&self) -> RB_ADC_DATA_R {
+        RB_ADC_DATA_R::new(self.bits & 0x0fff)
+    }
+}
+#[doc = "RO, ADC data\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_adc_data](index.html) module"]
+pub struct R16_ADC_DATA_SPEC;
+impl crate::RegisterSpec for R16_ADC_DATA_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_adc_data::R](R) reader structure"]
+impl crate::Readable for R16_ADC_DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets R16_ADC_DATA to value 0"]
+impl crate::Resettable for R16_ADC_DATA_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/sys/r16_clk_sys_cfg.rs

@@ -0,0 +1,120 @@
+#[doc = "Register `R16_CLK_SYS_CFG` reader"]
+pub struct R(crate::R<R16_CLK_SYS_CFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_CLK_SYS_CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_CLK_SYS_CFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_CLK_SYS_CFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_CLK_SYS_CFG` writer"]
+pub struct W(crate::W<R16_CLK_SYS_CFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_CLK_SYS_CFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_CLK_SYS_CFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_CLK_SYS_CFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_CLK_PLL_DIV` reader - RWA, output clock divider from PLL or CK32M"]
+pub type RB_CLK_PLL_DIV_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_CLK_PLL_DIV` writer - RWA, output clock divider from PLL or CK32M"]
+pub type RB_CLK_PLL_DIV_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u16, R16_CLK_SYS_CFG_SPEC, u8, u8, 5, O>;
+#[doc = "Field `RB_CLK_SYS_MOD` reader - RWA, system clock source mode: 00=divided from 32MHz, 01=divided from PLL-480MHz, 10=directly from 32MHz, 11=directly from 32KHz"]
+pub type RB_CLK_SYS_MOD_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RB_CLK_SYS_MOD` writer - RWA, system clock source mode: 00=divided from 32MHz, 01=divided from PLL-480MHz, 10=directly from 32MHz, 11=directly from 32KHz"]
+pub type RB_CLK_SYS_MOD_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u16, R16_CLK_SYS_CFG_SPEC, u8, u8, 2, O>;
+#[doc = "Field `RB_CLK_OSC32M_XT` reader - RWA, 32MHz clock source selection: 0=internal 32MHz oscillator, 1=external 32MHz oscillator"]
+pub type RB_CLK_OSC32M_XT_R = crate::BitReader<bool>;
+#[doc = "Field `RB_CLK_OSC32M_XT` writer - RWA, 32MHz clock source selection: 0=internal 32MHz oscillator, 1=external 32MHz oscillator"]
+pub type RB_CLK_OSC32M_XT_W<'a, const O: u8> =
+    crate::BitWriter<'a, u16, R16_CLK_SYS_CFG_SPEC, bool, O>;
+#[doc = "Field `RB_XO_DI` reader - RO, X32MO input status sample value"]
+pub type RB_XO_DI_R = crate::BitReader<bool>;
+impl R {
+    #[doc = "Bits 0:4 - RWA, output clock divider from PLL or CK32M"]
+    #[inline(always)]
+    pub fn rb_clk_pll_div(&self) -> RB_CLK_PLL_DIV_R {
+        RB_CLK_PLL_DIV_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bits 6:7 - RWA, system clock source mode: 00=divided from 32MHz, 01=divided from PLL-480MHz, 10=directly from 32MHz, 11=directly from 32KHz"]
+    #[inline(always)]
+    pub fn rb_clk_sys_mod(&self) -> RB_CLK_SYS_MOD_R {
+        RB_CLK_SYS_MOD_R::new(((self.bits >> 6) & 3) as u8)
+    }
+    #[doc = "Bit 9 - RWA, 32MHz clock source selection: 0=internal 32MHz oscillator, 1=external 32MHz oscillator"]
+    #[inline(always)]
+    pub fn rb_clk_osc32m_xt(&self) -> RB_CLK_OSC32M_XT_R {
+        RB_CLK_OSC32M_XT_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 15 - RO, X32MO input status sample value"]
+    #[inline(always)]
+    pub fn rb_xo_di(&self) -> RB_XO_DI_R {
+        RB_XO_DI_R::new(((self.bits >> 15) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - RWA, output clock divider from PLL or CK32M"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_clk_pll_div(&mut self) -> RB_CLK_PLL_DIV_W<0> {
+        RB_CLK_PLL_DIV_W::new(self)
+    }
+    #[doc = "Bits 6:7 - RWA, system clock source mode: 00=divided from 32MHz, 01=divided from PLL-480MHz, 10=directly from 32MHz, 11=directly from 32KHz"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_clk_sys_mod(&mut self) -> RB_CLK_SYS_MOD_W<6> {
+        RB_CLK_SYS_MOD_W::new(self)
+    }
+    #[doc = "Bit 9 - RWA, 32MHz clock source selection: 0=internal 32MHz oscillator, 1=external 32MHz oscillator"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_clk_osc32m_xt(&mut self) -> RB_CLK_OSC32M_XT_W<9> {
+        RB_CLK_OSC32M_XT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RWA, system clock configuration, SAM\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_clk_sys_cfg](index.html) module"]
+pub struct R16_CLK_SYS_CFG_SPEC;
+impl crate::RegisterSpec for R16_CLK_SYS_CFG_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_clk_sys_cfg::R](R) reader structure"]
+impl crate::Readable for R16_CLK_SYS_CFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_clk_sys_cfg::W](W) writer structure"]
+impl crate::Writable for R16_CLK_SYS_CFG_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_CLK_SYS_CFG to value 0"]
+impl crate::Resettable for R16_CLK_SYS_CFG_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/sys/r16_int32k_tune.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `R16_INT32K_TUNE` reader"]
+pub struct R(crate::R<R16_INT32K_TUNE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_INT32K_TUNE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_INT32K_TUNE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_INT32K_TUNE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_INT32K_TUNE` writer"]
+pub struct W(crate::W<R16_INT32K_TUNE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_INT32K_TUNE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_INT32K_TUNE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_INT32K_TUNE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RB_INT32K_TUNE` reader - RWA, internal 32KHz oscillator frequency tune"]
+pub type RB_INT32K_TUNE_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `RB_INT32K_TUNE` writer - RWA, internal 32KHz oscillator frequency tune"]
+pub type RB_INT32K_TUNE_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u16, R16_INT32K_TUNE_SPEC, u16, u16, 10, O>;
+impl R {
+    #[doc = "Bits 0:9 - RWA, internal 32KHz oscillator frequency tune"]
+    #[inline(always)]
+    pub fn rb_int32k_tune(&self) -> RB_INT32K_TUNE_R {
+        RB_INT32K_TUNE_R::new(self.bits & 0x03ff)
+    }
+}
+impl W {
+    #[doc = "Bits 0:9 - RWA, internal 32KHz oscillator frequency tune"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rb_int32k_tune(&mut self) -> RB_INT32K_TUNE_W<0> {
+        RB_INT32K_TUNE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RWA, internal 32KHz oscillator tune control, SAM\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_int32k_tune](index.html) module"]
+pub struct R16_INT32K_TUNE_SPEC;
+impl crate::RegisterSpec for R16_INT32K_TUNE_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_int32k_tune::R](R) reader structure"]
+impl crate::Readable for R16_INT32K_TUNE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_int32k_tune::W](W) writer structure"]
+impl crate::Writable for R16_INT32K_TUNE_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_INT32K_TUNE to value 0"]
+impl crate::Resettable for R16_INT32K_TUNE_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

src/sys/r16_int32m_calib.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `R16_INT32M_CALIB` reader"]
+pub struct R(crate::R<R16_INT32M_CALIB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<R16_INT32M_CALIB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<R16_INT32M_CALIB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<R16_INT32M_CALIB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `R16_INT32M_CALIB` writer"]
+pub struct W(crate::W<R16_INT32M_CALIB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<R16_INT32M_CALIB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<R16_INT32M_CALIB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<R16_INT32M_CALIB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RWA, internal 32MHz oscillator tune control, SAM\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r16_int32m_calib](index.html) module"]
+pub struct R16_INT32M_CALIB_SPEC;
+impl crate::RegisterSpec for R16_INT32M_CALIB_SPEC {
+    type Ux = u16;
+}
+#[doc = "`read()` method returns [r16_int32m_calib::R](R) reader structure"]
+impl crate::Readable for R16_INT32M_CALIB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [r16_int32m_calib::W](W) writer structure"]
+impl crate::Writable for R16_INT32M_CALIB_SPEC {
+    type Writer = W;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets R16_INT32M_CALIB to value 0"]
+impl crate::Resettable for R16_INT32M_CALIB_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}