Multiple fixes.
* Removed obsolete openocd config, use -c 'set WORKAREASIZE 0' on devices except ST-LINK and CMSIS-DAP debugger. * Removed logger functions due to non-reentrant logger API.
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17F01E106F9F5E0A
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@ -91,9 +91,9 @@
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#define configTICK_SOURCE FREERTOS_USE_RTC
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#define configUSE_PREEMPTION 1
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#define configUSE_PREEMPTION 1
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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#define configUSE_TICKLESS_IDLE 1
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#define configUSE_TICKLESS_IDLE 1
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#define configUSE_TICKLESS_IDLE_SIMPLE_DEBUG 1 /* See into vPortSuppressTicksAndSleep source code for explanation */
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#define configCPU_CLOCK_HZ ( SystemCoreClock )
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#define configTICK_RATE_HZ 1000
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@ -261,7 +261,7 @@
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// <e> UART_CONFIG_LOG_ENABLED - Enables logging in the module.
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//==========================================================
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#ifndef UART_CONFIG_LOG_ENABLED
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#define UART_CONFIG_LOG_ENABLED 1
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#define UART_CONFIG_LOG_ENABLED 0
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#endif
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#if UART_CONFIG_LOG_ENABLED
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// <o> UART_CONFIG_LOG_LEVEL - Default Severity level
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@ -273,7 +273,7 @@
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// <4=> Debug
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#ifndef UART_CONFIG_LOG_LEVEL
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#define UART_CONFIG_LOG_LEVEL 4
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#define UART_CONFIG_LOG_LEVEL 3
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#endif
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// <o> UART_CONFIG_INFO_COLOR - ANSI escape code prefix.
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@ -289,7 +289,7 @@
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// <8=> White
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#ifndef UART_CONFIG_INFO_COLOR
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#define UART_CONFIG_INFO_COLOR 3
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#define UART_CONFIG_INFO_COLOR 0
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#endif
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// <o> UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix.
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@ -305,7 +305,7 @@
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// <8=> White
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#ifndef UART_CONFIG_DEBUG_COLOR
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#define UART_CONFIG_DEBUG_COLOR 6
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#define UART_CONFIG_DEBUG_COLOR 0
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#endif
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#endif //UART_CONFIG_LOG_ENABLED
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@ -505,7 +505,7 @@
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// <268435456=> 57600 baud
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#ifndef NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE
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#define NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE 30924800
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#define NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE 251658240
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#endif
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// <o> NRF_LOG_BACKEND_SERIAL_UART_TX_PIN - UART TX pin
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9
main.c
9
main.c
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@ -8,10 +8,13 @@
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#include "nordic_common.h"
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#include "sdk_errors.h"
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#include "app_error.h"
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#include "nrf_log.h"
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#include "nrf_log_ctrl.h"
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#include "FreeRTOS.h"
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#include "task.h"
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#include "timers.h"
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#include "semphr.h"
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#define APP_TIMER_PRESCALER 0
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#define APP_TIMER_OP_QUEUE_SIZE 4
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@ -20,7 +23,7 @@ TaskHandle_t xTaskBlinkLEDHandle = NULL;
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void vTaskBlinkLED(void *pvParameters);
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TimerHandle_t xTimerBlinkAnotherLEDHandle = NULL;
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void xTimerBlinkAnotherLEDCallback(void *pvParameters);
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void xTimerBlinkAnotherLEDCallback(TimerHandle_t xTimer);
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int main(void) {
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ret_code_t err_code;
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@ -53,7 +56,7 @@ void vTaskBlinkLED(void *pvParameters) {
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}
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}
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void xTimerBlinkAnotherLEDCallback(void *pvParameters) {
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UNUSED_VARIABLE(pvParameters);
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void xTimerBlinkAnotherLEDCallback(TimerHandle_t xTimer) {
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UNUSED_VARIABLE(xTimer);
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bsp_board_led_invert(BSP_BOARD_LED_1);
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}
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61
nrf51.cfg
61
nrf51.cfg
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@ -1,61 +0,0 @@
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#
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# script for Nordic nRF51 series, a Cortex-M0 chip
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#
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME nrf51
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 16kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x0bb11477
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}
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swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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if {![using_hla]} {
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# The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
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cortex_m reset_config sysresetreq
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}
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flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME
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flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
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#
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# The chip should start up from internal 16Mhz RC, so setting adapter
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# clock to 1Mhz should be OK
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#
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adapter speed 1000
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proc enable_all_ram {} {
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# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
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# are reliably enabled after reset on some revisions (contrary to spec.) So after
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# resetting we enable all banks via the RAMON register
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mww 0x40000524 0xF
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}
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$_TARGETNAME configure -event reset-end { enable_all_ram }
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