2022-06-26 22:53:35 +00:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2010-07-19 11:22:18 +00:00
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/***************************************************************************
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* Copyright (C) 2010 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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***************************************************************************/
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/*
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* NAND controller interface for Nuvoton NUC910
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*/
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2015-09-21 19:07:46 +00:00
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#ifndef OPENOCD_FLASH_NAND_NUC910_H
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#define OPENOCD_FLASH_NAND_NUC910_H
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2010-07-19 11:22:18 +00:00
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#define NUC910_FMICSR 0xB000D000
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#define NUC910_SMCSR 0xB000D0A0
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#define NUC910_SMTCR 0xB000D0A4
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#define NUC910_SMIER 0xB000D0A8
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#define NUC910_SMISR 0xB000D0AC
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#define NUC910_SMCMD 0xB000D0B0
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#define NUC910_SMADDR 0xB000D0B4
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#define NUC910_SMDATA 0xB000D0B8
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#define NUC910_SMECC0 0xB000D0BC
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#define NUC910_SMECC1 0xB000D0C0
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#define NUC910_SMECC2 0xB000D0C4
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#define NUC910_SMECC3 0xB000D0C8
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#define NUC910_ECC4ST 0xB000D114
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/* Global Control and Status Register (FMICSR) */
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#define NUC910_FMICSR_SM_EN (1<<3)
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/* NAND Flash Address Port Register (SMADDR) */
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#define NUC910_SMADDR_EOA (1<<31)
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/* NAND Flash Control and Status Register (SMCSR) */
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#define NUC910_SMCSR_PSIZE (1<<3)
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#define NUC910_SMCSR_DBW (1<<4)
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/* NAND Flash Interrupt Status Register (SMISR) */
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#define NUC910_SMISR_ECC_IF (1<<2)
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#define NUC910_SMISR_RB_ (1<<18)
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/* ECC4 Correction Status (ECC4ST) */
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2015-09-21 19:07:46 +00:00
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#endif /* OPENOCD_FLASH_NAND_NUC910_H */
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