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openocd/tcl/cpld/jtagspi.cfg

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tcl: add SPDX tag For historical reasons, no license information was added to the tcl files. This makes trivial adding the SPDX tag through script: fgrep -rL SPDX tcl | while read a;do \ sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n }' $a;done With no specific license information from the author, let's extend the OpenOCD project license GPL-2.0-or-later to the files. Change-Id: Ief3da306a6e1978de7dfb8f552f9ff23151f9944 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7030 Tested-by: jenkins
2022-06-12 21:51:51 +00:00
# SPDX-License-Identifier: GPL-2.0-or-later
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
set _USER1 0x02
if { [info exists JTAGSPI_IR] } {
set _JTAGSPI_IR $JTAGSPI_IR
} else {
set _JTAGSPI_IR $_USER1
}
if { [info exists TARGETNAME] } {
set _TARGETNAME $TARGETNAME
} else {
set _TARGETNAME $_CHIPNAME.proxy
}
if { [info exists FLASHNAME] } {
set _FLASHNAME $FLASHNAME
} else {
set _FLASHNAME $_CHIPNAME.spi
}
target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
proc jtagspi_init {chain_id proxy_bit} {
# load proxy bitstream $proxy_bit and probe spi flash
global _FLASHNAME
pld load $chain_id $proxy_bit
reset halt
flash probe $_FLASHNAME
}
proc jtagspi_program {bin addr} {
# write and verify binary file $bin at offset $addr
global _FLASHNAME
flash write_image erase $bin $addr
flash verify_bank $_FLASHNAME $bin $addr
}