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helper/align.h: use it 

Use the new helper to make the code more readable.

Change-Id: I11b2a79dbc6f93f6cfde382bcc00dd7ff710d908
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6375
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
This commit is contained in:
Antonio Borneo 2021-05-14 00:48:31 +02:00
parent 9544cd653d
commit 08a0cfdeeb
4 changed files with 12 additions and 8 deletions
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3
src/flash/nor/stm32l4x.c
View File

@ -24,6 +24,7 @@
#endif #endif
#include "imp.h" #include "imp.h"
#include <helper/align.h>
#include <helper/binarybuffer.h> #include <helper/binarybuffer.h>
#include <target/algorithm.h> #include <target/algorithm.h>
#include <target/armv7m.h> #include <target/armv7m.h>
@ -1591,7 +1592,7 @@ static int stm32l4_probe(struct flash_bank *bank)
* max_flash_size is always power of two, so max_pages too * max_flash_size is always power of two, so max_pages too
*/ */
uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb; uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
assert((max_pages & (max_pages - 1)) == 0); assert(IS_PWR_OF_2(max_pages));
/* in dual bank mode number of pages is doubled, but extra bit is bank selection */ /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1); stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);

5
src/flash/nor/xmc1xxx.c
View File

@ -11,6 +11,7 @@
#endif #endif
#include "imp.h" #include "imp.h"
#include <helper/align.h>
#include <helper/binarybuffer.h> #include <helper/binarybuffer.h>
#include <target/algorithm.h> #include <target/algorithm.h>
#include <target/armv7m.h> #include <target/armv7m.h>
@ -256,12 +257,12 @@ static int xmc1xxx_write(struct flash_bank *bank, const uint8_t *buffer,
LOG_DEBUG("Infineon XMC1000 write at 0x%08" PRIx32 " (%" PRIu32 " bytes)", LOG_DEBUG("Infineon XMC1000 write at 0x%08" PRIx32 " (%" PRIu32 " bytes)",
offset, byte_count); offset, byte_count);
if (offset & (NVM_BLOCK_SIZE - 1)) { if (!IS_ALIGNED(offset, NVM_BLOCK_SIZE)) {
LOG_ERROR("offset 0x%" PRIx32 " breaks required block alignment", LOG_ERROR("offset 0x%" PRIx32 " breaks required block alignment",
offset); offset);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT; return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
} }
if (byte_count & (NVM_BLOCK_SIZE - 1)) { if (!IS_ALIGNED(byte_count, NVM_BLOCK_SIZE)) {
LOG_WARNING("length %" PRIu32 " is not block aligned, rounding up", LOG_WARNING("length %" PRIu32 " is not block aligned, rounding up",
byte_count); byte_count);
} }

3
src/target/mips32_pracc.c
View File

@ -68,6 +68,7 @@
#include "config.h" #include "config.h"
#endif #endif
#include <helper/align.h>
#include <helper/time_support.h> #include <helper/time_support.h>
#include "mips32.h" #include "mips32.h"
@ -658,7 +659,7 @@ static int mips32_pracc_synchronize_cache(struct mips_ejtag *ejtag_info,
goto exit; /* Nothing to do */ goto exit; /* Nothing to do */
/* make sure clsiz is power of 2 */ /* make sure clsiz is power of 2 */
if (clsiz & (clsiz - 1)) { if (!IS_PWR_OF_2(clsiz)) {
LOG_DEBUG("clsiz must be power of 2"); LOG_DEBUG("clsiz must be power of 2");
ctx.retval = ERROR_FAIL; ctx.retval = ERROR_FAIL;
goto exit; goto exit;

9
src/target/target.c
View File

@ -41,6 +41,7 @@
#include "config.h" #include "config.h"
#endif #endif
#include <helper/align.h>
#include <helper/time_support.h> #include <helper/time_support.h>
#include <jtag/jtag.h> #include <jtag/jtag.h>
#include <flash/nor/core.h> #include <flash/nor/core.h>
@ -1004,7 +1005,7 @@ int target_run_flash_async_algorithm(struct target *target,
uint32_t rp = fifo_start_addr; uint32_t rp = fifo_start_addr;
/* validate block_size is 2^n */ /* validate block_size is 2^n */
assert(!block_size || !(block_size & (block_size - 1))); assert(IS_PWR_OF_2(block_size));
retval = target_write_u32(target, wp_addr, wp); retval = target_write_u32(target, wp_addr, wp);
if (retval != ERROR_OK) if (retval != ERROR_OK)
@ -1042,7 +1043,7 @@ int target_run_flash_async_algorithm(struct target *target,
break; break;
} }
if (((rp - fifo_start_addr) & (block_size - 1)) || rp < fifo_start_addr || rp >= fifo_end_addr) { if (!IS_ALIGNED(rp - fifo_start_addr, block_size) || rp < fifo_start_addr || rp >= fifo_end_addr) {
LOG_ERROR("corrupted fifo read pointer 0x%" PRIx32, rp); LOG_ERROR("corrupted fifo read pointer 0x%" PRIx32, rp);
break; break;
} }
@ -1157,7 +1158,7 @@ int target_run_read_async_algorithm(struct target *target,
uint32_t rp = fifo_start_addr; uint32_t rp = fifo_start_addr;
/* validate block_size is 2^n */ /* validate block_size is 2^n */
assert(!block_size || !(block_size & (block_size - 1))); assert(IS_PWR_OF_2(block_size));
retval = target_write_u32(target, wp_addr, wp); retval = target_write_u32(target, wp_addr, wp);
if (retval != ERROR_OK) if (retval != ERROR_OK)
@ -1194,7 +1195,7 @@ int target_run_read_async_algorithm(struct target *target,
break; break;
} }
if (((wp - fifo_start_addr) & (block_size - 1)) || wp < fifo_start_addr || wp >= fifo_end_addr) { if (!IS_ALIGNED(wp - fifo_start_addr, block_size) || wp < fifo_start_addr || wp >= fifo_end_addr) {
LOG_ERROR("corrupted fifo write pointer 0x%" PRIx32, wp); LOG_ERROR("corrupted fifo write pointer 0x%" PRIx32, wp);
break; break;
} }