ARM: use <target/arm.h> not armv4_5.h
Move most declarations in <target/armv4_5.h> to <target/arm.h> and update users. What's left in the older file is stuff that I think should be removed ... the old register cache access stuff, which makes it awkward to support microcontroller profile (Cortex-M) cores. The armv4_5_run_algorithm() declaration was moved too, even though it's not yet as generic as it probably ought to be. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
parent
0529c14bfe
commit
0a1b7dcfc4
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@ -27,7 +27,7 @@
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#include "core.h"
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#include "arm_io.h"
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#include <helper/binarybuffer.h>
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#include <target/armv4_5.h>
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#include <target/arm.h>
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#include <target/algorithm.h>
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@ -28,7 +28,7 @@
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#include "imp.h"
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#include "arm_io.h"
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#include <target/armv4_5.h>
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#include <target/arm.h>
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struct orion_nand_controller
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@ -27,7 +27,7 @@
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#include <helper/binarybuffer.h>
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#include <helper/time_support.h>
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#include <target/algorithm.h>
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#include <target/armv4_5.h>
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#include <target/arm.h>
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static int aduc702x_build_sector_list(struct flash_bank *bank);
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@ -26,7 +26,7 @@
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#include "imp.h"
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#include "cfi.h"
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#include "non_cfi.h"
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#include <target/armv4_5.h>
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#include <target/arm.h>
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#include <helper/binarybuffer.h>
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#include <target/algorithm.h>
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@ -26,7 +26,7 @@
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#include "imp.h"
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#include <helper/binarybuffer.h>
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#include <target/algorithm.h>
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#include <target/armv4_5.h>
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#include <target/arm.h>
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#include <target/image.h>
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@ -26,7 +26,7 @@
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#include "imp.h"
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#include "str7x.h"
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#include <target/armv4_5.h>
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#include <target/arm.h>
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#include <helper/binarybuffer.h>
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#include <target/algorithm.h>
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@ -97,6 +97,7 @@ MIPS32_SRC = \
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noinst_HEADERS = \
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algorithm.h \
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arm.h \
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arm_dpm.h \
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arm_jtag.h \
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arm_adi_v5.h \
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@ -0,0 +1,206 @@
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/*
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* Copyright (C) 2005 by Dominic Rath
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* Dominic.Rath@gmx.de
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*
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* Copyright (C) 2008 by Spencer Oliver
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* spen@spen-soft.co.uk
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*
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* Copyright (C) 2009 by Øyvind Harboe
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* oyvind.harboe@zylin.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef ARM_H
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#define ARM_H
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#include <target/target.h>
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#include <helper/command.h>
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/**
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* @file
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* Holds the interface to ARM cores.
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*
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* At this writing, only "classic ARM" cores built on the ARMv4 register
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* and mode model are supported. The Thumb2-only microcontroller profile
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* support has not yet been integrated, affecting Cortex-M parts.
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*/
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/**
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* These numbers match the five low bits of the *PSR registers on
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* "classic ARM" processors, which build on the ARMv4 processor
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* modes and register set.
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*/
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enum arm_mode {
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ARM_MODE_USR = 16,
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ARM_MODE_FIQ = 17,
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ARM_MODE_IRQ = 18,
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ARM_MODE_SVC = 19,
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ARM_MODE_ABT = 23,
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ARM_MODE_MON = 26,
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ARM_MODE_UND = 27,
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ARM_MODE_SYS = 31,
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ARM_MODE_ANY = -1
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};
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const char *arm_mode_name(unsigned psr_mode);
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bool is_arm_mode(unsigned psr_mode);
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/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
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enum arm_state {
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ARM_STATE_ARM,
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ARM_STATE_THUMB,
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ARM_STATE_JAZELLE,
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ARM_STATE_THUMB_EE,
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};
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extern const char *arm_state_strings[];
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#define ARM_COMMON_MAGIC 0x0A450A45
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/**
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* Represents a generic ARM core, with standard application registers.
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*
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* There are sixteen application registers (including PC, SP, LR) and a PSR.
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* Cortex-M series cores do not support as many core states or shadowed
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* registers as traditional ARM cores, and only support Thumb2 instructions.
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*/
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struct arm {
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int common_magic;
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struct reg_cache *core_cache;
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/** Handle to the CPSR; valid in all core modes. */
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struct reg *cpsr;
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/** Handle to the SPSR; valid only in core modes with an SPSR. */
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struct reg *spsr;
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/** Support for arm_reg_current() */
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const int *map;
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/**
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* Indicates what registers are in the ARM state core register set.
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* ARM_MODE_ANY indicates the standard set of 37 registers,
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* seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
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* more registers are shadowed, for "Secure Monitor" mode.
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*/
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enum arm_mode core_type;
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/** Record the current core mode: SVC, USR, or some other mode. */
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enum arm_mode core_mode;
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/** Record the current core state: ARM, Thumb, or otherwise. */
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enum arm_state core_state;
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/** Flag reporting unavailability of the BKPT instruction. */
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bool is_armv4;
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/** Flag reporting whether semihosting is active. */
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bool is_semihosting;
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/** Value to be returned by semihosting SYS_ERRNO request. */
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int semihosting_errno;
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/** Backpointer to the target. */
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struct target *target;
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/** Handle for the debug module, if one is present. */
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struct arm_dpm *dpm;
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/** Handle for the Embedded Trace Module, if one is present. */
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struct etm_context *etm;
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/* FIXME all these methods should take "struct arm *" not target */
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/** Retrieve all core registers, for display. */
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int (*full_context)(struct target *target);
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/** Retrieve a single core register. */
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int (*read_core_reg)(struct target *target, struct reg *reg,
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int num, enum arm_mode mode);
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int (*write_core_reg)(struct target *target, struct reg *reg,
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int num, enum arm_mode mode, uint32_t value);
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/** Read coprocessor register. */
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int (*mrc)(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t *value);
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/** Write coprocessor register. */
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int (*mcr)(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t value);
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void *arch_info;
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};
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/** Convert target handle to generic ARM target state handle. */
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static inline struct arm *target_to_arm(struct target *target)
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{
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return target->arch_info;
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}
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static inline bool is_arm(struct arm *arm)
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{
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return arm && arm->common_magic == ARM_COMMON_MAGIC;
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}
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struct arm_algorithm {
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int common_magic;
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enum arm_mode core_mode;
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enum arm_state core_state;
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};
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struct arm_reg {
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int num;
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enum arm_mode mode;
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struct target *target;
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struct arm *armv4_5_common;
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uint32_t value;
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};
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struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
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extern const struct command_registration arm_command_handlers[];
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int arm_arch_state(struct target *target);
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int arm_get_gdb_reg_list(struct target *target,
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struct reg **reg_list[], int *reg_list_size);
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int arm_init_arch_info(struct target *target, struct arm *arm);
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/* REVISIT rename this once it's usable by ARMv7-M */
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int armv4_5_run_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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uint32_t entry_point, uint32_t exit_point,
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int timeout_ms, void *arch_info);
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int arm_checksum_memory(struct target *target,
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uint32_t address, uint32_t count, uint32_t *checksum);
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int arm_blank_check_memory(struct target *target,
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uint32_t address, uint32_t count, uint32_t *blank);
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void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
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struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
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extern struct reg arm_gdb_dummy_fp_reg;
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extern struct reg arm_gdb_dummy_fps_reg;
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#endif /* ARM_H */
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@ -23,7 +23,7 @@
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#ifndef ARM11_H
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#define ARM11_H
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#include <target/armv4_5.h>
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#include <target/arm.h>
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#include <target/arm_dpm.h>
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#define ARM11_TAP_DEFAULT TAP_INVALID
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@ -39,6 +39,7 @@
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#include "arm_semihosting.h"
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#include "algorithm.h"
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#include "register.h"
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#include "armv4_5.h"
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/**
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@ -29,7 +29,7 @@
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#ifndef ARM7_9_COMMON_H
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#define ARM7_9_COMMON_H
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#include <target/armv4_5.h>
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#include <target/arm.h>
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#include <target/arm_jtag.h>
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#define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
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@ -21,7 +21,7 @@
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#include "config.h"
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#endif
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#include "armv4_5.h" /* REVISIT to become arm.h */
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#include "arm.h"
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#include "arm_dpm.h"
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#include <jtag/jtag.h>
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#include "register.h"
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@ -34,6 +34,7 @@
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#include "config.h"
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#endif
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#include "arm.h"
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#include "armv4_5.h"
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#include "register.h"
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#include "arm_semihosting.h"
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@ -24,6 +24,7 @@
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#include "config.h"
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#endif
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#include "arm.h"
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#include "armv4_5.h"
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#include "arm_disassembler.h"
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#include "arm_simulator.h"
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@ -27,6 +27,7 @@
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#include "config.h"
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#endif
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#include "arm.h"
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#include "armv4_5.h"
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#include "arm_jtag.h"
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#include "breakpoints.h"
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@ -26,39 +26,10 @@
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#ifndef ARMV4_5_H
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#define ARMV4_5_H
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#include <target/target.h>
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#include <helper/command.h>
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/**
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* These numbers match the five low bits of the *PSR registers on
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* "classic ARM" processors, which build on the ARMv4 processor
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* modes and register set.
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/* This stuff "knows" that its callers aren't talking
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* to microcontroller profile (current Cortex-M) parts.
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* We want to phase it out so core code can be shared.
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*/
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enum arm_mode {
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ARM_MODE_USR = 16,
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ARM_MODE_FIQ = 17,
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ARM_MODE_IRQ = 18,
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ARM_MODE_SVC = 19,
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ARM_MODE_ABT = 23,
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ARM_MODE_MON = 26,
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ARM_MODE_UND = 27,
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ARM_MODE_SYS = 31,
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ARM_MODE_ANY = -1
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};
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const char *arm_mode_name(unsigned psr_mode);
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bool is_arm_mode(unsigned psr_mode);
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/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
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enum arm_state {
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ARM_STATE_ARM,
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ARM_STATE_THUMB,
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ARM_STATE_JAZELLE,
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ARM_STATE_THUMB_EE,
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};
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extern const char *arm_state_strings[];
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/* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an
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* index into the armv4_5_core_reg_map array. Its remaining users are
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@ -76,140 +47,4 @@ extern const int armv4_5_core_reg_map[8][17];
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/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
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enum { ARMV4_5_CPSR = 31, };
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#define ARM_COMMON_MAGIC 0x0A450A45
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/**
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* Represents a generic ARM core, with standard application registers.
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*
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* There are sixteen application registers (including PC, SP, LR) and a PSR.
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* Cortex-M series cores do not support as many core states or shadowed
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* registers as traditional ARM cores, and only support Thumb2 instructions.
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*/
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struct arm
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{
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int common_magic;
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struct reg_cache *core_cache;
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/** Handle to the CPSR; valid in all core modes. */
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struct reg *cpsr;
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/** Handle to the SPSR; valid only in core modes with an SPSR. */
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struct reg *spsr;
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/** Support for arm_reg_current() */
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const int *map;
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/**
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* Indicates what registers are in the ARM state core register set.
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* ARM_MODE_ANY indicates the standard set of 37 registers,
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* seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
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* more registers are shadowed, for "Secure Monitor" mode.
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*/
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enum arm_mode core_type;
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/** Record the current core mode: SVC, USR, or some other mode. */
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enum arm_mode core_mode;
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/** Record the current core state: ARM, Thumb, or otherwise. */
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enum arm_state core_state;
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/** Flag reporting unavailability of the BKPT instruction. */
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bool is_armv4;
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/** Flag reporting whether semihosting is active. */
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bool is_semihosting;
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/** Value to be returned by semihosting SYS_ERRNO request. */
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int semihosting_errno;
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/** Backpointer to the target. */
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struct target *target;
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/** Handle for the debug module, if one is present. */
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struct arm_dpm *dpm;
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/** Handle for the Embedded Trace Module, if one is present. */
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struct etm_context *etm;
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|
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/* FIXME all these methods should take "struct arm *" not target */
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|
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/** Retrieve all core registers, for display. */
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int (*full_context)(struct target *target);
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/** Retrieve a single core register. */
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int (*read_core_reg)(struct target *target, struct reg *reg,
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int num, enum arm_mode mode);
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int (*write_core_reg)(struct target *target, struct reg *reg,
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int num, enum arm_mode mode, uint32_t value);
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/** Read coprocessor register. */
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int (*mrc)(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t *value);
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/** Write coprocessor register. */
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int (*mcr)(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t value);
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void *arch_info;
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};
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/** Convert target handle to generic ARM target state handle. */
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static inline struct arm *target_to_arm(struct target *target)
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{
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return target->arch_info;
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}
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static inline bool is_arm(struct arm *arm)
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{
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return arm && arm->common_magic == ARM_COMMON_MAGIC;
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}
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||||
struct arm_algorithm
|
||||
{
|
||||
int common_magic;
|
||||
|
||||
enum arm_mode core_mode;
|
||||
enum arm_state core_state;
|
||||
};
|
||||
|
||||
struct arm_reg
|
||||
{
|
||||
int num;
|
||||
enum arm_mode mode;
|
||||
struct target *target;
|
||||
struct arm *armv4_5_common;
|
||||
uint32_t value;
|
||||
};
|
||||
|
||||
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
|
||||
|
||||
int arm_arch_state(struct target *target);
|
||||
int arm_get_gdb_reg_list(struct target *target,
|
||||
struct reg **reg_list[], int *reg_list_size);
|
||||
|
||||
extern const struct command_registration arm_command_handlers[];
|
||||
|
||||
int arm_init_arch_info(struct target *target, struct arm *arm);
|
||||
|
||||
int armv4_5_run_algorithm(struct target *target,
|
||||
int num_mem_params, struct mem_param *mem_params,
|
||||
int num_reg_params, struct reg_param *reg_params,
|
||||
uint32_t entry_point, uint32_t exit_point,
|
||||
int timeout_ms, void *arch_info);
|
||||
|
||||
int arm_checksum_memory(struct target *target,
|
||||
uint32_t address, uint32_t count, uint32_t *checksum);
|
||||
int arm_blank_check_memory(struct target *target,
|
||||
uint32_t address, uint32_t count, uint32_t *blank);
|
||||
|
||||
void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
|
||||
struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
|
||||
|
||||
extern struct reg arm_gdb_dummy_fp_reg;
|
||||
extern struct reg arm_gdb_dummy_fps_reg;
|
||||
|
||||
#endif /* ARMV4_5_H */
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
#define ARMV7A_H
|
||||
|
||||
#include <target/arm_adi_v5.h>
|
||||
#include <target/armv4_5.h>
|
||||
#include <target/arm.h>
|
||||
#include <target/armv4_5_mmu.h>
|
||||
#include <target/armv4_5_cache.h>
|
||||
#include <target/arm_dpm.h>
|
||||
|
|
@ -114,22 +114,6 @@ target_to_armv7a(struct target *target)
|
|||
/* See ARMv7a arch spec section C10.8 */
|
||||
#define CPUDBG_AUTHSTATUS 0xFB8
|
||||
|
||||
struct armv7a_algorithm
|
||||
{
|
||||
int common_magic;
|
||||
|
||||
enum arm_mode core_mode;
|
||||
enum arm_state core_state;
|
||||
};
|
||||
|
||||
struct armv7a_core_reg
|
||||
{
|
||||
int num;
|
||||
enum arm_mode mode;
|
||||
struct target *target;
|
||||
struct armv7a_common *armv7a_common;
|
||||
};
|
||||
|
||||
int armv7a_arch_state(struct target *target);
|
||||
struct reg_cache *armv7a_build_reg_cache(struct target *target,
|
||||
struct armv7a_common *armv7a_common);
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
#define ARMV7M_COMMON_H
|
||||
|
||||
#include <target/arm_adi_v5.h>
|
||||
#include <target/armv4_5.h>
|
||||
#include <target/arm.h>
|
||||
|
||||
/* define for enabling armv7 gdb workarounds */
|
||||
#if 1
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include "armv4_5.h"
|
||||
#include "arm.h"
|
||||
#include "etm.h"
|
||||
#include "etb.h"
|
||||
#include "register.h"
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include "armv4_5.h"
|
||||
#include "arm.h"
|
||||
#include "etm.h"
|
||||
#include "etb.h"
|
||||
#include "image.h"
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include "armv4_5.h"
|
||||
#include "arm.h"
|
||||
#include "etm_dummy.h"
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
#include "config.h"
|
||||
#endif
|
||||
|
||||
#include "armv4_5.h"
|
||||
#include "arm.h"
|
||||
#include "oocd_trace.h"
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@
|
|||
#include "register.h"
|
||||
#include "image.h"
|
||||
#include "arm_opcodes.h"
|
||||
#include "armv4_5.h"
|
||||
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
#ifndef XSCALE_H
|
||||
#define XSCALE_H
|
||||
|
||||
#include <target/armv4_5.h>
|
||||
#include <target/arm.h>
|
||||
#include <target/armv4_5_mmu.h>
|
||||
#include <target/trace.h>
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue