target/cortex_m: use cortex_m->dcb_dhcsr in cortex_m_soft_reset_halt()
cortex_m->dcb_dhcsr caches status of DHCSR register. Use it instead of local variable in cortex_m_soft_reset_halt() like in other code. Extracted from [1]. [1] Antonio Borneo: 6207: cortex_m: rework handling of dcb_dhcsr Link: https://review.openocd.org/c/openocd/+/6207 Change-Id: I9a0aeba0b6b0b4969f05f4a32fc2fc8d244f56ca Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6677 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
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@ -776,7 +776,6 @@ static int cortex_m_soft_reset_halt(struct target *target)
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{
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{
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struct cortex_m_common *cortex_m = target_to_cm(target);
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struct cortex_m_common *cortex_m = target_to_cm(target);
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struct armv7m_common *armv7m = &cortex_m->armv7m;
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struct armv7m_common *armv7m = &cortex_m->armv7m;
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uint32_t dcb_dhcsr = 0;
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int retval, timeout = 0;
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int retval, timeout = 0;
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/* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
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/* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
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@ -812,25 +811,23 @@ static int cortex_m_soft_reset_halt(struct target *target)
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register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
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register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
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while (timeout < 100) {
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while (timeout < 100) {
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retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
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retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
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if (retval == ERROR_OK) {
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if (retval == ERROR_OK) {
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retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
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retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
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&cortex_m->nvic_dfsr);
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&cortex_m->nvic_dfsr);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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if ((dcb_dhcsr & S_HALT)
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if ((cortex_m->dcb_dhcsr & S_HALT)
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&& (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
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&& (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
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LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
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LOG_DEBUG("system reset-halted, DHCSR 0x%08" PRIx32 ", DFSR 0x%08" PRIx32,
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"DFSR 0x%08x",
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cortex_m->dcb_dhcsr, cortex_m->nvic_dfsr);
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(unsigned) dcb_dhcsr,
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(unsigned) cortex_m->nvic_dfsr);
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cortex_m_poll(target);
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cortex_m_poll(target);
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/* FIXME restore user's vector catch config */
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/* FIXME restore user's vector catch config */
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return ERROR_OK;
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return ERROR_OK;
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} else
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} else
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LOG_DEBUG("waiting for system reset-halt, "
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LOG_DEBUG("waiting for system reset-halt, "
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"DHCSR 0x%08x, %d ms",
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"DHCSR 0x%08" PRIx32 ", %d ms",
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(unsigned) dcb_dhcsr, timeout);
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cortex_m->dcb_dhcsr, timeout);
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}
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}
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timeout++;
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timeout++;
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alive_sleep(1);
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alive_sleep(1);
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