- keep additional information for decoded instructions
git-svn-id: svn://svn.berlios.de/openocd/trunk@69 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
parent
b9628accd6
commit
1f76f69999
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@ -70,6 +70,7 @@ int evaluate_blx_imm(u32 opcode, u32 address, arm_instruction_t *instruction)
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{
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int offset;
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u32 immediate;
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u32 target_address;
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instruction->type = ARM_BLX;
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immediate = opcode & 0x00ffffff;
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@ -87,9 +88,12 @@ int evaluate_blx_imm(u32 opcode, u32 address, arm_instruction_t *instruction)
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if (opcode & 0x01000000)
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offset |= 0x2;
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instruction->target_address = address + 8 + offset;
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target_address = address + 8 + offset;
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snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBLX 0x%8.8x", address, opcode, instruction->target_address);
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snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBLX 0x%8.8x", address, opcode, target_address);
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instruction->info.b_bl_bx_blx.reg_operand = -1;
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instruction->info.b_bl_bx_blx.target_address = target_address;
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return ERROR_OK;
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}
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@ -99,6 +103,7 @@ int evaluate_b_bl(u32 opcode, u32 address, arm_instruction_t *instruction)
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u8 L;
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u32 immediate;
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int offset;
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u32 target_address;
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immediate = opcode & 0x00ffffff;
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L = (opcode & 0x01000000) >> 24;
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@ -112,7 +117,7 @@ int evaluate_b_bl(u32 opcode, u32 address, arm_instruction_t *instruction)
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/* shift two bits left */
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offset <<= 2;
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instruction->target_address = address + 8 + offset;
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target_address = address + 8 + offset;
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if (L)
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instruction->type = ARM_BL;
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@ -120,7 +125,10 @@ int evaluate_b_bl(u32 opcode, u32 address, arm_instruction_t *instruction)
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instruction->type = ARM_B;
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snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tB%s%s 0x%8.8x", address, opcode,
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(L) ? "L" : "", COND(opcode), instruction->target_address);
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(L) ? "L" : "", COND(opcode), target_address);
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instruction->info.b_bl_bx_blx.reg_operand = -1;
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instruction->info.b_bl_bx_blx.target_address = target_address;
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return ERROR_OK;
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}
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@ -278,6 +286,10 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
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/* base register */
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Rn = (opcode & 0xf0000) >> 16;
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instruction->info.load_store.Rd = Rd;
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instruction->info.load_store.Rn = Rn;
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instruction->info.load_store.U = U;
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/* determine operation */
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if (L)
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operation = "LDR";
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@ -328,6 +340,9 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
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{
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u32 offset_12 = (opcode & 0xfff);
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snprintf(offset, 32, "#%s0x%x", (U) ? "" : "-", offset_12);
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instruction->info.load_store.offset_mode = 0;
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instruction->info.load_store.offset.offset = offset_12;
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}
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else /* either +-<Rm> or +-<Rm>, <shift>, #<shift_imm> */
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{
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@ -338,30 +353,46 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
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shift = (opcode & 0x60) >> 5;
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Rm = (opcode & 0xf);
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/* LSR encodes a shift by 32 bit as 0x0 */
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if ((shift == 0x1) && (shift_imm == 0x0))
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shift_imm = 0x20;
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/* ASR encodes a shift by 32 bit as 0x0 */
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if ((shift == 0x2) && (shift_imm == 0x0))
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shift_imm = 0x20;
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/* ROR by 32 bit is actually a RRX */
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if ((shift == 0x3) && (shift_imm == 0x0))
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shift = 0x4;
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instruction->info.load_store.offset_mode = 1;
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instruction->info.load_store.offset.reg.Rm = Rm;
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instruction->info.load_store.offset.reg.shift = shift;
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instruction->info.load_store.offset.reg.shift_imm = shift_imm;
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if ((shift_imm == 0x0) && (shift == 0x0)) /* +-<Rm> */
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{
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snprintf(offset, 32, "%sr%i", (U) ? "" : "-", Rm);
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}
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else /* +-<Rm>, <Shift>, #<shift_imm> */
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{
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if (shift == 0x0) /* LSL */
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switch (shift)
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{
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snprintf(offset, 32, "%sr%i, LSL #0x%x", (U) ? "" : "-", Rm, shift_imm);
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}
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else if (shift == 0x1) /* LSR */
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{
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snprintf(offset, 32, "%sr%i, LSR #0x%x", (U) ? "" : "-", Rm, shift_imm);
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}
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else if (shift == 0x2) /* ASR */
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{
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snprintf(offset, 32, "%sr%i, ASR #0x%x", (U) ? "" : "-", Rm, shift_imm);
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}
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else if (shift == 0x3) /* ROR or RRX */
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{
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if (shift_imm == 0x0) /* RRX */
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snprintf(offset, 32, "%sr%i, RRX", (U) ? "" : "-", Rm);
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else
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case 0x0: /* LSL */
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snprintf(offset, 32, "%sr%i, LSL #0x%x", (U) ? "" : "-", Rm, shift_imm);
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break;
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case 0x1: /* LSR */
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snprintf(offset, 32, "%sr%i, LSR #0x%x", (U) ? "" : "-", Rm, shift_imm);
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break;
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case 0x2: /* ASR */
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snprintf(offset, 32, "%sr%i, ASR #0x%x", (U) ? "" : "-", Rm, shift_imm);
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break;
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case 0x3: /* ROR */
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snprintf(offset, 32, "%sr%i, ROR #0x%x", (U) ? "" : "-", Rm, shift_imm);
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break;
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case 0x4: /* RRX */
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snprintf(offset, 32, "%sr%i, RRX", (U) ? "" : "-", Rm);
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break;
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}
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}
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}
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@ -373,12 +404,16 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
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snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i, %s]",
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address, opcode, operation, COND(opcode), suffix,
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Rd, Rn, offset);
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instruction->info.load_store.index_mode = 0;
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}
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else /* pre-indexed */
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{
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snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i, %s]!",
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address, opcode, operation, COND(opcode), suffix,
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Rd, Rn, offset);
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instruction->info.load_store.index_mode = 1;
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}
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}
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else /* post-indexed */
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@ -386,6 +421,8 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
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snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i], %s",
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address, opcode, operation, COND(opcode), suffix,
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Rd, Rn, offset);
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instruction->info.load_store.index_mode = 2;
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}
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return ERROR_OK;
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@ -415,6 +452,10 @@ int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruc
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/* base register */
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Rn = (opcode & 0xf0000) >> 16;
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instruction->info.load_store.Rd = Rd;
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instruction->info.load_store.Rn = Rn;
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instruction->info.load_store.U = U;
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/* determine instruction type and suffix */
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if (S) /* signed */
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{
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@ -467,12 +508,20 @@ int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruc
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{
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u32 offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf);
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snprintf(offset, 32, "#%s0x%x", (U) ? "" : "-", offset_8);
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instruction->info.load_store.offset_mode = 0;
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instruction->info.load_store.offset.offset = offset_8;
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}
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else /* Register offset/index (+-<Rm>) */
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{
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u8 Rm;
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Rm = (opcode & 0xf);
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snprintf(offset, 32, "%sr%i", (U) ? "" : "-", Rm);
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instruction->info.load_store.offset_mode = 1;
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instruction->info.load_store.offset.reg.Rm = Rm;
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instruction->info.load_store.offset.reg.shift = 0x0;
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instruction->info.load_store.offset.reg.shift_imm = 0x0;
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}
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if (P == 1)
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@ -482,12 +531,16 @@ int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruc
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snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i, %s]",
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address, opcode, operation, COND(opcode), suffix,
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Rd, Rn, offset);
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instruction->info.load_store.index_mode = 0;
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}
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else /* pre-indexed */
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{
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snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i, %s]!",
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address, opcode, operation, COND(opcode), suffix,
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Rd, Rn, offset);
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instruction->info.load_store.index_mode = 1;
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}
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}
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else /* post-indexed */
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@ -495,6 +548,8 @@ int evaluate_misc_load_store(u32 opcode, u32 address, arm_instruction_t *instruc
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snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i], %s",
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address, opcode, operation, COND(opcode), suffix,
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Rd, Rn, offset);
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instruction->info.load_store.index_mode = 2;
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}
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return ERROR_OK;
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@ -520,6 +575,11 @@ int evaluate_ldm_stm(u32 opcode, u32 address, arm_instruction_t *instruction)
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register_list = (opcode & 0xffff);
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Rn = (opcode & 0xf0000) >> 16;
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instruction->info.load_store_multiple.Rn = Rn;
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instruction->info.load_store_multiple.register_list = register_list;
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instruction->info.load_store_multiple.S = S;
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instruction->info.load_store_multiple.W = W;
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if (L)
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{
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instruction->type = ARM_LDM;
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@ -534,16 +594,28 @@ int evaluate_ldm_stm(u32 opcode, u32 address, arm_instruction_t *instruction)
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if (P)
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{
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if (U)
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{
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instruction->info.load_store_multiple.addressing_mode = 1;
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addressing_mode = "IB";
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}
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else
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{
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instruction->info.load_store_multiple.addressing_mode = 3;
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addressing_mode = "DB";
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}
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}
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else
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{
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if (U)
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{
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instruction->info.load_store_multiple.addressing_mode = 0;
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addressing_mode = "IA";
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}
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else
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{
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instruction->info.load_store_multiple.addressing_mode = 2;
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addressing_mode = "DA";
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}
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}
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reg_list_p = reg_list;
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@ -733,6 +805,9 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
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snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBX%s r%i",
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address, opcode, COND(opcode), Rm);
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instruction->info.b_bl_bx_blx.reg_operand = Rm;
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instruction->info.b_bl_bx_blx.target_address = -1;
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}
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/* CLZ */
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@ -898,6 +973,10 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
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Rd = (opcode & 0xf000) >> 12;
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Rn = (opcode & 0xf0000) >> 16;
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instruction->info.data_proc.Rd = Rd;
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instruction->info.data_proc.Rn = Rn;
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instruction->info.data_proc.S = S;
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switch (op)
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{
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case 0x0:
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@ -975,6 +1054,9 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
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immediate = ror(immed_8, rotate_imm * 2);
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snprintf(shifter_operand, 32, "#0x%x", immediate);
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instruction->info.data_proc.variant = 0;
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instruction->info.data_proc.shifter_operand.immediate.immediate = immediate;
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}
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else /* register-based shifter operand */
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{
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@ -987,7 +1069,11 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
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u8 shift_imm;
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shift_imm = (opcode & 0xf80) >> 7;
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instruction->info.data_proc.variant = 1;
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instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
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instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = shift_imm;
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instruction->info.data_proc.shifter_operand.immediate_shift.shift = shift;
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if ((shift_imm == 0x0) && (shift == 0x0))
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{
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snprintf(shifter_operand, 32, "r%i", Rm);
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@ -1023,6 +1109,11 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
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{
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u8 Rs = (opcode & 0xf00) >> 8;
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instruction->info.data_proc.variant = 2;
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instruction->info.data_proc.shifter_operand.register_shift.Rm = Rm;
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instruction->info.data_proc.shifter_operand.register_shift.Rs = Rs;
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instruction->info.data_proc.shifter_operand.register_shift.shift = shift;
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if (shift == 0x0) /* LSL */
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{
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snprintf(shifter_operand, 32, "r%i, LSL r%i", Rm, Rs);
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@ -120,15 +120,76 @@ enum arm_instruction_type
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ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
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};
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typedef struct arm_b_bl_bx_blx_instr_s
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{
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int reg_operand;
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u32 target_address;
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} arm_b_bl_bx_blx_instr_t;
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typedef struct arm_data_proc_instr_s
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{
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int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
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u8 S;
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u8 Rn;
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u8 Rd;
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union
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{
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struct {
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u8 immediate;
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} immediate;
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struct {
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u8 Rm;
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u8 shift;
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u8 shift_imm;
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} immediate_shift;
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struct {
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u8 Rm;
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u8 shift;
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u8 Rs;
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} register_shift;
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} shifter_operand;
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} arm_data_proc_instr_t;
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typedef struct arm_load_store_instr_s
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{
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u8 Rd;
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u8 Rn;
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u8 U;
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int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
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int offset_mode; /* 0: immediate, 1: (scaled) register */
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union
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{
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u32 offset;
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struct {
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u8 Rm;
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u8 shift;
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u8 shift_imm;
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} reg;
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} offset;
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} arm_load_store_instr_t;
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typedef struct arm_load_store_multiple_instr_s
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{
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u8 Rn;
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u32 register_list;
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u8 addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
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u8 S;
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u8 W;
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} arm_load_store_multiple_instr_t;
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typedef struct arm_instruction_s
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{
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enum arm_instruction_type type;
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char text[128];
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u32 opcode;
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/* target */
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u32 target_address;
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union {
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arm_b_bl_bx_blx_instr_t b_bl_bx_blx;
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arm_data_proc_instr_t data_proc;
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arm_load_store_instr_t load_store;
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arm_load_store_multiple_instr_t load_store_multiple;
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} info;
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} arm_instruction_t;
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extern int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
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