- the 'help' command now takes an optional argument to display help only on a certain command (thanks to Andrew Dyer for this enhancement)
- OpenOCD now includes the ability to diassemble instructions on its own (only ARM for now, Thumb might follow). The command is "armv4_5 disassemble <address> <count> ['thumb']" (thumb is currently unsupported). I've compared the produced disassembly against GDB/GNU Objdump output, and it seems to be correct, but there may still be some bugs left. git-svn-id: svn://svn.berlios.de/openocd/trunk@68 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
parent
335f667d44
commit
b9628accd6
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@ -443,6 +443,15 @@ int command_print_help(command_context_t* context, char* name, char** args, int
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for (c = context->commands; c; c = c->next)
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{
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if (argc == 1)
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{
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if (strncasecmp(c->name, args[0], c->unique_len))
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continue;
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if (strncasecmp(c->name, args[0], strlen(args[0])))
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continue;
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}
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command_print_help_line(context, c, 0);
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}
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@ -2,6 +2,7 @@ INCLUDES = -I$(top_srcdir)/src/gdb -I$(top_srcdir)/src/helper -I$(top_srcdir)/s
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METASOURCES = AUTO
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noinst_LIBRARIES = libtarget.a
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libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \
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arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c
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arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c
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noinst_HEADERS = target.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
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arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h
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arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
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arm_disassembler.h
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,138 @@
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/***************************************************************************
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* Copyright (C) 2006 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARM_DISASSEMBLER_H
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#define ARM_DISASSEMBLER_H
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#include "types.h"
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enum arm_instruction_type
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{
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ARM_UNKNOWN_INSTUCTION,
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/* Branch instructions */
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ARM_B,
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ARM_BL,
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ARM_BX,
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ARM_BLX,
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/* Data processing instructions */
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ARM_AND,
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ARM_EOR,
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ARM_SUB,
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ARM_RSB,
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ARM_ADD,
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ARM_ADC,
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ARM_SBC,
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ARM_RSC,
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ARM_TST,
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ARM_TEQ,
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ARM_CMP,
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ARM_CMN,
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ARM_ORR,
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ARM_MOV,
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ARM_BIC,
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ARM_MVN,
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/* Load/store instructions */
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ARM_LDR,
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ARM_LDRB,
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ARM_LDRT,
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ARM_LDRBT,
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ARM_LDRH,
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ARM_LDRSB,
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ARM_LDRSH,
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ARM_LDM,
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ARM_STR,
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ARM_STRB,
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ARM_STRT,
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ARM_STRBT,
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ARM_STRH,
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ARM_STM,
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/* Status register access instructions */
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ARM_MRS,
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ARM_MSR,
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/* Multiply instructions */
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ARM_MUL,
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ARM_MLA,
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ARM_SMULL,
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ARM_SMLAL,
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ARM_UMULL,
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ARM_UMLAL,
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/* Miscellaneous instructions */
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ARM_CLZ,
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/* Exception generating instructions */
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ARM_BKPT,
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ARM_SWI,
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/* Coprocessor instructions */
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ARM_CDP,
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ARM_LDC,
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ARM_STC,
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ARM_MCR,
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ARM_MRC,
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/* Semaphore instructions */
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ARM_SWP,
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ARM_SWPB,
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/* Enhanced DSP extensions */
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ARM_MCRR,
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ARM_MRRC,
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ARM_PLD,
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ARM_QADD,
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ARM_QDADD,
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ARM_QSUB,
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ARM_QDSUB,
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ARM_SMLAxy,
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ARM_SMLALxy,
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ARM_SMLAWy,
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ARM_SMULxy,
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ARM_SMULWy,
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ARM_LDRD,
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ARM_STRD,
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ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
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};
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typedef struct arm_instruction_s
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{
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enum arm_instruction_type type;
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char text[128];
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u32 opcode;
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/* target */
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u32 target_address;
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} arm_instruction_t;
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extern int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
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#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28])
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#endif /* ARM_DISASSEMBLER_H */
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@ -19,6 +19,8 @@
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***************************************************************************/
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#include "config.h"
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#include "arm_disassembler.h"
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#include "armv4_5.h"
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#include "target.h"
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return ERROR_OK;
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}
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int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
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armv4_5_common_t *armv4_5 = target->arch_info;
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u32 address;
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int count;
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int i;
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arm_instruction_t cur_instruction;
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u32 opcode;
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int thumb;
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if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
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{
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command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
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return ERROR_OK;
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}
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if (argc < 2)
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{
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command_print(cmd_ctx, "usage: armv4_5 disassemble <address> <count> ['thumb']");
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return ERROR_OK;
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}
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address = strtoul(args[0], NULL, 0);
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count = strtoul(args[1], NULL, 0);
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if (argc >= 3)
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if (strcmp(args[2], "thumb") == 0)
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thumb = 1;
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for (i = 0; i < count; i++)
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{
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target->type->read_memory(target, address, 4, 1, (u8*)&opcode);
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evaluate_opcode(opcode, address, &cur_instruction);
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command_print(cmd_ctx, "%s", cur_instruction.text);
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address += (thumb) ? 2 : 4;
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}
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return ERROR_OK;
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}
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int armv4_5_register_commands(struct command_context_s *cmd_ctx)
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{
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command_t *armv4_5_cmd;
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register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers");
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register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm|thumb>");
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register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions <address> <count> ['thumb']");
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return ERROR_OK;
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}
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