numicro: Integrate Nuvoton NuMicro flash driver.
Flash driver "mini51.c" and "nuc1x.c" are same target MCU. This patch integrates each driver and functions, and makes into new "NuMicro" flash driver. Change-Id: Ifff5c1cfdd265acca0f489631695be9194fa144c Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp> Reviewed-on: http://openocd.zylin.com/2794 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Nemui Trinomius
Spencer Oliver
parent
03f46e3688
commit
33e406824c
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@ -43,8 +43,7 @@ NOR_DRIVERS = \
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fm3.c \
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dsp5680xx_flash.c \
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kinetis.c \
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mini51.c \
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nuc1x.c \
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numicro.c \
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nrf51.c \
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mrvlqspi.c \
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psoc4.c \
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@ -54,8 +54,7 @@ extern struct flash_driver fm3_flash;
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extern struct flash_driver kinetis_flash;
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extern struct flash_driver efm32_flash;
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extern struct flash_driver mdr_flash;
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extern struct flash_driver mini51_flash;
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extern struct flash_driver nuc1x_flash;
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extern struct flash_driver numicro_flash;
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extern struct flash_driver nrf51_flash;
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extern struct flash_driver mrvlqspi_flash;
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extern struct flash_driver psoc4_flash;
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@ -99,8 +98,7 @@ static struct flash_driver *flash_drivers[] = {
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&kinetis_flash,
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&efm32_flash,
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&mdr_flash,
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&mini51_flash,
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&nuc1x_flash,
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&numicro_flash,
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&nrf51_flash,
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&mrvlqspi_flash,
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&psoc4_flash,
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@ -1,584 +0,0 @@
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/***************************************************************************
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* Copyright (C) 2013 Cosmin Gorgovan *
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* cosmin [at] linux-geek [dot] org *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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/*
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Flash driver for the Nuvoton NuMicro Mini51 and M051 series microcontrollers
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Part |APROM Size |Part ID (at 0x5000_0000)
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----------------------------------------------
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MINI51LAN 4 KB 0x00205100
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MINI51ZAN 4 KB 0x00205103
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MINI51TAN 4 KB 0x00205104
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MINI52LAN 8 KB 0x00205200
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MINI52ZAN 8 KB 0x00205203
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MINI52TAN 8 KB 0x00205204
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MINI54LAN 16 KB 0x00205400
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MINI54ZAN 16 KB 0x00205403
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MINI54TAN 16 KB 0x00205404
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M052LBN 8 KB 0x10005200
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M054LBN 16 KB 0x10005400
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M058LBN 32 KB 0x10005800
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M0516LBN 64 KB 0x10005A00
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M052ZBN 8 KB 0x10005203
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M054ZBN 16 KB 0x10005403
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M058ZBN 32 KB 0x10005803
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M0516ZBN 64 KB 0x10005A03
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M052LDN 8 KB 0x20005200
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M054LDN 16 KB 0x20005400
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M058LDN 32 KB 0x20005800
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M0516LDN 64 KB 0x20005A00
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M052ZDN 8 KB 0x20005203
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M054ZDN 16 KB 0x20005403
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M058ZDN 32 KB 0x20005803
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M0516ZDN 64 KB 0x20005A03
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M052LDE 8 KB 0x30005200
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M054LDE 16 KB 0x30005400
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M058LDE 32 KB 0x30005800
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M0516LDE 64 KB 0x30005A00
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M052ZDE 8 KB 0x30005203
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M054ZDE 16 KB 0x30005403
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M058ZDE 32 KB 0x30005803
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M0516ZDE 64 KB 0x30005A03
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Datasheet & TRM
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---------------
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The ISP flash programming procedure is described on pages 130 and 131 of the (not very verbose) TRM.
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http://www.keil.com/dd/docs/datashts/nuvoton/mini51/da00-mini51_52_54c1.pdf
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M051 ISP datasheet pages 190-206:
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http://www.nuvoton.com/hq/resource-download.jsp?tp_GUID=DA05-M052-54-58-516
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This driver
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-----------
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* chip_erase, erase, read and write operations have been implemented;
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* All operations support APROM, LDROM, FLASH DATA and CONFIG;
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Flash access limitations
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------------------------
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For implementing the read operation, please note that the APROM isn't memory mapped when booted from LDROM.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "imp.h"
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#define PART_ID_REG 0x50000000
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#define IPRSTC1 0x50000008
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#define REGLOCKADDR 0x50000100
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#define ISPCON 0x5000C000
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#define ISPADR 0x5000C004
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#define ISPDAT 0x5000C008
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#define ISPCMD 0x5000C00C
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#define ISPTRG 0x5000C010
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/* Undocumented isp register */
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#define ISPUNKNOWN 0x5000C01C
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#define IPRSTC_CPU_RST 0x02
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#define ISPCON_ISPFF 0x40
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#define ISPCON_LDUEN 0x20
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#define ISPCON_CFGUEN 0x10
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#define ISPCON_APUEN 0x08
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#define ISPCON_BS_LDROM 0x02
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#define ISPCON_ISPEN 0x01
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#define ISPCMD_READ 0x00
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#define ISPCMD_PROGRAM 0x21
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#define ISPCMD_ERASE 0x22
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#define ISPCMD_CHIP_ERASE 0x26
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#define ISPTRG_ISPGO 0x01
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#define MINI51_APROM_BASE 0x00000000
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#define MINI51_DATA_BASE 0x0001F000
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#define MINI51_LDROM_BASE 0x00100000
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#define MINI51_CONFIG_BASE 0x00300000
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#define MINI51_KB 1024
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#define MINI51_PAGE_SIZE 512
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#define MINI51_TIMEOUT 1000
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#define ENSURE_OK(status) if (status != ERROR_OK) return status
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#define MINI51_MAX_FLASH_BANKS 4
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struct mini51_flash_bank_type {
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uint32_t base;
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uint32_t size;
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};
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struct mini51_cpu_type {
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char *name;
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uint32_t ppid;
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unsigned n_banks;
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struct mini51_flash_bank_type bank[MINI51_MAX_FLASH_BANKS];
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};
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#define MINI51_BANKS_MINI51(aprom_size) \
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.n_banks = 3, \
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{ {MINI51_APROM_BASE, (aprom_size)}, {MINI51_LDROM_BASE, 2*1024}, {MINI51_CONFIG_BASE, 512} }
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#define MINI51_BANKS_M051(aprom_size) \
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.n_banks = 4, \
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{ {MINI51_APROM_BASE, (aprom_size)}, {MINI51_DATA_BASE, 4*1024}, {MINI51_LDROM_BASE, 4*1024}, \
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{MINI51_CONFIG_BASE, 1024} }
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static const struct mini51_cpu_type mini51_cpu[] = {
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{ "MINI51LAN", 0x00205100, MINI51_BANKS_MINI51(4*1024) },
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{ "MINI51ZAN", 0x00205103, MINI51_BANKS_MINI51(4*1024) },
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{ "MINI51TAN", 0x00205104, MINI51_BANKS_MINI51(4*1024) },
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{ "MINI52LAN", 0x00205200, MINI51_BANKS_MINI51(8*1024) },
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{ "MINI52ZAN", 0x00205203, MINI51_BANKS_MINI51(8*1024) },
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{ "MINI52TAN", 0x00205204, MINI51_BANKS_MINI51(8*1024) },
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{ "MINI54LAN", 0x00205400, MINI51_BANKS_MINI51(16*1024) },
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{ "MINI54ZAN", 0x00205403, MINI51_BANKS_MINI51(16*1024) },
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{ "MINI54TAN", 0x00205404, MINI51_BANKS_MINI51(16*1024) },
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{ "M052LBN", 0x10005200, MINI51_BANKS_M051(8*1024) },
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{ "M054LBN", 0x10005400, MINI51_BANKS_M051(16*1024) },
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{ "M058LBN", 0x10005800, MINI51_BANKS_M051(32*1024) },
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{ "M0516LBN", 0x10005A00, MINI51_BANKS_M051(64*1024) },
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{ "M052ZBN", 0x10005203, MINI51_BANKS_M051(8*1024) },
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{ "M054ZBN", 0x10005403, MINI51_BANKS_M051(16*1024) },
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{ "M058ZBN", 0x10005803, MINI51_BANKS_M051(32*1024) },
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{ "M0516ZBN", 0x10005A03, MINI51_BANKS_M051(64*1024) },
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{ "M052LDN", 0x20005200, MINI51_BANKS_M051(8*1024) },
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{ "M054LDN", 0x20005400, MINI51_BANKS_M051(16*1024) },
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{ "M058LDN", 0x20005800, MINI51_BANKS_M051(32*1024) },
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{ "M0516LDN", 0x20005A00, MINI51_BANKS_M051(64*1024) },
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{ "M052ZDN", 0x20005203, MINI51_BANKS_M051(8*1024) },
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{ "M054ZDN", 0x20005403, MINI51_BANKS_M051(16*1024) },
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{ "M058ZDN", 0x20005803, MINI51_BANKS_M051(32*1024) },
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{ "M0516ZDN", 0x20005A03, MINI51_BANKS_M051(64*1024) },
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{ "M052LDE", 0x30005200, MINI51_BANKS_M051(8*1024) },
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{ "M054LDE", 0x30005400, MINI51_BANKS_M051(16*1024) },
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{ "M058LDE", 0x30005800, MINI51_BANKS_M051(32*1024) },
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{ "M0516LDE", 0x30005A00, MINI51_BANKS_M051(64*1024) },
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{ "M052ZDE", 0x30005203, MINI51_BANKS_M051(8*1024) },
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{ "M054ZDE", 0x30005403, MINI51_BANKS_M051(16*1024) },
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{ "M058ZDE", 0x30005803, MINI51_BANKS_M051(32*1024) },
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{ "M0516ZDE", 0x30005A03, MINI51_BANKS_M051(64*1024) },
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};
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struct mini51_flash_bank {
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bool probed;
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const struct mini51_cpu_type *cpu;
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};
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/* Private methods */
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static int mini51_unlock_reg(struct target *target)
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{
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int status;
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status = target_write_u32(target, REGLOCKADDR, 0x59);
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if (status != ERROR_OK)
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return status;
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status = target_write_u32(target, REGLOCKADDR, 0x16);
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if (status != ERROR_OK)
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return status;
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status = target_write_u32(target, REGLOCKADDR, 0x88);
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if (status != ERROR_OK)
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return status;
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return ERROR_OK;
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}
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static int mini51_get_part_id(struct target *target, uint32_t *part_id)
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{
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int retu = target_read_u32(target, PART_ID_REG, part_id);
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LOG_INFO("device id = 0x%08" PRIx32 "", *part_id);
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return retu;
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}
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static int mini51_get_cpu_type(struct target *target, const struct mini51_cpu_type** cpu)
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{
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uint32_t part_id;
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int status;
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status = mini51_get_part_id(target, &part_id);
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ENSURE_OK(status);
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for (size_t i = 0; i < sizeof(mini51_cpu)/sizeof(mini51_cpu[0]); i++) {
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if (part_id == mini51_cpu[i].ppid) {
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*cpu = &mini51_cpu[i];
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LOG_INFO("device name = %s", (*cpu)->name);
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return ERROR_OK;
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}
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}
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return ERROR_FLASH_OPERATION_FAILED;
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}
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static int mini51_get_flash_size(struct flash_bank *bank, const struct mini51_cpu_type *cpu, uint32_t *flash_size)
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{
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for (size_t i = 0; i < cpu->n_banks; i++) {
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if (bank->base == cpu->bank[i].base) {
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*flash_size = cpu->bank[i].size;
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LOG_INFO("bank base = 0x%08" PRIx32 ", size = 0x%08" PRIx32 "", bank->base, *flash_size);
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return ERROR_OK;
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}
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}
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return ERROR_FLASH_OPERATION_FAILED;
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}
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static int mini51_isp_execute(struct target *target)
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{
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int status;
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uint32_t ispcon;
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int timeout;
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uint32_t isptrg;
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/* start ISP operation */
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status = target_write_u32(target, ISPTRG, ISPTRG_ISPGO);
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ENSURE_OK(status);
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/* Wait for for command to finish executing */
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timeout = MINI51_TIMEOUT;
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do {
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target_read_u32(target, ISPTRG, &isptrg);
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timeout--;
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} while ((isptrg & ISPTRG_ISPGO) && (timeout > 0));
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if (timeout == 0) {
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LOG_WARNING("Mini51 flash driver: Timeout executing flash command\n");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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/* Check for errors */
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status = target_read_u32(target, ISPCON, &ispcon);
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ENSURE_OK(status);
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if (ispcon & ISPCON_ISPFF) {
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LOG_WARNING("Mini51 flash driver: operation failed\n");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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return status;
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}
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static int mini51_isp_execute_cmd(struct target *target, uint32_t cmd, uint32_t address, uint32_t data)
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{
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int status;
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status = target_write_u32(target, ISPDAT, data);
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ENSURE_OK(status);
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status = target_write_u32(target, ISPADR, address);
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ENSURE_OK(status);
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status = target_write_u32(target, ISPCMD, cmd);
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ENSURE_OK(status);
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status = mini51_isp_execute(target);
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return status;
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}
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static int mini51_isp_execute_cmd_read(struct target *target, uint32_t cmd, uint32_t address, uint32_t *data)
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{
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int status;
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status = target_write_u32(target, ISPADR, address);
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ENSURE_OK(status);
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status = target_write_u32(target, ISPCMD, cmd);
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ENSURE_OK(status);
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status = mini51_isp_execute(target);
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ENSURE_OK(status);
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status = target_read_u32(target, ISPDAT, data);
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ENSURE_OK(status);
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return status;
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}
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static int mini51_isp_enable(struct target *target)
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{
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int status;
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uint32_t ispcon;
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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status = mini51_unlock_reg(target);
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ENSURE_OK(status);
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status = target_read_u32(target, ISPCON, &ispcon);
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ENSURE_OK(status);
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ispcon |= ISPCON_ISPEN | ISPCON_LDUEN | ISPCON_APUEN | ISPCON_CFGUEN;
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status = target_write_u32(target, ISPCON, ispcon);
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return status;
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}
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/* Public (API) methods */
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FLASH_BANK_COMMAND_HANDLER(mini51_flash_bank_command)
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{
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struct mini51_flash_bank *mini51_info;
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mini51_info = malloc(sizeof(struct mini51_flash_bank));
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mini51_info->probed = false;
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bank->driver_priv = mini51_info;
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return ERROR_OK;
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}
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static int mini51_protect_check(struct flash_bank *bank)
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{
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LOG_WARNING("Mini51 flash driver: protect_check not implemented yet\n");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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static int mini51_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
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{
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int status;
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uint32_t ispdat;
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struct target *target = bank->target;
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if ((offset & 0x3) || (count & 0x3)) {
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LOG_WARNING("Mini51 flash driver: unaligned access not supported\n");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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status = mini51_isp_enable(target);
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ENSURE_OK(status);
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for (uint32_t i = offset; i < offset + count; i += 4) {
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status = mini51_isp_execute_cmd_read(target, ISPCMD_READ, bank->base + i, &ispdat);
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memcpy(buffer, &ispdat, sizeof(ispdat));
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ENSURE_OK(status);
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buffer += sizeof(ispdat);
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}
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return ERROR_OK;
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}
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static int mini51_erase(struct flash_bank *bank, int first, int last)
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{
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int status;
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struct target *target = bank->target;
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/* Enable ISP */
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status = mini51_isp_enable(target);
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ENSURE_OK(status);
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for (int page_start = first; page_start <= last; page_start++) {
|
||||
/* Set up erase command */
|
||||
uint32_t address = bank->base + page_start*MINI51_PAGE_SIZE;
|
||||
status = mini51_isp_execute_cmd(target, ISPCMD_ERASE, address, 0);
|
||||
ENSURE_OK(status);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int mini51_protect(struct flash_bank *bank, int set, int first, int last)
|
||||
{
|
||||
LOG_WARNING("Mini51 flash driver: protect operation not implemented yet\n");
|
||||
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
static int mini51_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
|
||||
{
|
||||
int status;
|
||||
uint32_t ispdat;
|
||||
struct target *target = bank->target;
|
||||
|
||||
if ((offset & 0x3) || (count & 0x3)) {
|
||||
LOG_WARNING("Mini51 flash driver: unaligned access not supported\n");
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
status = mini51_isp_enable(target);
|
||||
ENSURE_OK(status);
|
||||
|
||||
for (uint32_t i = offset; i < offset + count; i += 4) {
|
||||
memcpy(&ispdat, buffer, sizeof(ispdat));
|
||||
status = mini51_isp_execute_cmd(target, ISPCMD_PROGRAM, bank->base + i, ispdat);
|
||||
ENSURE_OK(status);
|
||||
buffer += sizeof(ispdat);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int mini51_probe(struct flash_bank *bank)
|
||||
{
|
||||
uint32_t flash_size;
|
||||
int status;
|
||||
int num_pages;
|
||||
uint32_t offset = 0;
|
||||
const struct mini51_cpu_type *cpu;
|
||||
struct target *target = bank->target;
|
||||
|
||||
status = mini51_get_cpu_type(target, &cpu);
|
||||
if (status != ERROR_OK) {
|
||||
LOG_WARNING("Mini51 flash driver: Failed to detect a known part\n");
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
status = mini51_get_flash_size(bank, cpu, &flash_size);
|
||||
if (status != ERROR_OK) {
|
||||
LOG_WARNING("Mini51 flash driver: Failed to detect flash size\n");
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
num_pages = flash_size / MINI51_PAGE_SIZE;
|
||||
|
||||
bank->num_sectors = num_pages;
|
||||
bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
|
||||
bank->size = flash_size;
|
||||
|
||||
for (int i = 0; i < num_pages; i++) {
|
||||
bank->sectors[i].offset = offset;
|
||||
bank->sectors[i].size = MINI51_PAGE_SIZE;
|
||||
bank->sectors[i].is_erased = -1;
|
||||
bank->sectors[i].is_protected = 0;
|
||||
offset += MINI51_PAGE_SIZE;
|
||||
}
|
||||
|
||||
struct mini51_flash_bank *mini51_info = bank->driver_priv;
|
||||
mini51_info->probed = true;
|
||||
mini51_info->cpu = cpu;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int mini51_auto_probe(struct flash_bank *bank)
|
||||
{
|
||||
struct mini51_flash_bank *mini51_info = bank->driver_priv;
|
||||
if (mini51_info->probed)
|
||||
return ERROR_OK;
|
||||
return mini51_probe(bank);
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(mini51_handle_read_isp_command)
|
||||
{
|
||||
uint32_t address;
|
||||
uint32_t ispdat;
|
||||
int status;
|
||||
|
||||
if (CMD_ARGC != 1)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
|
||||
|
||||
struct target *target = get_current_target(CMD_CTX);
|
||||
|
||||
status = mini51_isp_enable(target);
|
||||
ENSURE_OK(status);
|
||||
status = mini51_isp_execute_cmd_read(target, ISPCMD_READ, address, &ispdat);
|
||||
ENSURE_OK(status);
|
||||
LOG_INFO("0x%08" PRIx32 ": 0x%08" PRIx32, address, ispdat);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(mini51_handle_write_isp_command)
|
||||
{
|
||||
uint32_t address;
|
||||
uint32_t ispdat;
|
||||
int status;
|
||||
|
||||
if (CMD_ARGC != 2)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], ispdat);
|
||||
|
||||
struct target *target = get_current_target(CMD_CTX);
|
||||
|
||||
status = mini51_isp_enable(target);
|
||||
ENSURE_OK(status);
|
||||
status = mini51_isp_execute_cmd(target, ISPCMD_PROGRAM, address, ispdat);
|
||||
ENSURE_OK(status);
|
||||
LOG_INFO("0x%08" PRIx32 ": 0x%08" PRIx32, address, ispdat);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(mini51_handle_chip_erase_command)
|
||||
{
|
||||
int status;
|
||||
if (CMD_ARGC != 0)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
|
||||
struct target *target = get_current_target(CMD_CTX);
|
||||
|
||||
status = mini51_isp_enable(target);
|
||||
ENSURE_OK(status);
|
||||
/* Write one to undocumented flash control register */
|
||||
status = target_write_u32(target, ISPUNKNOWN, 1);
|
||||
ENSURE_OK(status);
|
||||
|
||||
status = mini51_isp_execute_cmd(target, ISPCMD_CHIP_ERASE, 0, 0);
|
||||
ENSURE_OK(status);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static const struct command_registration mini51_exec_command_handlers[] = {
|
||||
{
|
||||
.name = "read_isp",
|
||||
.handler = mini51_handle_read_isp_command,
|
||||
.usage = "address",
|
||||
.mode = COMMAND_EXEC,
|
||||
.help = "read flash through ISP.",
|
||||
},
|
||||
{
|
||||
.name = "write_isp",
|
||||
.handler = mini51_handle_write_isp_command,
|
||||
.usage = "address value",
|
||||
.mode = COMMAND_EXEC,
|
||||
.help = "write flash through ISP.",
|
||||
},
|
||||
{
|
||||
.name = "chip_erase",
|
||||
.handler = mini51_handle_chip_erase_command,
|
||||
.mode = COMMAND_EXEC,
|
||||
.help = "chip erase.",
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
static const struct command_registration mini51_command_handlers[] = {
|
||||
{
|
||||
.name = "mini51",
|
||||
.mode = COMMAND_ANY,
|
||||
.help = "mini51 flash command group",
|
||||
.usage = "",
|
||||
.chain = mini51_exec_command_handlers,
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
struct flash_driver mini51_flash = {
|
||||
.name = "mini51",
|
||||
.commands = mini51_command_handlers,
|
||||
.flash_bank_command = mini51_flash_bank_command,
|
||||
.erase = mini51_erase,
|
||||
.protect = mini51_protect,
|
||||
.write = mini51_write,
|
||||
.read = mini51_read,
|
||||
.probe = mini51_probe,
|
||||
.auto_probe = mini51_auto_probe,
|
||||
.erase_check = default_flash_blank_check,
|
||||
.protect_check = mini51_protect_check,
|
||||
};
|
||||
|
|
@ -1,640 +0,0 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2011 by James K. Larson *
|
||||
* jlarson@pacifier.com *
|
||||
* *
|
||||
* Copyright (C) 2013 Nemui Trinomius *
|
||||
* nemuisan_kawausogasuki@live.jp *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program; if not, write to the *
|
||||
* Free Software Foundation, Inc., *
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
|
||||
***************************************************************************/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include <config.h>
|
||||
#endif
|
||||
|
||||
#include "imp.h"
|
||||
|
||||
/* nuc1x register locations */
|
||||
#define NUC1X_SYS_BASE 0x50000000
|
||||
#define NUC1X_SYS_WRPROT 0x50000100
|
||||
#define NUC1X_SYS_IPRSTC1 0x50000008
|
||||
|
||||
#define NUC1X_SYSCLK_BASE 0x50000200
|
||||
#define NUC1X_SYSCLK_PWRCON 0x50000200
|
||||
#define NUC1X_SYSCLK_CLKSEL0 0x50000210
|
||||
#define NUC1X_SYSCLK_CLKDIV 0x50000218
|
||||
#define NUC1X_SYSCLK_AHBCLK 0x50000204
|
||||
|
||||
#define NUC1X_FLASH_BASE 0x5000C000
|
||||
#define NUC1X_FLASH_ISPCON 0x5000C000
|
||||
#define NUC1X_FLASH_ISPCMD 0x5000C00C
|
||||
#define NUC1X_FLASH_ISPADR 0x5000C004
|
||||
#define NUC1X_FLASH_ISPDAT 0x5000C008
|
||||
#define NUC1X_FLASH_ISPTRG 0x5000C010
|
||||
|
||||
/* Command register bits */
|
||||
#define PWRCON_OSC22M (1 << 2)
|
||||
#define PWRCON_XTL12M (1 << 0)
|
||||
|
||||
#define IPRSTC1_CPU_RST (1<<1)
|
||||
#define IPRSTC1_CHIP_RST (1<<0)
|
||||
|
||||
#define AHBCLK_ISP_EN (1 << 2)
|
||||
|
||||
#define ISPCON_ISPEN (1 << 0)
|
||||
#define ISPCON_BS_AP (0 << 1)
|
||||
#define ISPCON_BS_LP (1 << 1)
|
||||
#define ISPCON_CFGUEN (1 << 4)
|
||||
#define ISPCON_LDUEN (1 << 5)
|
||||
#define ISPCON_ISPFF (1 << 6)
|
||||
|
||||
/* isp commands */
|
||||
#define ISPCMD_FCTRL (0x2)
|
||||
#define ISPCMD_FCEN (1 << 4)
|
||||
#define ISPCMD_FOEN (1 << 5)
|
||||
#define ISPCMD_ERASE (0x2 | ISPCMD_FOEN)
|
||||
#define ISPCMD_WRITE (0x1 | ISPCMD_FOEN)
|
||||
#define ISPTRG_ISPGO (1 << 0)
|
||||
|
||||
/* access unlock keys */
|
||||
#define KEY1 0x59
|
||||
#define KEY2 0x16
|
||||
#define KEY3 0x88
|
||||
#define LOCK 0x00
|
||||
|
||||
/* part structs */
|
||||
static const struct {
|
||||
const char *partname;
|
||||
uint32_t partno;
|
||||
uint16_t num_page;
|
||||
}
|
||||
NuMicroParts[] = {
|
||||
/*PART NO*/ /*PART ID*/ /*NUM PAGE*/
|
||||
{"NUC100LC1", 0x00010008, 64},
|
||||
{"NUC100LD1", 0x00010005, 128},
|
||||
{"NUC100LD2", 0x00010004, 128},
|
||||
{"NUC100RC1", 0x00010017, 64},
|
||||
{"NUC100RD1", 0x00010014, 128},
|
||||
{"NUC100RD2", 0x00010013, 128},
|
||||
|
||||
{"NUC100LD3", 0x00010003, 128},
|
||||
{"NUC100LE3", 0x00010000, 256},
|
||||
{"NUC100RD3", 0x00010012, 128},
|
||||
{"NUC100RE3", 0x00010009, 256},
|
||||
{"NUC100VD2", 0x00010022, 128},
|
||||
{"NUC100VD3", 0x00010021, 128},
|
||||
{"NUC100VE3", 0x00010018, 256},
|
||||
|
||||
{"NUC120LC1", 0x00012008, 64},
|
||||
{"NUC120LD1", 0x00012005, 128},
|
||||
{"NUC120LD2", 0x00012004, 128},
|
||||
{"NUC120RC1", 0x00012017, 64},
|
||||
{"NUC120RD1", 0x00012014, 128},
|
||||
{"NUC120RD2", 0x00012013, 128},
|
||||
|
||||
{"NUC120LD3", 0x00012003, 128},
|
||||
{"NUC120LE3", 0x00012000, 256},
|
||||
{"NUC120RD3", 0x00012012, 128},
|
||||
{"NUC120RE3", 0x00012009, 256},
|
||||
{"NUC120VD2", 0x00012022, 128},
|
||||
{"NUC120VD3", 0x00012021, 128},
|
||||
{"NUC120VE3", 0x00012018, 256},
|
||||
|
||||
{"NUC122ZD2", 0x00012231, 128},
|
||||
{"NUC122ZC1", 0x00012235, 64},
|
||||
{"NUC122LD2", 0x00012204, 128},
|
||||
{"NUC122LC1", 0x00012208, 64},
|
||||
{"NUC122RD2", 0x00012213, 128},
|
||||
{"NUC122RC1", 0x00012217, 64},
|
||||
|
||||
{"NUC123ZD4", 0x00012255, 136},
|
||||
{"NUC123ZC2", 0x00012245, 68},
|
||||
{"NUC123LD4", 0x00012235, 136},
|
||||
{"NUC123LC2", 0x00012225, 68},
|
||||
{"NUC123SD4", 0x00012215, 136},
|
||||
{"NUC123SC2", 0x00012205, 68},
|
||||
|
||||
{"NUC130LC1", 0x00013008, 64},
|
||||
{"NUC130LD2", 0x00013004, 128},
|
||||
{"NUC130LE3", 0x00013000, 256},
|
||||
{"NUC130RC1", 0x00013017, 64},
|
||||
{"NUC130RD2", 0x00013013, 128},
|
||||
{"NUC130RE3", 0x00013009, 256},
|
||||
{"NUC130VE3", 0x00013018, 256},
|
||||
|
||||
{"M052L", 0x00005200, 16},
|
||||
{"M052Z", 0x00005203, 16},
|
||||
{"M054L", 0x00005400, 32},
|
||||
{"M054Z", 0x00005403, 32},
|
||||
{"M058L", 0x00005800, 64},
|
||||
{"M058Z", 0x00005803, 64},
|
||||
{"M0516L", 0x00005A00, 128},
|
||||
{"M0516Z", 0x00005A03, 128},
|
||||
|
||||
{"MINI51L", 0x00205100, 8},
|
||||
{"MINI51Z", 0x00205103, 8},
|
||||
{"MINI52L", 0x00205200, 16},
|
||||
{"MINI52Z", 0x00205203, 16},
|
||||
{"MINI54L", 0x00205400, 32},
|
||||
{"MINI54Z", 0x00205403, 32},
|
||||
|
||||
{"UNKNOWN", 0x00000000, 256},
|
||||
};
|
||||
|
||||
static int nuc1x_unlock(struct flash_bank *bank)
|
||||
{
|
||||
uint32_t is_protected;
|
||||
struct target *target = bank->target;
|
||||
|
||||
/* Check to see if Nuc is unlocked or not */
|
||||
int retval = target_read_u32(target, NUC1X_SYS_WRPROT, &is_protected);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
LOG_DEBUG("protected = 0x%08" PRIx32 "", is_protected);
|
||||
if (is_protected == 0) { /* means protected - so unlock it */
|
||||
/* unlock flash registers */
|
||||
retval = target_write_u32(target, NUC1X_SYS_WRPROT, KEY1);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
retval = target_write_u32(target, NUC1X_SYS_WRPROT, KEY2);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
retval = target_write_u32(target, NUC1X_SYS_WRPROT, KEY3);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
}
|
||||
/* Check that unlock worked */
|
||||
retval = target_read_u32(target, NUC1X_SYS_WRPROT, &is_protected);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
if (is_protected == 1) { /* means unprotected */
|
||||
LOG_DEBUG("protection removed");
|
||||
} else {
|
||||
LOG_DEBUG("still protected!!");
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int nuc1x_reset(struct flash_bank *bank)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
|
||||
nuc1x_unlock(bank);
|
||||
|
||||
int retval = target_write_u32(target, NUC1X_SYS_IPRSTC1, IPRSTC1_CPU_RST);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int nuc1x_reset2lprom(struct flash_bank *bank)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
|
||||
nuc1x_unlock(bank);
|
||||
int retval = target_write_u32(target, NUC1X_FLASH_ISPCON, ISPCON_BS_LP);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
nuc1x_reset(bank);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int nuc1x_init_iap(struct flash_bank *bank)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
int retval = nuc1x_unlock(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
/* enable isp clock and ispen bit */
|
||||
retval = target_write_u32(target, NUC1X_SYSCLK_AHBCLK, AHBCLK_ISP_EN);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = target_write_u32(target, NUC1X_FLASH_ISPCON, ISPCON_ISPFF | ISPCON_LDUEN | ISPCON_CFGUEN | ISPCON_ISPEN);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* Private bank information for nuc1x. */
|
||||
struct nuc1x_flash_bank {
|
||||
struct working_area *write_algorithm;
|
||||
int probed;
|
||||
};
|
||||
|
||||
/* This is the function called in the config file. */
|
||||
FLASH_BANK_COMMAND_HANDLER(nuc1x_flash_bank_command)
|
||||
{
|
||||
struct nuc1x_flash_bank *bank_info;
|
||||
|
||||
if (CMD_ARGC < 6)
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
|
||||
LOG_INFO("add flash_bank nuc1x %s", bank->name);
|
||||
|
||||
bank_info = malloc(sizeof(struct nuc1x_flash_bank));
|
||||
|
||||
memset(bank_info, 0, sizeof(struct nuc1x_flash_bank));
|
||||
|
||||
bank->driver_priv = bank_info;
|
||||
|
||||
return ERROR_OK;
|
||||
|
||||
}
|
||||
|
||||
/* Protection checking - examines the lock bit. */
|
||||
static int nuc1x_protect_check(struct flash_bank *bank)
|
||||
{
|
||||
uint32_t is_protected, set;
|
||||
struct target *target = bank->target;
|
||||
int i;
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
/* Check to see if Nuc is unlocked or not */
|
||||
int retval = target_read_u32(target, NUC1X_SYS_WRPROT, &is_protected);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
LOG_INFO("is_protected = 0x%08" PRIx32 "", is_protected);
|
||||
if (is_protected == 0) { /* means protected */
|
||||
set = 1;
|
||||
} else {
|
||||
set = 0;
|
||||
}
|
||||
for (i = 0; i < bank->num_sectors; i++)
|
||||
bank->sectors[i].is_protected = set;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static int nuc1x_erase(struct flash_bank *bank, int first, int last)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
uint32_t timeout, status;
|
||||
int i;
|
||||
|
||||
if (bank->target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
LOG_INFO("Nuvoton NUC: Sector Erase ... (%d to %d)", first, last);
|
||||
|
||||
int retval = nuc1x_reset2lprom(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = nuc1x_init_iap(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = nuc1x_unlock(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = target_write_u32(target, NUC1X_FLASH_ISPCMD, ISPCMD_ERASE);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
for (i = first; i <= last; i++) {
|
||||
LOG_DEBUG("erasing sector %d at address 0x%" PRIx32 "", i, bank->base + bank->sectors[i].offset);
|
||||
retval = target_write_u32(target, NUC1X_FLASH_ISPADR, bank->base + bank->sectors[i].offset);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
retval = target_write_u32(target, NUC1X_FLASH_ISPTRG, ISPTRG_ISPGO); /* This is the only bit available */
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
/* wait for busy to clear - check the GO flag */
|
||||
timeout = 100;
|
||||
for (;;) {
|
||||
retval = target_read_u32(target, NUC1X_FLASH_ISPTRG, &status);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
LOG_DEBUG("status: 0x%" PRIx32 "", status);
|
||||
if (status == 0)
|
||||
break;
|
||||
if (timeout-- <= 0) {
|
||||
LOG_DEBUG("timed out waiting for flash");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
busy_sleep(1); /* can use busy sleep for short times. */
|
||||
}
|
||||
|
||||
/* check for failure */
|
||||
retval = target_read_u32(target, NUC1X_FLASH_ISPCON, &status);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
if ((status & ISPCON_ISPFF) != 0) {
|
||||
LOG_DEBUG("failure: 0x%" PRIx32 "", status);
|
||||
/* if bit is set, then must write to it to clear it. */
|
||||
retval = target_write_u32(target, NUC1X_FLASH_ISPCON, ISPCON_ISPFF);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
} else {
|
||||
bank->sectors[i].is_erased = 1;
|
||||
}
|
||||
}
|
||||
|
||||
retval = nuc1x_reset(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
/* done, */
|
||||
LOG_DEBUG("Erase done.");
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* The write routine stub. */
|
||||
static int nuc1x_write(struct flash_bank *bank, const uint8_t *buffer,
|
||||
uint32_t offset, uint32_t count)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
uint32_t i, timeout, status;
|
||||
|
||||
if (bank->target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
LOG_INFO("Nuvoton NUC: FLASH Write ...");
|
||||
|
||||
int retval = nuc1x_reset2lprom(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = nuc1x_init_iap(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = nuc1x_unlock(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = target_write_u32(target, NUC1X_FLASH_ISPCMD, ISPCMD_WRITE);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
/* program command */
|
||||
for (i = 0; i < count; i += 4) {
|
||||
|
||||
LOG_DEBUG("write longword @ %08" PRIX32, (uint32_t)(offset + i));
|
||||
|
||||
uint8_t padding[4] = {0xff, 0xff, 0xff, 0xff};
|
||||
memcpy(padding, buffer + i, MIN(4, count-i));
|
||||
|
||||
retval = target_write_u32(target, NUC1X_FLASH_ISPADR, bank->base + offset + i);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
retval = target_write_memory(target, NUC1X_FLASH_ISPDAT, 4, 1, padding);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
retval = target_write_u32(target, NUC1X_FLASH_ISPTRG, ISPTRG_ISPGO);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
/* wait for busy to clear - check the GO flag */
|
||||
timeout = 100;
|
||||
for (;;) {
|
||||
retval = target_read_u32(target, NUC1X_FLASH_ISPTRG, &status);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
LOG_DEBUG("status: 0x%" PRIx32 "", status);
|
||||
if (status == 0)
|
||||
break;
|
||||
if (timeout-- <= 0) {
|
||||
LOG_DEBUG("timed out waiting for flash");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
busy_sleep(1); /* can use busy sleep for short times. */
|
||||
}
|
||||
|
||||
/* check for failure */
|
||||
retval = target_read_u32(target, NUC1X_FLASH_ISPCON, &status);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
if ((status & ISPCON_ISPFF) != 0) {
|
||||
LOG_DEBUG("failure: 0x%" PRIx32 "", status);
|
||||
/* if bit is set, then must write to it to clear it. */
|
||||
retval = target_write_u32(target, NUC1X_FLASH_ISPCON, ISPCON_ISPFF);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
} else {
|
||||
LOG_DEBUG("Write OK");
|
||||
}
|
||||
}
|
||||
|
||||
retval = nuc1x_reset(bank);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
/* done, */
|
||||
LOG_DEBUG("Write done.");
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* The probe routine for the nuc. Only recognizes the nuc120 right now. */
|
||||
static int nuc1x_probe(struct flash_bank *bank)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
struct nuc1x_flash_bank *nuc1x_info = bank->driver_priv;
|
||||
int i;
|
||||
uint16_t num_pages;
|
||||
uint32_t device_id;
|
||||
int page_size;
|
||||
uint32_t base_address = 0x00000000;
|
||||
|
||||
nuc1x_info->probed = 0;
|
||||
|
||||
/* read nuc1x device id register */
|
||||
int retval = target_read_u32(target, 0x50000000, &device_id);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
page_size = 512; /* all nuc parts has 512 byte per sector */
|
||||
|
||||
/* search part numbers */
|
||||
for (i = 0; NuMicroParts[i].partno; i++) {
|
||||
if (NuMicroParts[i].partno == (device_id & 0x0FFFFFFF)) {
|
||||
num_pages = NuMicroParts[i].num_page;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!(NuMicroParts[i].partno == 0x00000000)) {
|
||||
LOG_INFO("DeviceID : 0x%08" PRIx32 "", device_id);
|
||||
LOG_INFO("Detect %s%cN!", NuMicroParts[i].partname, (char)('A'+(device_id>>28)));
|
||||
} else {
|
||||
LOG_INFO("No NUC Device Detected...");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
if (bank->sectors) {
|
||||
free(bank->sectors);
|
||||
bank->sectors = NULL;
|
||||
}
|
||||
|
||||
bank->base = base_address;
|
||||
bank->size = (num_pages * page_size);
|
||||
bank->num_sectors = num_pages;
|
||||
bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
|
||||
|
||||
for (i = 0; i < num_pages; i++) {
|
||||
bank->sectors[i].offset = i * page_size;
|
||||
bank->sectors[i].size = page_size;
|
||||
bank->sectors[i].is_erased = -1;
|
||||
bank->sectors[i].is_protected = 1;
|
||||
}
|
||||
|
||||
nuc1x_info->probed = 1;
|
||||
|
||||
LOG_DEBUG("Nuvoton NUC: Probed ...");
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* Standard approach to autoprobing. */
|
||||
static int nuc1x_auto_probe(struct flash_bank *bank)
|
||||
{
|
||||
struct nuc1x_flash_bank *nuc1x_info = bank->driver_priv;
|
||||
if (nuc1x_info->probed)
|
||||
return ERROR_OK;
|
||||
return nuc1x_probe(bank);
|
||||
}
|
||||
|
||||
/* Info doesn't really add much, but works correctly. */
|
||||
static int get_nuc1x_info(struct flash_bank *bank, char *buf, int buf_size)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
uint32_t i, device_id;
|
||||
|
||||
/* read nuc1x device id register */
|
||||
int retval = target_read_u32(target, 0x50000000, &device_id);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
/* search part numbers */
|
||||
for (i = 0; NuMicroParts[i].partno; i++) {
|
||||
if (NuMicroParts[i].partno == (device_id & 0x0FFFFFFF))
|
||||
break;
|
||||
}
|
||||
if (!(NuMicroParts[i].partno == 0x00000000)) {
|
||||
LOG_INFO("DeviceID : 0x%08" PRIx32 "", device_id);
|
||||
LOG_INFO("Detect %s%cN!", NuMicroParts[i].partname, (char)('A'+(device_id>>28)));
|
||||
} else {
|
||||
LOG_INFO("No NUC Device Detected...");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/* The nuc120 doesn't support mass erase, so this will probably be removed soon.
|
||||
* The structure is left for now until I am sure I don't want to add any custom
|
||||
* commands. */
|
||||
static int nuc1x_mass_erase(struct flash_bank *bank)
|
||||
{
|
||||
struct target *target = bank->target;
|
||||
int retval = ERROR_OK;
|
||||
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_ERROR("Target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
LOG_INFO("Nuvoton NUC: Chip Erase ... (may take several seconds)");
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(nuc1x_handle_mass_erase_command)
|
||||
{
|
||||
int i; /* for erasing sectors */
|
||||
if (CMD_ARGC < 1) {
|
||||
command_print(CMD_CTX, "nuc1x mass_erase <bank>");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
struct flash_bank *bank;
|
||||
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
||||
if (ERROR_OK != retval)
|
||||
return retval;
|
||||
|
||||
retval = nuc1x_mass_erase(bank);
|
||||
if (retval == ERROR_OK) {
|
||||
/* set all sectors as erased */
|
||||
for (i = 0; i < bank->num_sectors; i++)
|
||||
bank->sectors[i].is_erased = 1;
|
||||
|
||||
command_print(CMD_CTX, "nuc1x mass erase complete");
|
||||
} else
|
||||
command_print(CMD_CTX, "nuc1x mass erase failed");
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static const struct command_registration nuc1x_exec_command_handlers[] = {
|
||||
{
|
||||
.name = "mass_erase",
|
||||
.handler = nuc1x_handle_mass_erase_command,
|
||||
.mode = COMMAND_EXEC,
|
||||
.usage = "bank_id",
|
||||
.help = "Erase entire Flash device.",
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
static const struct command_registration nuc1x_command_handlers[] = {
|
||||
{
|
||||
.name = "nuc1x",
|
||||
.mode = COMMAND_ANY,
|
||||
.help = "nuc1x Flash command group",
|
||||
.chain = nuc1x_exec_command_handlers,
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
struct flash_driver nuc1x_flash = {
|
||||
.name = "nuc1x",
|
||||
.commands = nuc1x_command_handlers,
|
||||
.flash_bank_command = nuc1x_flash_bank_command,
|
||||
.erase = nuc1x_erase,
|
||||
.write = nuc1x_write,
|
||||
.read = default_flash_read,
|
||||
.probe = nuc1x_probe,
|
||||
.auto_probe = nuc1x_auto_probe,
|
||||
.erase_check = default_flash_blank_check,
|
||||
.protect_check = nuc1x_protect_check,
|
||||
.info = get_nuc1x_info,
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,61 +0,0 @@
|
|||
# script for nuvoton M051 family
|
||||
|
||||
transport select hla_swd
|
||||
|
||||
source [find target/swj-dp.tcl]
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME m051
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
# Work-area is a space in RAM used for flash programming
|
||||
# By default use 4kB
|
||||
if { [info exists WORKAREASIZE] } {
|
||||
set _WORKAREASIZE $WORKAREASIZE
|
||||
} else {
|
||||
set _WORKAREASIZE 0x1000
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
# See STM Document RM0091
|
||||
# Section 29.5.3
|
||||
set _CPUTAPID 0x0bb11477
|
||||
}
|
||||
|
||||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
|
||||
# flash size will be probed
|
||||
set _FLASHNAME $_CHIPNAME.flash_aprom
|
||||
flash bank $_FLASHNAME mini51 0x00000000 0x4000 0 0 $_TARGETNAME
|
||||
set _FLASHNAME $_CHIPNAME.flash_data
|
||||
flash bank $_FLASHNAME mini51 0x0001F000 0x1000 0 0 $_TARGETNAME
|
||||
set _FLASHNAME $_CHIPNAME.flash_ldrom
|
||||
flash bank $_FLASHNAME mini51 0x00100000 0x1000 0 0 $_TARGETNAME
|
||||
set _FLASHNAME $_CHIPNAME.flash_conf
|
||||
flash bank $_FLASHNAME mini51 0x00300000 0x0100 0 0 $_TARGETNAME
|
||||
|
||||
# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
|
||||
adapter_khz 1000
|
||||
|
||||
adapter_nsrst_delay 100
|
||||
|
||||
if {![using_hla]} {
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
}
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
# script for Nuvoton MuMicro Cortex-M0 Series
|
||||
|
||||
# Adapt based on what transport is active.
|
||||
source [find target/swj-dp.tcl]
|
||||
|
||||
# Set Chipname
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME NuMicro
|
||||
}
|
||||
|
||||
# SWD DP-ID Nuvoton NuMicro Cortex-M0 has SWD Transport only.
|
||||
if { [info exists CPUDAPID] } {
|
||||
set _CPUDAPID $CPUDAPID
|
||||
} else {
|
||||
set _CPUDAPID 0x0BB11477
|
||||
}
|
||||
|
||||
# Work-area is a space in RAM used for flash programming
|
||||
# By default use 2kB
|
||||
if { [info exists WORKAREASIZE] } {
|
||||
set _WORKAREASIZE $WORKAREASIZE
|
||||
} else {
|
||||
set _WORKAREASIZE 0x800
|
||||
}
|
||||
|
||||
|
||||
# Debug Adapter Target Settings
|
||||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
|
||||
# flash bank <name> numicro <base> <size(autodetect,set to 0)> 0 0 <target#>
|
||||
#set _FLASHNAME $_CHIPNAME.flash
|
||||
#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME
|
||||
# flash size will be probed
|
||||
set _FLASHNAME $_CHIPNAME.flash_aprom
|
||||
flash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME
|
||||
set _FLASHNAME $_CHIPNAME.flash_data
|
||||
flash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME
|
||||
set _FLASHNAME $_CHIPNAME.flash_ldrom
|
||||
flash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME
|
||||
set _FLASHNAME $_CHIPNAME.flash_config
|
||||
flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
|
||||
|
||||
# set default SWCLK frequency
|
||||
adapter_khz 1000
|
||||
|
||||
# set default srst setting "none"
|
||||
reset_config none
|
||||
|
||||
# HLA doesn't have cortex_m commands
|
||||
if {![using_hla]} {
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
}
|
||||
Loading…
Reference in New Issue