target/cortex_m: supress historical reset detection
The S_RESET_ST sticky bit is reset after DHCSR read. It is set at power-on reset and keeps active until the debuger reads DHCSR. Ignore S_RESET_ST at the very first read after OpenOCD start and suppress possibly misleading message "external reset detected" if we cannot guarantee the reset happened recently. While on it add a TODO comment. Change-Id: I15217c2ca6f69ac97aff8be86bce67cba94a42cd Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7109 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
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@ -652,6 +652,11 @@ static int cortex_m_endreset_event(struct target *target)
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register_cache_invalidate(armv7m->arm.core_cache);
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register_cache_invalidate(armv7m->arm.core_cache);
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/* TODO: invalidate also working areas (needed in the case of detected reset).
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* Doing so will require flash drivers to test if working area
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* is still valid in all target algo calling loops.
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*/
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/* make sure we have latest dhcsr flags */
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/* make sure we have latest dhcsr flags */
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retval = cortex_m_read_dhcsr_atomic_sticky(target);
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retval = cortex_m_read_dhcsr_atomic_sticky(target);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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@ -2396,6 +2401,20 @@ int cortex_m_examine(struct target *target)
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retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
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retval = target_read_u32(target, DCB_DHCSR, &cortex_m->dcb_dhcsr);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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/* Don't cumulate sticky S_RESET_ST at the very first read of DHCSR
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* as S_RESET_ST may indicate a reset that happened long time ago
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* (most probably the power-on reset before OpenOCD was started).
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* As we are just initializing the debug system we do not need
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* to call cortex_m_endreset_event() in the following poll.
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*/
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if (!cortex_m->dcb_dhcsr_sticky_is_recent) {
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cortex_m->dcb_dhcsr_sticky_is_recent = true;
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if (cortex_m->dcb_dhcsr & S_RESET_ST) {
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LOG_TARGET_DEBUG(target, "reset happened some time ago, ignore");
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cortex_m->dcb_dhcsr &= ~S_RESET_ST;
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}
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}
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cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
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cortex_m_cumulate_dhcsr_sticky(cortex_m, cortex_m->dcb_dhcsr);
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if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
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if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
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@ -206,6 +206,8 @@ struct cortex_m_common {
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/* Context information */
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/* Context information */
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uint32_t dcb_dhcsr;
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uint32_t dcb_dhcsr;
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uint32_t dcb_dhcsr_cumulated_sticky;
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uint32_t dcb_dhcsr_cumulated_sticky;
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/* DCB DHCSR has been at least once read, so the sticky bits have been reset */
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bool dcb_dhcsr_sticky_is_recent;
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uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
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uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
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uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
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uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
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