cortex_m: use LOG_TARGET_XXX
Change-Id: I8be0f67442644031e6e8df3090d81af195caf82b Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6672 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tarek BOCHKATI
Antonio Borneo
parent
f583f338b0
commit
4906176c77
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@ -185,7 +185,7 @@ static int cortex_m_load_core_reg_u32(struct target *target,
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break;
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cortex_m->slow_register_read = true; /* Polling (still) needed. */
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if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
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LOG_ERROR("Timeout waiting for DCRDR transfer ready");
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LOG_TARGET_ERROR(target, "Timeout waiting for DCRDR transfer ready");
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return ERROR_TIMEOUT_REACHED;
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}
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keep_alive();
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@ -223,7 +223,7 @@ static int cortex_m_slow_read_all_regs(struct target *target)
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}
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if (!cortex_m->slow_register_read)
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LOG_DEBUG("Switching back to fast register reads");
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LOG_TARGET_DEBUG(target, "Switching back to fast register reads");
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return ERROR_OK;
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}
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@ -319,7 +319,7 @@ static int cortex_m_fast_read_all_regs(struct target *target)
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for (unsigned int i = 0; i < wi; i++) {
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if ((dhcsr[i] & S_REGRDY) == 0) {
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not_ready = true;
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LOG_DEBUG("Register %u was not ready during fast read", i);
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LOG_TARGET_DEBUG(target, "Register %u was not ready during fast read", i);
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}
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cortex_m_cumulate_dhcsr_sticky(cortex_m, dhcsr[i]);
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}
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@ -330,7 +330,7 @@ static int cortex_m_fast_read_all_regs(struct target *target)
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return ERROR_TIMEOUT_REACHED;
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}
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LOG_DEBUG("read %u 32-bit registers", wi);
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LOG_TARGET_DEBUG(target, "read %u 32-bit registers", wi);
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unsigned int ri = 0; /* read index from r_vals array */
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for (reg_id = 0; reg_id < num_regs; reg_id++) {
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@ -403,7 +403,7 @@ static int cortex_m_store_core_reg_u32(struct target *target,
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if (cortex_m->dcb_dhcsr & S_REGRDY)
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break;
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if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
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LOG_ERROR("Timeout waiting for DCRDR transfer ready");
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LOG_TARGET_ERROR(target, "Timeout waiting for DCRDR transfer ready");
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return ERROR_TIMEOUT_REACHED;
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}
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keep_alive();
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@ -528,7 +528,7 @@ static int cortex_m_clear_halt(struct target *target)
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retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
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LOG_TARGET_DEBUG(target, "NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
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return ERROR_OK;
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}
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@ -550,7 +550,7 @@ static int cortex_m_single_step_core(struct target *target)
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retval = cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG(" ");
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LOG_TARGET_DEBUG(target, "single step");
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/* restore dhcsr reg */
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cortex_m_clear_halt(target);
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@ -590,7 +590,7 @@ static int cortex_m_endreset_event(struct target *target)
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retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
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LOG_TARGET_DEBUG(target, "DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
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/* this register is used for emulated dcc channel */
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retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
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@ -629,7 +629,7 @@ static int cortex_m_endreset_event(struct target *target)
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/* Enable FPB */
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retval = cortex_m_enable_fpb(target);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to enable the FPB");
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LOG_TARGET_ERROR(target, "Failed to enable the FPB");
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return retval;
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}
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@ -766,7 +766,7 @@ static int cortex_m_examine_exception_reason(struct target *target)
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}
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retval = dap_run(swjdp);
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if (retval == ERROR_OK)
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LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
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LOG_TARGET_DEBUG(target, "%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
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", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
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armv7m_exception_string(armv7m->exception_number),
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shcsr, except_sr, cfsr, except_ar);
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@ -782,7 +782,7 @@ static int cortex_m_debug_entry(struct target *target)
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struct arm *arm = &armv7m->arm;
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struct reg *r;
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LOG_DEBUG(" ");
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LOG_TARGET_DEBUG(target, " ");
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/* Do this really early to minimize the window where the MASKINTS erratum
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* can pile up pending interrupts. */
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@ -815,7 +815,7 @@ static int cortex_m_debug_entry(struct target *target)
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retval = cortex_m_fast_read_all_regs(target);
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if (retval == ERROR_TIMEOUT_REACHED) {
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cortex_m->slow_register_read = true;
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LOG_DEBUG("Switched to slow register read");
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LOG_TARGET_DEBUG(target, "Switched to slow register read");
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}
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}
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@ -855,7 +855,8 @@ static int cortex_m_debug_entry(struct target *target)
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if (armv7m->exception_number)
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cortex_m_examine_exception_reason(target);
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LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
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LOG_TARGET_DEBUG(target, "entered debug state in core mode: %s at PC 0x%" PRIx32
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", cpu in %s state, target->state: %s",
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arm_mode_name(arm->core_mode),
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buf_get_u32(arm->pc->value, 0, 32),
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secure_state ? "Secure" : "Non-Secure",
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@ -889,8 +890,7 @@ static int cortex_m_poll(struct target *target)
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* section B1.5.15 "Unrecoverable exception cases".
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*/
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if (cortex_m->dcb_dhcsr & S_LOCKUP) {
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LOG_ERROR("%s -- clearing lockup after double fault",
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target_name(target));
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LOG_TARGET_ERROR(target, "clearing lockup after double fault");
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cortex_m_write_debug_halt_mask(target, C_HALT, 0);
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target->debug_reason = DBG_REASON_DBGRQ;
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@ -909,7 +909,7 @@ static int cortex_m_poll(struct target *target)
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cortex_m->dcb_dhcsr_cumulated_sticky &= ~S_RESET_ST;
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if (target->state != TARGET_RESET) {
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target->state = TARGET_RESET;
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LOG_INFO("%s: external reset detected", target_name(target));
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LOG_TARGET_INFO(target, "external reset detected");
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}
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return ERROR_OK;
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}
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@ -918,7 +918,7 @@ static int cortex_m_poll(struct target *target)
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/* Cannot switch context while running so endreset is
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* called with target->state == TARGET_RESET
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*/
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LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
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LOG_TARGET_DEBUG(target, "Exit from reset with dcb_dhcsr 0x%" PRIx32,
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cortex_m->dcb_dhcsr);
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retval = cortex_m_endreset_event(target);
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if (retval != ERROR_OK) {
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@ -943,7 +943,6 @@ static int cortex_m_poll(struct target *target)
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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}
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if (prev_target_state == TARGET_DEBUG_RUNNING) {
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LOG_DEBUG(" ");
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retval = cortex_m_debug_entry(target);
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if (retval != ERROR_OK)
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return retval;
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@ -971,7 +970,7 @@ static int cortex_m_poll(struct target *target)
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register_cache_invalidate(armv7m->arm.core_cache);
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target->state = TARGET_RUNNING;
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LOG_WARNING("%s: external resume detected", target_name(target));
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LOG_TARGET_WARNING(target, "external resume detected");
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target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
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retval = ERROR_OK;
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}
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@ -984,20 +983,19 @@ static int cortex_m_poll(struct target *target)
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static int cortex_m_halt(struct target *target)
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{
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LOG_DEBUG("target->state: %s",
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target_state_name(target));
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LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
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if (target->state == TARGET_HALTED) {
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LOG_DEBUG("target was already halted");
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LOG_TARGET_DEBUG(target, "target was already halted");
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return ERROR_OK;
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}
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if (target->state == TARGET_UNKNOWN)
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LOG_WARNING("target was in unknown state when halt was requested");
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LOG_TARGET_WARNING(target, "target was in unknown state when halt was requested");
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if (target->state == TARGET_RESET) {
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if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
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LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
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LOG_TARGET_ERROR(target, "can't request a halt while in reset if nSRST pulls nTRST");
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return ERROR_TARGET_FAILURE;
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} else {
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/* we came here in a reset_halt or reset_init sequence
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@ -1031,10 +1029,10 @@ static int cortex_m_soft_reset_halt(struct target *target)
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* can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
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* As this reset only uses VC_CORERESET it would only ever reset the cortex_m
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* core, not the peripherals */
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LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
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LOG_TARGET_DEBUG(target, "soft_reset_halt is discouraged, please use 'reset halt' instead.");
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if (!cortex_m->vectreset_supported) {
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LOG_ERROR("VECTRESET is not supported on this Cortex-M core");
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LOG_TARGET_ERROR(target, "VECTRESET is not supported on this Cortex-M core");
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return ERROR_FAIL;
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}
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@ -1068,15 +1066,16 @@ static int cortex_m_soft_reset_halt(struct target *target)
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return retval;
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if ((cortex_m->dcb_dhcsr & S_HALT)
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&& (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
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LOG_DEBUG("system reset-halted, DHCSR 0x%08" PRIx32 ", DFSR 0x%08" PRIx32,
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cortex_m->dcb_dhcsr, cortex_m->nvic_dfsr);
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LOG_TARGET_DEBUG(target, "system reset-halted, DHCSR 0x%08" PRIx32 ", DFSR 0x%08" PRIx32,
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cortex_m->dcb_dhcsr, cortex_m->nvic_dfsr);
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cortex_m_poll(target);
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/* FIXME restore user's vector catch config */
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return ERROR_OK;
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} else
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LOG_DEBUG("waiting for system reset-halt, "
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} else {
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LOG_TARGET_DEBUG(target, "waiting for system reset-halt, "
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"DHCSR 0x%08" PRIx32 ", %d ms",
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cortex_m->dcb_dhcsr, timeout);
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}
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}
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timeout++;
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alive_sleep(1);
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@ -1106,7 +1105,7 @@ static int cortex_m_resume(struct target *target, int current,
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struct reg *r;
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if (target->state != TARGET_HALTED) {
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LOG_WARNING("target not halted");
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LOG_TARGET_WARNING(target, "target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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@ -1170,7 +1169,7 @@ static int cortex_m_resume(struct target *target, int current,
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/* Single step past breakpoint at current address */
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breakpoint = breakpoint_find(target, resume_pc);
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if (breakpoint) {
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LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
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LOG_TARGET_DEBUG(target, "unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
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breakpoint->address,
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breakpoint->unique_id);
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cortex_m_unset_breakpoint(target, breakpoint);
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@ -1191,11 +1190,11 @@ static int cortex_m_resume(struct target *target, int current,
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if (!debug_execution) {
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target->state = TARGET_RUNNING;
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target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
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LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
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LOG_TARGET_DEBUG(target, "target resumed at 0x%" PRIx32 "", resume_pc);
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} else {
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target->state = TARGET_DEBUG_RUNNING;
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target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
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LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
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LOG_TARGET_DEBUG(target, "target debug resumed at 0x%" PRIx32 "", resume_pc);
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}
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return ERROR_OK;
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@ -1214,7 +1213,7 @@ static int cortex_m_step(struct target *target, int current,
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bool isr_timed_out = false;
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if (target->state != TARGET_HALTED) {
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LOG_WARNING("target not halted");
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LOG_TARGET_WARNING(target, "target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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@ -1287,7 +1286,7 @@ static int cortex_m_step(struct target *target, int current,
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*
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*/
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if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
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LOG_DEBUG("Stepping over next instruction with interrupts disabled");
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LOG_TARGET_DEBUG(target, "Stepping over next instruction with interrupts disabled");
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cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
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cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
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/* Re-enable interrupts if appropriate */
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@ -1318,7 +1317,7 @@ static int cortex_m_step(struct target *target, int current,
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cortex_m_set_maskints_for_halt(target);
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} else {
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/* Start the core */
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LOG_DEBUG("Starting core to serve pending interrupts");
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LOG_TARGET_DEBUG(target, "Starting core to serve pending interrupts");
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int64_t t_start = timeval_ms();
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cortex_m_set_maskints_for_run(target);
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cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
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@ -1342,7 +1341,7 @@ static int cortex_m_step(struct target *target, int current,
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}
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if (isr_timed_out) {
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LOG_DEBUG("Interrupt handlers didn't complete within time, "
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LOG_TARGET_DEBUG(target, "Interrupt handlers didn't complete within time, "
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"leaving target running");
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} else {
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/* Step over next instruction with interrupts disabled */
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@ -1377,7 +1376,7 @@ static int cortex_m_step(struct target *target, int current,
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return ERROR_OK;
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}
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LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
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LOG_TARGET_DEBUG(target, "target stepped dcb_dhcsr = 0x%" PRIx32
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" nvic_icsr = 0x%" PRIx32,
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cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
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@ -1386,7 +1385,7 @@ static int cortex_m_step(struct target *target, int current,
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return retval;
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
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LOG_TARGET_DEBUG(target, "target stepped dcb_dhcsr = 0x%" PRIx32
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" nvic_icsr = 0x%" PRIx32,
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cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
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@ -1399,7 +1398,7 @@ static int cortex_m_assert_reset(struct target *target)
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struct armv7m_common *armv7m = &cortex_m->armv7m;
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enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
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LOG_DEBUG("target->state: %s",
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LOG_TARGET_DEBUG(target, "target->state: %s",
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target_state_name(target));
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enum reset_types jtag_reset_config = jtag_get_reset_config();
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@ -1423,10 +1422,10 @@ static int cortex_m_assert_reset(struct target *target)
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if (jtag_reset_config & RESET_HAS_SRST) {
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adapter_assert_reset();
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if (target->reset_halt)
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LOG_ERROR("Target not examined, will not halt after reset!");
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LOG_TARGET_ERROR(target, "Target not examined, will not halt after reset!");
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return ERROR_OK;
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} else {
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LOG_ERROR("Target not examined, reset NOT asserted!");
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LOG_TARGET_ERROR(target, "Target not examined, reset NOT asserted!");
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return ERROR_FAIL;
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}
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}
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@ -1473,7 +1472,7 @@ static int cortex_m_assert_reset(struct target *target)
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retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
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TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
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if (retval != ERROR_OK || retval2 != ERROR_OK)
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LOG_INFO("AP write error, reset will not halt");
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LOG_TARGET_INFO(target, "AP write error, reset will not halt");
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}
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if (jtag_reset_config & RESET_HAS_SRST) {
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@ -1493,15 +1492,15 @@ static int cortex_m_assert_reset(struct target *target)
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if (!cortex_m->vectreset_supported
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&& reset_config == CORTEX_M_RESET_VECTRESET) {
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reset_config = CORTEX_M_RESET_SYSRESETREQ;
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LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
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LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
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LOG_TARGET_WARNING(target, "VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
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LOG_TARGET_WARNING(target, "Set 'cortex_m reset_config sysresetreq'.");
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}
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LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
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LOG_TARGET_DEBUG(target, "Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
|
||||
? "SYSRESETREQ" : "VECTRESET");
|
||||
|
||||
if (reset_config == CORTEX_M_RESET_VECTRESET) {
|
||||
LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
|
||||
LOG_TARGET_WARNING(target, "Only resetting the Cortex-M core, use a reset-init event "
|
||||
"handler to reset any peripherals or configure hardware srst support.");
|
||||
}
|
||||
|
||||
|
|
@ -1510,11 +1509,11 @@ static int cortex_m_assert_reset(struct target *target)
|
|||
AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
|
||||
? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
|
||||
if (retval3 != ERROR_OK)
|
||||
LOG_DEBUG("Ignoring AP write error right after reset");
|
||||
LOG_TARGET_DEBUG(target, "Ignoring AP write error right after reset");
|
||||
|
||||
retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
|
||||
if (retval3 != ERROR_OK) {
|
||||
LOG_ERROR("DP initialisation failed");
|
||||
LOG_TARGET_ERROR(target, "DP initialisation failed");
|
||||
/* The error return value must not be propagated in this case.
|
||||
* SYSRESETREQ or VECTRESET have been possibly triggered
|
||||
* so reset processing should continue */
|
||||
|
|
@ -1550,7 +1549,7 @@ static int cortex_m_deassert_reset(struct target *target)
|
|||
{
|
||||
struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
|
||||
|
||||
LOG_DEBUG("target->state: %s",
|
||||
LOG_TARGET_DEBUG(target, "target->state: %s",
|
||||
target_state_name(target));
|
||||
|
||||
/* deassert reset lines */
|
||||
|
|
@ -1564,7 +1563,7 @@ static int cortex_m_deassert_reset(struct target *target)
|
|||
|
||||
int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("DP initialisation failed");
|
||||
LOG_TARGET_ERROR(target, "DP initialisation failed");
|
||||
return retval;
|
||||
}
|
||||
}
|
||||
|
|
@ -1580,7 +1579,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
|
|||
struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
|
||||
|
||||
if (breakpoint->set) {
|
||||
LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
|
||||
LOG_TARGET_WARNING(target, "breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -1589,35 +1588,36 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
|
|||
while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
|
||||
fp_num++;
|
||||
if (fp_num >= cortex_m->fp_num_code) {
|
||||
LOG_ERROR("Can not find free FPB Comparator!");
|
||||
LOG_TARGET_ERROR(target, "Can not find free FPB Comparator!");
|
||||
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||
}
|
||||
breakpoint->set = fp_num + 1;
|
||||
fpcr_value = breakpoint->address | 1;
|
||||
if (cortex_m->fp_rev == 0) {
|
||||
if (breakpoint->address > 0x1FFFFFFF) {
|
||||
LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
|
||||
LOG_TARGET_ERROR(target, "Cortex-M Flash Patch Breakpoint rev.1 "
|
||||
"cannot handle HW breakpoint above address 0x1FFFFFFE");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
uint32_t hilo;
|
||||
hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
|
||||
fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
|
||||
} else if (cortex_m->fp_rev > 1) {
|
||||
LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
|
||||
LOG_TARGET_ERROR(target, "Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
comparator_list[fp_num].used = true;
|
||||
comparator_list[fp_num].fpcr_value = fpcr_value;
|
||||
target_write_u32(target, comparator_list[fp_num].fpcr_address,
|
||||
comparator_list[fp_num].fpcr_value);
|
||||
LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
|
||||
LOG_TARGET_DEBUG(target, "fpc_num %i fpcr_value 0x%" PRIx32 "",
|
||||
fp_num,
|
||||
comparator_list[fp_num].fpcr_value);
|
||||
if (!cortex_m->fpb_enabled) {
|
||||
LOG_DEBUG("FPB wasn't enabled, do it now");
|
||||
LOG_TARGET_DEBUG(target, "FPB wasn't enabled, do it now");
|
||||
retval = cortex_m_enable_fpb(target);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("Failed to enable the FPB");
|
||||
LOG_TARGET_ERROR(target, "Failed to enable the FPB");
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
|
@ -1646,7 +1646,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
|
|||
breakpoint->set = true;
|
||||
}
|
||||
|
||||
LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
|
||||
LOG_TARGET_DEBUG(target, "BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
|
||||
breakpoint->unique_id,
|
||||
(int)(breakpoint->type),
|
||||
breakpoint->address,
|
||||
|
|
@ -1663,11 +1663,11 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
|
|||
struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
|
||||
|
||||
if (breakpoint->set <= 0) {
|
||||
LOG_WARNING("breakpoint not set");
|
||||
LOG_TARGET_WARNING(target, "breakpoint not set");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
|
||||
LOG_TARGET_DEBUG(target, "BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
|
||||
breakpoint->unique_id,
|
||||
(int)(breakpoint->type),
|
||||
breakpoint->address,
|
||||
|
|
@ -1677,7 +1677,7 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
|
|||
if (breakpoint->type == BKPT_HARD) {
|
||||
unsigned int fp_num = breakpoint->set - 1;
|
||||
if (fp_num >= cortex_m->fp_num_code) {
|
||||
LOG_DEBUG("Invalid FP Comparator number in breakpoint");
|
||||
LOG_TARGET_DEBUG(target, "Invalid FP Comparator number in breakpoint");
|
||||
return ERROR_OK;
|
||||
}
|
||||
comparator_list[fp_num].used = false;
|
||||
|
|
@ -1700,12 +1700,12 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
|
|||
int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
|
||||
{
|
||||
if (breakpoint->length == 3) {
|
||||
LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
|
||||
LOG_TARGET_DEBUG(target, "Using a two byte breakpoint for 32bit Thumb-2 request");
|
||||
breakpoint->length = 2;
|
||||
}
|
||||
|
||||
if ((breakpoint->length != 2)) {
|
||||
LOG_INFO("only breakpoints of two bytes length supported");
|
||||
LOG_TARGET_INFO(target, "only breakpoints of two bytes length supported");
|
||||
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
|
|
@ -1737,7 +1737,7 @@ static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *wat
|
|||
comparator++, dwt_num++)
|
||||
continue;
|
||||
if (dwt_num >= cortex_m->dwt_num_comp) {
|
||||
LOG_ERROR("Can not find free DWT Comparator");
|
||||
LOG_TARGET_ERROR(target, "Can not find free DWT Comparator");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
comparator->used = true;
|
||||
|
|
@ -1795,7 +1795,7 @@ static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *wat
|
|||
target_write_u32(target, comparator->dwt_comparator_address + 8,
|
||||
comparator->function);
|
||||
|
||||
LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
|
||||
LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
|
||||
watchpoint->unique_id, dwt_num,
|
||||
(unsigned) comparator->comp,
|
||||
(unsigned) comparator->mask,
|
||||
|
|
@ -1809,19 +1809,19 @@ static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *w
|
|||
struct cortex_m_dwt_comparator *comparator;
|
||||
|
||||
if (watchpoint->set <= 0) {
|
||||
LOG_WARNING("watchpoint (wpid: %d) not set",
|
||||
LOG_TARGET_WARNING(target, "watchpoint (wpid: %d) not set",
|
||||
watchpoint->unique_id);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
unsigned int dwt_num = watchpoint->set - 1;
|
||||
|
||||
LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
|
||||
LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%d address: 0x%08x clear",
|
||||
watchpoint->unique_id, dwt_num,
|
||||
(unsigned) watchpoint->address);
|
||||
|
||||
if (dwt_num >= cortex_m->dwt_num_comp) {
|
||||
LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
|
||||
LOG_TARGET_DEBUG(target, "Invalid DWT Comparator number in watchpoint");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -1841,13 +1841,13 @@ int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint
|
|||
struct cortex_m_common *cortex_m = target_to_cm(target);
|
||||
|
||||
if (cortex_m->dwt_comp_available < 1) {
|
||||
LOG_DEBUG("no comparators?");
|
||||
LOG_TARGET_DEBUG(target, "no comparators?");
|
||||
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
/* hardware doesn't support data value masking */
|
||||
if (watchpoint->mask != ~(uint32_t)0) {
|
||||
LOG_DEBUG("watchpoint value masks not supported");
|
||||
LOG_TARGET_DEBUG(target, "watchpoint value masks not supported");
|
||||
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
|
|
@ -1859,11 +1859,11 @@ int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint
|
|||
break;
|
||||
}
|
||||
if (mask == 16) {
|
||||
LOG_DEBUG("unsupported watchpoint length");
|
||||
LOG_TARGET_DEBUG(target, "unsupported watchpoint length");
|
||||
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||
}
|
||||
if (watchpoint->address & ((1 << mask) - 1)) {
|
||||
LOG_DEBUG("watchpoint address is unaligned");
|
||||
LOG_TARGET_DEBUG(target, "watchpoint address is unaligned");
|
||||
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
|
|
@ -1875,12 +1875,12 @@ int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint
|
|||
* the data, and another comparator (DATAVADDR0) matching addr.
|
||||
*/
|
||||
if (watchpoint->value) {
|
||||
LOG_DEBUG("data value watchpoint not YET supported");
|
||||
LOG_TARGET_DEBUG(target, "data value watchpoint not YET supported");
|
||||
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||
}
|
||||
|
||||
cortex_m->dwt_comp_available--;
|
||||
LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
|
||||
LOG_TARGET_DEBUG(target, "dwt_comp_available: %d", cortex_m->dwt_comp_available);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -1891,7 +1891,7 @@ int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpo
|
|||
|
||||
/* REVISIT why check? DWT can be updated with core running ... */
|
||||
if (target->state != TARGET_HALTED) {
|
||||
LOG_WARNING("target not halted");
|
||||
LOG_TARGET_WARNING(target, "target not halted");
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
|
|
@ -1899,7 +1899,7 @@ int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpo
|
|||
cortex_m_unset_watchpoint(target, watchpoint);
|
||||
|
||||
cortex_m->dwt_comp_available++;
|
||||
LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
|
||||
LOG_TARGET_DEBUG(target, "dwt_comp_available: %d", cortex_m->dwt_comp_available);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -2004,18 +2004,18 @@ int cortex_m_profiling(struct target *target, uint32_t *samples,
|
|||
|
||||
retval = target_read_u32(target, DWT_PCSR, ®_value);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("Error while reading PCSR");
|
||||
LOG_TARGET_ERROR(target, "Error while reading PCSR");
|
||||
return retval;
|
||||
}
|
||||
if (reg_value == 0) {
|
||||
LOG_INFO("PCSR sampling not supported on this processor.");
|
||||
LOG_TARGET_INFO(target, "PCSR sampling not supported on this processor.");
|
||||
return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
|
||||
}
|
||||
|
||||
gettimeofday(&timeout, NULL);
|
||||
timeval_add_time(&timeout, seconds, 0);
|
||||
|
||||
LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
|
||||
LOG_TARGET_INFO(target, "Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
|
||||
|
||||
/* Make sure the target is running */
|
||||
target_poll(target);
|
||||
|
|
@ -2023,7 +2023,7 @@ int cortex_m_profiling(struct target *target, uint32_t *samples,
|
|||
retval = target_resume(target, 1, 0, 0, 0);
|
||||
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("Error while resuming target");
|
||||
LOG_TARGET_ERROR(target, "Error while resuming target");
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
|
@ -2044,14 +2044,14 @@ int cortex_m_profiling(struct target *target, uint32_t *samples,
|
|||
}
|
||||
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("Error while reading PCSR");
|
||||
LOG_TARGET_ERROR(target, "Error while reading PCSR");
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
gettimeofday(&now, NULL);
|
||||
if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
|
||||
LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
|
||||
LOG_TARGET_INFO(target, "Profiling completed. %" PRIu32 " samples.", sample_count);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -2162,14 +2162,14 @@ static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target
|
|||
int reg;
|
||||
|
||||
target_read_u32(target, DWT_CTRL, &dwtcr);
|
||||
LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
|
||||
LOG_TARGET_DEBUG(target, "DWT_CTRL: 0x%" PRIx32, dwtcr);
|
||||
if (!dwtcr) {
|
||||
LOG_DEBUG("no DWT");
|
||||
LOG_TARGET_DEBUG(target, "no DWT");
|
||||
return;
|
||||
}
|
||||
|
||||
target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
|
||||
LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
|
||||
LOG_TARGET_DEBUG(target, "DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
|
||||
|
||||
cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
|
||||
cm->dwt_comp_available = cm->dwt_num_comp;
|
||||
|
|
@ -2178,7 +2178,7 @@ static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target
|
|||
if (!cm->dwt_comparator_list) {
|
||||
fail0:
|
||||
cm->dwt_num_comp = 0;
|
||||
LOG_ERROR("out of mem");
|
||||
LOG_TARGET_ERROR(target, "out of mem");
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -2216,7 +2216,7 @@ fail1:
|
|||
*register_get_last_cache_p(&target->reg_cache) = cache;
|
||||
cm->dwt_cache = cache;
|
||||
|
||||
LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
|
||||
LOG_TARGET_DEBUG(target, "DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
|
||||
dwtcr, cm->dwt_num_comp,
|
||||
(dwtcr & (0xf << 24)) ? " only" : "/trigger");
|
||||
|
||||
|
|
@ -2283,7 +2283,7 @@ int cortex_m_examine(struct target *target)
|
|||
/* Search for the MEM-AP */
|
||||
retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("Could not find MEM-AP to control the core");
|
||||
LOG_TARGET_ERROR(target, "Could not find MEM-AP to control the core");
|
||||
return retval;
|
||||
}
|
||||
} else {
|
||||
|
|
@ -2316,14 +2316,13 @@ int cortex_m_examine(struct target *target)
|
|||
}
|
||||
|
||||
if (!cortex_m->core_info) {
|
||||
LOG_ERROR("Cortex-M PARTNO 0x%x is unrecognized", core_partno);
|
||||
LOG_TARGET_ERROR(target, "Cortex-M PARTNO 0x%x is unrecognized", core_partno);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
armv7m->arm.arch = cortex_m->core_info->arch;
|
||||
|
||||
LOG_INFO("%s: %s r%" PRId8 "p%" PRId8 " processor detected",
|
||||
target_name(target),
|
||||
LOG_TARGET_INFO(target, "%s r%" PRId8 "p%" PRId8 " processor detected",
|
||||
cortex_m->core_info->name,
|
||||
(uint8_t)((cpuid >> 20) & 0xf),
|
||||
(uint8_t)((cpuid >> 0) & 0xf));
|
||||
|
|
@ -2334,11 +2333,11 @@ int cortex_m_examine(struct target *target)
|
|||
rev = (cpuid >> 20) & 0xf;
|
||||
patch = (cpuid >> 0) & 0xf;
|
||||
if ((rev == 0) && (patch < 2)) {
|
||||
LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
|
||||
LOG_TARGET_WARNING(target, "Silicon bug: single stepping may enter pending exception handler!");
|
||||
cortex_m->maskints_erratum = true;
|
||||
}
|
||||
}
|
||||
LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
|
||||
LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32 "", cpuid);
|
||||
|
||||
if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV4) {
|
||||
target_read_u32(target, MVFR0, &mvfr0);
|
||||
|
|
@ -2346,7 +2345,7 @@ int cortex_m_examine(struct target *target)
|
|||
|
||||
/* test for floating point feature on Cortex-M4 */
|
||||
if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
|
||||
LOG_DEBUG("%s floating point feature FPv4_SP found", cortex_m->core_info->name);
|
||||
LOG_TARGET_DEBUG(target, "%s floating point feature FPv4_SP found", cortex_m->core_info->name);
|
||||
armv7m->fp_feature = FPV4_SP;
|
||||
}
|
||||
} else if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV5) {
|
||||
|
|
@ -2355,10 +2354,10 @@ int cortex_m_examine(struct target *target)
|
|||
|
||||
/* test for floating point features on Cortex-M7 */
|
||||
if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
|
||||
LOG_DEBUG("%s floating point feature FPv5_SP found", cortex_m->core_info->name);
|
||||
LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_SP found", cortex_m->core_info->name);
|
||||
armv7m->fp_feature = FPV5_SP;
|
||||
} else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
|
||||
LOG_DEBUG("%s floating point feature FPv5_DP found", cortex_m->core_info->name);
|
||||
LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_DP found", cortex_m->core_info->name);
|
||||
armv7m->fp_feature = FPV5_DP;
|
||||
}
|
||||
}
|
||||
|
|
@ -2428,7 +2427,7 @@ int cortex_m_examine(struct target *target)
|
|||
/* make sure we clear any breakpoints enabled on the target */
|
||||
target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
|
||||
}
|
||||
LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
|
||||
LOG_TARGET_DEBUG(target, "FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
|
||||
fpcr,
|
||||
cortex_m->fp_num_code,
|
||||
cortex_m->fp_num_lit);
|
||||
|
|
@ -2438,8 +2437,7 @@ int cortex_m_examine(struct target *target)
|
|||
cortex_m_dwt_setup(cortex_m, target);
|
||||
|
||||
/* These hardware breakpoints only work for code in flash! */
|
||||
LOG_INFO("%s: target has %d breakpoints, %d watchpoints",
|
||||
target_name(target),
|
||||
LOG_TARGET_INFO(target, "target has %d breakpoints, %d watchpoints",
|
||||
cortex_m->fp_num_code,
|
||||
cortex_m->dwt_num_comp);
|
||||
}
|
||||
|
|
@ -2462,7 +2460,7 @@ static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctr
|
|||
*ctrl = (uint8_t)dcrdr;
|
||||
*value = (uint8_t)(dcrdr >> 8);
|
||||
|
||||
LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
|
||||
LOG_TARGET_DEBUG(target, "data 0x%x ctrl 0x%x", *value, *ctrl);
|
||||
|
||||
/* write ack back to software dcc register
|
||||
* signify we have read data */
|
||||
|
|
@ -2569,7 +2567,7 @@ static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
|
|||
|
||||
struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
|
||||
if (!cortex_m) {
|
||||
LOG_ERROR("No memory creating target");
|
||||
LOG_TARGET_ERROR(target, "No memory creating target");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
|
|
@ -2626,7 +2624,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
|
|||
return retval;
|
||||
|
||||
if (!target_was_examined(target)) {
|
||||
LOG_ERROR("Target not examined yet");
|
||||
LOG_TARGET_ERROR(target, "Target not examined yet");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
|
|
@ -2655,7 +2653,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
|
|||
break;
|
||||
}
|
||||
if (i == ARRAY_SIZE(vec_ids)) {
|
||||
LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
|
||||
LOG_TARGET_ERROR(target, "No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
}
|
||||
|
|
@ -2745,7 +2743,7 @@ COMMAND_HANDLER(handle_cortex_m_reset_config_command)
|
|||
else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
|
||||
if (target_was_examined(target)
|
||||
&& !cortex_m->vectreset_supported)
|
||||
LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
|
||||
LOG_TARGET_WARNING(target, "VECTRESET is not supported on your Cortex-M core!");
|
||||
else
|
||||
cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue