rtos: use struct member names instead of comments

This is more readable, and as a bonus the compiler will help out if the
definition of the struct changes.

Change-Id: Ibf660134d9900173f6592407d5cc2203654a4a1b
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6659
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

src/rtos/ThreadX.c

@@ -112,18 +112,16 @@ static const struct stack_register_offset rtos_threadx_arm926ejs_stack_offsets_i
 
 static const struct rtos_register_stacking rtos_threadx_arm926ejs_stacking[] = {
 {
-	ARM926EJS_REGISTERS_SIZE_SOLICITED,	/* stack_registers_size */
-	-1,									/* stack_growth_direction */
-	17,									/* num_output_registers */
-	NULL,								/* stack_alignment */
-	rtos_threadx_arm926ejs_stack_offsets_solicited	/* register_offsets */
+	.stack_registers_size = ARM926EJS_REGISTERS_SIZE_SOLICITED,
+	.stack_growth_direction = -1,
+	.num_output_registers = 17,
+	.register_offsets = rtos_threadx_arm926ejs_stack_offsets_solicited
 },
 {
-	ARM926EJS_REGISTERS_SIZE_INTERRUPT,	/* stack_registers_size */
-	-1,									/* stack_growth_direction */
-	17,									/* num_output_registers */
-	NULL,								/* stack_alignment */
-	rtos_threadx_arm926ejs_stack_offsets_interrupt	/* register_offsets */
+	.stack_registers_size = ARM926EJS_REGISTERS_SIZE_INTERRUPT,
+	.stack_growth_direction = -1,
+	.num_output_registers = 17,
+	.register_offsets = rtos_threadx_arm926ejs_stack_offsets_interrupt
 },
 };
 

src/rtos/nuttx.c

@@ -119,11 +119,10 @@ static const struct stack_register_offset nuttx_stack_offsets_cortex_m[] = {
 
 
 static const struct rtos_register_stacking nuttx_stacking_cortex_m = {
-	0x48,                                   /* stack_registers_size */
-	-1,                                     /* stack_growth_direction */
-	17,                                     /* num_output_registers */
-	0,                                      /* stack_alignment */
-	nuttx_stack_offsets_cortex_m   /* register_offsets */
+	.stack_registers_size = 0x48,
+	.stack_growth_direction = -1,
+	.num_output_registers = 17,
+	.register_offsets = nuttx_stack_offsets_cortex_m
 };
 
 static const struct stack_register_offset nuttx_stack_offsets_cortex_m_fpu[] = {
@@ -147,11 +146,10 @@ static const struct stack_register_offset nuttx_stack_offsets_cortex_m_fpu[] = {
 };
 
 static const struct rtos_register_stacking nuttx_stacking_cortex_m_fpu = {
-	0x8c,                                   /* stack_registers_size */
-	-1,                                     /* stack_growth_direction */
-	17,                                     /* num_output_registers */
-	0,                                      /* stack_alignment */
-	nuttx_stack_offsets_cortex_m_fpu        /* register_offsets */
+	.stack_registers_size = 0x8c,
+	.stack_growth_direction = -1,
+	.num_output_registers = 17,
+	.register_offsets = nuttx_stack_offsets_cortex_m_fpu
 };
 
 static int pid_offset = PID;

src/rtos/rtos_chibios_stackings.c

@@ -47,11 +47,10 @@ static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[ARM
 };
 
 const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking = {
-	0x24,					/* stack_registers_size */
-	-1,						/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	NULL,					/* stack_alignment */
-	rtos_chibios_arm_v7m_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x24,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.register_offsets = rtos_chibios_arm_v7m_stack_offsets
 };
 
 static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets_w_fpu[ARMV7M_NUM_CORE_REGS] = {
@@ -75,9 +74,8 @@ static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets_w_f
 };
 
 const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking_w_fpu = {
-	0x64,										/* stack_registers_size */
-	-1,											/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,						/* num_output_registers */
-	NULL,										/* stack_alignment */
-	rtos_chibios_arm_v7m_stack_offsets_w_fpu	/* register_offsets */
+	.stack_registers_size = 0x64,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.register_offsets = rtos_chibios_arm_v7m_stack_offsets_w_fpu
 };

src/rtos/rtos_ecos_stackings.c

@@ -43,9 +43,9 @@ static const struct stack_register_offset rtos_ecos_cortex_m3_stack_offsets[ARMV
 };
 
 const struct rtos_register_stacking rtos_ecos_cortex_m3_stacking = {
-	0x44,					/* stack_registers_size */
-	-1,						/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	rtos_generic_stack_align8,	/* stack_alignment */
-	rtos_ecos_cortex_m3_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x44,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.calculate_process_stack = rtos_generic_stack_align8,
+	.register_offsets = rtos_ecos_cortex_m3_stack_offsets
 };

src/rtos/rtos_embkernel_stackings.c

@@ -45,9 +45,9 @@ static const struct stack_register_offset rtos_embkernel_cortex_m_stack_offsets[
 };
 
 const struct rtos_register_stacking rtos_embkernel_cortex_m_stacking = {
-	0x40,					/* stack_registers_size */
-	-1,						/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	rtos_generic_stack_align8,	/* stack_alignment */
-	rtos_embkernel_cortex_m_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x40,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.calculate_process_stack = rtos_generic_stack_align8,
+	.register_offsets = rtos_embkernel_cortex_m_stack_offsets
 };

src/rtos/rtos_mqx_stackings.c

@@ -71,9 +71,8 @@ static const struct stack_register_offset rtos_mqx_arm_v7m_stack_offsets[ARMV7M_
 };
 
 const struct rtos_register_stacking rtos_mqx_arm_v7m_stacking = {
-	0x4C,					/* stack_registers_size, calculate offset base address */
-	-1,						/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	NULL,					/* stack_alignment */
-	rtos_mqx_arm_v7m_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x4C,					/* calculate offset base address */
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.register_offsets = rtos_mqx_arm_v7m_stack_offsets
 };

src/rtos/rtos_riot_stackings.c

@@ -58,11 +58,11 @@ static const struct stack_register_offset rtos_riot_cortex_m0_stack_offsets[ARMV
 };
 
 const struct rtos_register_stacking rtos_riot_cortex_m0_stacking = {
-	0x44,					/* stack_registers_size */
-	-1,						/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	rtos_riot_cortex_m_stack_align,		/* stack_alignment */
-	rtos_riot_cortex_m0_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x44,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.calculate_process_stack = rtos_riot_cortex_m_stack_align,
+	.register_offsets = rtos_riot_cortex_m0_stack_offsets
 };
 
 /* see thread_arch.c */
@@ -87,9 +87,9 @@ static const struct stack_register_offset rtos_riot_cortex_m34_stack_offsets[ARM
 };
 
 const struct rtos_register_stacking rtos_riot_cortex_m34_stacking = {
-	0x44,			/* stack_registers_size */
-	-1,			/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	rtos_riot_cortex_m_stack_align,	/* stack_alignment */
-	rtos_riot_cortex_m34_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x44,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.calculate_process_stack = rtos_riot_cortex_m_stack_align,
+	.register_offsets = rtos_riot_cortex_m34_stack_offsets
 };

src/rtos/rtos_standard_stackings.c

@@ -249,41 +249,41 @@ static target_addr_t rtos_standard_cortex_m4f_fpu_stack_align(struct target *tar
 
 
 const struct rtos_register_stacking rtos_standard_cortex_m3_stacking = {
-	0x40,					/* stack_registers_size */
-	-1,						/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	rtos_standard_cortex_m3_stack_align,	/* stack_alignment */
-	rtos_standard_cortex_m3_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x40,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.calculate_process_stack = rtos_standard_cortex_m3_stack_align,
+	.register_offsets = rtos_standard_cortex_m3_stack_offsets
 };
 
 const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking = {
-	0x44,					/* stack_registers_size 4 more for LR*/
-	-1,						/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	rtos_standard_cortex_m4f_stack_align,	/* stack_alignment */
-	rtos_standard_cortex_m4f_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x44,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.calculate_process_stack = rtos_standard_cortex_m4f_stack_align,
+	.register_offsets = rtos_standard_cortex_m4f_stack_offsets
 };
 
 const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking = {
-	0xcc,					/* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/
-	-1,						/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	rtos_standard_cortex_m4f_fpu_stack_align,	/* stack_alignment */
-	rtos_standard_cortex_m4f_fpu_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0xcc,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.calculate_process_stack = rtos_standard_cortex_m4f_fpu_stack_align,
+	.register_offsets = rtos_standard_cortex_m4f_fpu_stack_offsets
 };
 
 const struct rtos_register_stacking rtos_standard_cortex_r4_stacking = {
-	0x48,				/* stack_registers_size */
-	-1,					/* stack_growth_direction */
-	26,					/* num_output_registers */
-	rtos_generic_stack_align8,	/* stack_alignment */
-	rtos_standard_cortex_r4_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x48,
+	.stack_growth_direction = -1,
+	.num_output_registers = 26,
+	.calculate_process_stack = rtos_generic_stack_align8,
+	.register_offsets = rtos_standard_cortex_r4_stack_offsets
 };
 
 const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking = {
-	0x90,				/* stack_registers_size */
-	-1,					/* stack_growth_direction */
-	32,					/* num_output_registers */
-	rtos_generic_stack_align8,	/* stack_alignment */
-	rtos_standard_nds32_n1068_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x90,
+	.stack_growth_direction = -1,
+	.num_output_registers = 32,
+	.calculate_process_stack = rtos_generic_stack_align8,
+	.register_offsets = rtos_standard_nds32_n1068_stack_offsets
 };

src/rtos/rtos_ucos_iii_stackings.c

@@ -68,17 +68,16 @@ static const struct stack_register_offset rtos_ucos_iii_esi_risc_stack_offsets[]
 };
 
 const struct rtos_register_stacking rtos_ucos_iii_cortex_m_stacking = {
-	0x40,												/* stack_registers_size */
-	-1,													/* stack_growth_direction */
-	ARRAY_SIZE(rtos_ucos_iii_cortex_m_stack_offsets),	/* num_output_registers */
-	rtos_generic_stack_align8,							/* stack_alignment */
-	rtos_ucos_iii_cortex_m_stack_offsets				/* register_offsets */
+	.stack_registers_size = 0x40,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARRAY_SIZE(rtos_ucos_iii_cortex_m_stack_offsets),
+	.calculate_process_stack = rtos_generic_stack_align8,
+	.register_offsets = rtos_ucos_iii_cortex_m_stack_offsets
 };
 
 const struct rtos_register_stacking rtos_ucos_iii_esi_risc_stacking = {
-	0x4c,												/* stack_registers_size */
-	-1,													/* stack_growth_direction */
-	ARRAY_SIZE(rtos_ucos_iii_esi_risc_stack_offsets),	/* num_output_registers */
-	NULL,												/* stack_alignment */
-	rtos_ucos_iii_esi_risc_stack_offsets				/* register_offsets */
+	.stack_registers_size = 0x4c,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARRAY_SIZE(rtos_ucos_iii_esi_risc_stack_offsets),
+	.register_offsets = rtos_ucos_iii_esi_risc_stack_offsets
 };