rtos: use struct member names instead of comments
This is more readable, and as a bonus the compiler will help out if the definition of the struct changes. Change-Id: Ibf660134d9900173f6592407d5cc2203654a4a1b Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6659 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
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@ -112,18 +112,16 @@ static const struct stack_register_offset rtos_threadx_arm926ejs_stack_offsets_i
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static const struct rtos_register_stacking rtos_threadx_arm926ejs_stacking[] = {
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static const struct rtos_register_stacking rtos_threadx_arm926ejs_stacking[] = {
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{
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{
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ARM926EJS_REGISTERS_SIZE_SOLICITED, /* stack_registers_size */
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.stack_registers_size = ARM926EJS_REGISTERS_SIZE_SOLICITED,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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17, /* num_output_registers */
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.num_output_registers = 17,
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NULL, /* stack_alignment */
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.register_offsets = rtos_threadx_arm926ejs_stack_offsets_solicited
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rtos_threadx_arm926ejs_stack_offsets_solicited /* register_offsets */
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},
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},
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{
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{
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ARM926EJS_REGISTERS_SIZE_INTERRUPT, /* stack_registers_size */
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.stack_registers_size = ARM926EJS_REGISTERS_SIZE_INTERRUPT,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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17, /* num_output_registers */
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.num_output_registers = 17,
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NULL, /* stack_alignment */
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.register_offsets = rtos_threadx_arm926ejs_stack_offsets_interrupt
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rtos_threadx_arm926ejs_stack_offsets_interrupt /* register_offsets */
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},
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},
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};
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};
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@ -119,11 +119,10 @@ static const struct stack_register_offset nuttx_stack_offsets_cortex_m[] = {
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static const struct rtos_register_stacking nuttx_stacking_cortex_m = {
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static const struct rtos_register_stacking nuttx_stacking_cortex_m = {
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0x48, /* stack_registers_size */
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.stack_registers_size = 0x48,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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17, /* num_output_registers */
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.num_output_registers = 17,
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0, /* stack_alignment */
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.register_offsets = nuttx_stack_offsets_cortex_m
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nuttx_stack_offsets_cortex_m /* register_offsets */
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};
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};
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static const struct stack_register_offset nuttx_stack_offsets_cortex_m_fpu[] = {
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static const struct stack_register_offset nuttx_stack_offsets_cortex_m_fpu[] = {
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@ -147,11 +146,10 @@ static const struct stack_register_offset nuttx_stack_offsets_cortex_m_fpu[] = {
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};
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};
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static const struct rtos_register_stacking nuttx_stacking_cortex_m_fpu = {
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static const struct rtos_register_stacking nuttx_stacking_cortex_m_fpu = {
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0x8c, /* stack_registers_size */
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.stack_registers_size = 0x8c,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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17, /* num_output_registers */
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.num_output_registers = 17,
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0, /* stack_alignment */
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.register_offsets = nuttx_stack_offsets_cortex_m_fpu
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nuttx_stack_offsets_cortex_m_fpu /* register_offsets */
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};
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};
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static int pid_offset = PID;
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static int pid_offset = PID;
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@ -47,11 +47,10 @@ static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[ARM
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};
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};
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const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking = {
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const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking = {
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0x24, /* stack_registers_size */
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.stack_registers_size = 0x24,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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NULL, /* stack_alignment */
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.register_offsets = rtos_chibios_arm_v7m_stack_offsets
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rtos_chibios_arm_v7m_stack_offsets /* register_offsets */
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};
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};
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static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets_w_fpu[ARMV7M_NUM_CORE_REGS] = {
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static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets_w_fpu[ARMV7M_NUM_CORE_REGS] = {
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@ -75,9 +74,8 @@ static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets_w_f
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};
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};
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const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking_w_fpu = {
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const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking_w_fpu = {
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0x64, /* stack_registers_size */
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.stack_registers_size = 0x64,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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NULL, /* stack_alignment */
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.register_offsets = rtos_chibios_arm_v7m_stack_offsets_w_fpu
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rtos_chibios_arm_v7m_stack_offsets_w_fpu /* register_offsets */
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};
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};
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@ -43,9 +43,9 @@ static const struct stack_register_offset rtos_ecos_cortex_m3_stack_offsets[ARMV
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};
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};
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const struct rtos_register_stacking rtos_ecos_cortex_m3_stacking = {
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const struct rtos_register_stacking rtos_ecos_cortex_m3_stacking = {
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0x44, /* stack_registers_size */
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.stack_registers_size = 0x44,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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rtos_generic_stack_align8, /* stack_alignment */
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.calculate_process_stack = rtos_generic_stack_align8,
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rtos_ecos_cortex_m3_stack_offsets /* register_offsets */
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.register_offsets = rtos_ecos_cortex_m3_stack_offsets
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};
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};
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@ -45,9 +45,9 @@ static const struct stack_register_offset rtos_embkernel_cortex_m_stack_offsets[
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};
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};
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const struct rtos_register_stacking rtos_embkernel_cortex_m_stacking = {
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const struct rtos_register_stacking rtos_embkernel_cortex_m_stacking = {
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0x40, /* stack_registers_size */
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.stack_registers_size = 0x40,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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rtos_generic_stack_align8, /* stack_alignment */
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.calculate_process_stack = rtos_generic_stack_align8,
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rtos_embkernel_cortex_m_stack_offsets /* register_offsets */
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.register_offsets = rtos_embkernel_cortex_m_stack_offsets
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};
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};
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@ -71,9 +71,8 @@ static const struct stack_register_offset rtos_mqx_arm_v7m_stack_offsets[ARMV7M_
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};
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};
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const struct rtos_register_stacking rtos_mqx_arm_v7m_stacking = {
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const struct rtos_register_stacking rtos_mqx_arm_v7m_stacking = {
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0x4C, /* stack_registers_size, calculate offset base address */
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.stack_registers_size = 0x4C, /* calculate offset base address */
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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NULL, /* stack_alignment */
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.register_offsets = rtos_mqx_arm_v7m_stack_offsets
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rtos_mqx_arm_v7m_stack_offsets /* register_offsets */
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};
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};
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@ -58,11 +58,11 @@ static const struct stack_register_offset rtos_riot_cortex_m0_stack_offsets[ARMV
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};
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};
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const struct rtos_register_stacking rtos_riot_cortex_m0_stacking = {
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const struct rtos_register_stacking rtos_riot_cortex_m0_stacking = {
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0x44, /* stack_registers_size */
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.stack_registers_size = 0x44,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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rtos_riot_cortex_m_stack_align, /* stack_alignment */
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.calculate_process_stack = rtos_riot_cortex_m_stack_align,
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rtos_riot_cortex_m0_stack_offsets /* register_offsets */
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.register_offsets = rtos_riot_cortex_m0_stack_offsets
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};
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};
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/* see thread_arch.c */
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/* see thread_arch.c */
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@ -87,9 +87,9 @@ static const struct stack_register_offset rtos_riot_cortex_m34_stack_offsets[ARM
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};
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};
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const struct rtos_register_stacking rtos_riot_cortex_m34_stacking = {
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const struct rtos_register_stacking rtos_riot_cortex_m34_stacking = {
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0x44, /* stack_registers_size */
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.stack_registers_size = 0x44,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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rtos_riot_cortex_m_stack_align, /* stack_alignment */
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.calculate_process_stack = rtos_riot_cortex_m_stack_align,
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rtos_riot_cortex_m34_stack_offsets /* register_offsets */
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.register_offsets = rtos_riot_cortex_m34_stack_offsets
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};
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};
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@ -249,41 +249,41 @@ static target_addr_t rtos_standard_cortex_m4f_fpu_stack_align(struct target *tar
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const struct rtos_register_stacking rtos_standard_cortex_m3_stacking = {
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const struct rtos_register_stacking rtos_standard_cortex_m3_stacking = {
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0x40, /* stack_registers_size */
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.stack_registers_size = 0x40,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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rtos_standard_cortex_m3_stack_align, /* stack_alignment */
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.calculate_process_stack = rtos_standard_cortex_m3_stack_align,
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rtos_standard_cortex_m3_stack_offsets /* register_offsets */
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.register_offsets = rtos_standard_cortex_m3_stack_offsets
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};
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};
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const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking = {
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const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking = {
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0x44, /* stack_registers_size 4 more for LR*/
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.stack_registers_size = 0x44,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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rtos_standard_cortex_m4f_stack_align, /* stack_alignment */
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.calculate_process_stack = rtos_standard_cortex_m4f_stack_align,
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rtos_standard_cortex_m4f_stack_offsets /* register_offsets */
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.register_offsets = rtos_standard_cortex_m4f_stack_offsets
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};
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};
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const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking = {
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const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking = {
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0xcc, /* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/
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.stack_registers_size = 0xcc,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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rtos_standard_cortex_m4f_fpu_stack_align, /* stack_alignment */
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.calculate_process_stack = rtos_standard_cortex_m4f_fpu_stack_align,
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rtos_standard_cortex_m4f_fpu_stack_offsets /* register_offsets */
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.register_offsets = rtos_standard_cortex_m4f_fpu_stack_offsets
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};
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};
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const struct rtos_register_stacking rtos_standard_cortex_r4_stacking = {
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const struct rtos_register_stacking rtos_standard_cortex_r4_stacking = {
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0x48, /* stack_registers_size */
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.stack_registers_size = 0x48,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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26, /* num_output_registers */
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.num_output_registers = 26,
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rtos_generic_stack_align8, /* stack_alignment */
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.calculate_process_stack = rtos_generic_stack_align8,
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rtos_standard_cortex_r4_stack_offsets /* register_offsets */
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.register_offsets = rtos_standard_cortex_r4_stack_offsets
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};
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};
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const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking = {
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const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking = {
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0x90, /* stack_registers_size */
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.stack_registers_size = 0x90,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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32, /* num_output_registers */
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.num_output_registers = 32,
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rtos_generic_stack_align8, /* stack_alignment */
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.calculate_process_stack = rtos_generic_stack_align8,
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rtos_standard_nds32_n1068_stack_offsets /* register_offsets */
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.register_offsets = rtos_standard_nds32_n1068_stack_offsets
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};
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};
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@ -68,17 +68,16 @@ static const struct stack_register_offset rtos_ucos_iii_esi_risc_stack_offsets[]
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};
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};
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const struct rtos_register_stacking rtos_ucos_iii_cortex_m_stacking = {
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const struct rtos_register_stacking rtos_ucos_iii_cortex_m_stacking = {
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0x40, /* stack_registers_size */
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.stack_registers_size = 0x40,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARRAY_SIZE(rtos_ucos_iii_cortex_m_stack_offsets), /* num_output_registers */
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.num_output_registers = ARRAY_SIZE(rtos_ucos_iii_cortex_m_stack_offsets),
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rtos_generic_stack_align8, /* stack_alignment */
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.calculate_process_stack = rtos_generic_stack_align8,
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rtos_ucos_iii_cortex_m_stack_offsets /* register_offsets */
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.register_offsets = rtos_ucos_iii_cortex_m_stack_offsets
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};
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};
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const struct rtos_register_stacking rtos_ucos_iii_esi_risc_stacking = {
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const struct rtos_register_stacking rtos_ucos_iii_esi_risc_stacking = {
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0x4c, /* stack_registers_size */
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.stack_registers_size = 0x4c,
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-1, /* stack_growth_direction */
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.stack_growth_direction = -1,
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ARRAY_SIZE(rtos_ucos_iii_esi_risc_stack_offsets), /* num_output_registers */
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.num_output_registers = ARRAY_SIZE(rtos_ucos_iii_esi_risc_stack_offsets),
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NULL, /* stack_alignment */
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.register_offsets = rtos_ucos_iii_esi_risc_stack_offsets
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rtos_ucos_iii_esi_risc_stack_offsets /* register_offsets */
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};
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};
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