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tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change

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Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Fix manually the remaining lines that don't match simple patterns
and would require dedicated boring scripting.
Remove the 'expr' command where appropriate.

Change-Id: Ia75210c8447f88d38515addab4a836af9103096d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6161
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo 2021-04-10 18:28:52 +02:00
parent f855fdcf0d
commit 64d89d5ee1
33 changed files with 109 additions and 109 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tcl/bitsbytes.tcl
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@ -36,7 +36,7 @@ proc create_mask { MSB LSB } {
# Result: 0x02340000 # Result: 0x02340000
proc extract_bitfield { VALUE MSB LSB } { proc extract_bitfield { VALUE MSB LSB } {
return [expr [create_mask $MSB $LSB] & $VALUE] return [expr {[create_mask $MSB $LSB] & $VALUE}]
} }
@ -47,7 +47,7 @@ proc extract_bitfield { VALUE MSB LSB } {
# Result: 0x00000234 # Result: 0x00000234
# #
proc normalize_bitfield { VALUE MSB LSB } { proc normalize_bitfield { VALUE MSB LSB } {
return [expr [extract_bitfield $VALUE $MSB $LSB ] >> $LSB] return [expr {[extract_bitfield $VALUE $MSB $LSB ] >> $LSB}]
} }
proc show_normalize_bitfield { VALUE MSB LSB } { proc show_normalize_bitfield { VALUE MSB LSB } {

4
tcl/board/at91sam9261-ek.cfg
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@ -29,7 +29,7 @@ proc at91sam9261ek_reset_init { } {
;# set master_pll_div 1 ;# set master_pll_div 1
;# set master_pll_mul 13 ;# set master_pll_mul 13
set val [expr $::AT91_WDT_WDV] ;# Counter Value set val $::AT91_WDT_WDV ;# Counter Value
set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt
@ -42,7 +42,7 @@ proc at91sam9261ek_reset_init { } {
set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}] set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
;# SDRAMC_CR - Configuration register ;# SDRAMC_CR - Configuration register
set val [expr $::AT91_SDRAMC_NC_9] set val $::AT91_SDRAMC_NC_9
set val [expr {$val | $::AT91_SDRAMC_NR_13}] set val [expr {$val | $::AT91_SDRAMC_NR_13}]
set val [expr {$val | $::AT91_SDRAMC_NB_4}] set val [expr {$val | $::AT91_SDRAMC_NB_4}]
set val [expr {$val | $::AT91_SDRAMC_CAS_3}] set val [expr {$val | $::AT91_SDRAMC_CAS_3}]

6
tcl/board/at91sam9263-ek.cfg
View File

@ -24,7 +24,7 @@ proc at91sam9263ek_reset_init { } {
set config(master_pll_div) 14 set config(master_pll_div) 14
set config(master_pll_mul) 171 set config(master_pll_mul) 171
set val [expr $::AT91_WDT_WDV] ;# Counter Value set val $::AT91_WDT_WDV ;# Counter Value
set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt
@ -36,13 +36,13 @@ proc at91sam9263ek_reset_init { } {
;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA
set val [expr $::AT91_MATRIX_EBI0_DBPUC] set val $::AT91_MATRIX_EBI0_DBPUC
set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}] set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}]
set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}] set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}]
set config(matrix_ebicsa_val) $val set config(matrix_ebicsa_val) $val
;# SDRAMC_CR - Configuration register ;# SDRAMC_CR - Configuration register
set val [expr $::AT91_SDRAMC_NC_9] set val $::AT91_SDRAMC_NC_9
set val [expr {$val | $::AT91_SDRAMC_NR_13}] set val [expr {$val | $::AT91_SDRAMC_NR_13}]
set val [expr {$val | $::AT91_SDRAMC_NB_4}] set val [expr {$val | $::AT91_SDRAMC_NB_4}]
set val [expr {$val | $::AT91_SDRAMC_CAS_3}] set val [expr {$val | $::AT91_SDRAMC_CAS_3}]

8
tcl/board/at91sam9g20-ek.cfg
View File

@ -77,25 +77,25 @@ proc at91sam9g20_reset_init { } {
# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR. # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
mww 0xfffffc20 0x00004001 mww 0xfffffc20 0x00004001
while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 } while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43). # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
mww 0xfffffc28 0x202a3f01 mww 0xfffffc28 0x202a3f01
while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 } while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
# Wait for MCKRDY signal from PMC_SR to assert. # Wait for MCKRDY signal from PMC_SR to assert.
mww 0xfffffc30 0x00000101 mww 0xfffffc30 0x00000101
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
# Now change PMC_MCKR register to select PLLA. # Now change PMC_MCKR register to select PLLA.
# Wait for MCKRDY signal from PMC_SR to assert. # Wait for MCKRDY signal from PMC_SR to assert.
mww 0xfffffc30 0x00001302 mww 0xfffffc30 0x00001302
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
# Processor and master clocks are now operating and stable at maximum frequency possible: # Processor and master clocks are now operating and stable at maximum frequency possible:
# -> MCLK = 132.096 MHz # -> MCLK = 132.096 MHz

2
tcl/board/dm355evm.cfg
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@ -87,7 +87,7 @@ proc dm355evm_init {} {
mmw $addr 0x2000 0 mmw $addr 0x2000 0
# wait for READY # wait for READY
while { [expr [mrw $addr] & 0x8000] == 0 } { sleep 1 } while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 }
# set IO_READY; then LOCK and PWRSAVE; then PWRDN # set IO_READY; then LOCK and PWRSAVE; then PWRDN
mmw $addr 0x4000 0 mmw $addr 0x4000 0

2
tcl/board/embedded-artists_lpc2478-32.cfg
View File

@ -125,7 +125,7 @@ proc init_board {} {
# #
proc enable_pll {} { proc enable_pll {} {
# Disconnect PLL in case it is already connected # Disconnect PLL in case it is already connected
if {[expr [read_register 0xE01FC080] & 0x03] == 3} { if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} {
# Disconnect it, but leave it enabled # Disconnect it, but leave it enabled
# (This MUST be done in two steps) # (This MUST be done in two steps)
mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL

4
tcl/board/hilscher_nxhx10.cfg
View File

@ -34,7 +34,7 @@ proc mread32 {addr} {
proc init_clocks { } { proc init_clocks { } {
puts "Enabling all clocks " puts "Enabling all clocks "
set accesskey [mread32 0x101c0070] set accesskey [mread32 0x101c0070]
mww 0x101c0070 [expr $accesskey] mww 0x101c0070 $accesskey
mww 0x101c0028 0x00007511 mww 0x101c0028 0x00007511
} }
@ -42,7 +42,7 @@ proc init_clocks { } {
proc init_sdrambus { } { proc init_sdrambus { } {
puts "Initializing external SDRAM Bus 16 Bit " puts "Initializing external SDRAM Bus 16 Bit "
set accesskey [mread32 0x101c0070] set accesskey [mread32 0x101c0070]
mww 0x101c0070 [expr $accesskey] mww 0x101c0070 $accesskey
mww 0x101c0C40 0x00000050 mww 0x101c0C40 0x00000050
puts "Configuring SDRAM controller for K4S561632E (32MB) " puts "Configuring SDRAM controller for K4S561632E (32MB) "

8
tcl/board/icnova_imx53_sodimm.cfg
View File

@ -69,7 +69,7 @@ proc init_l2cc { } {
set tR [arm mrc 15 0 1 0 1] set tR [arm mrc 15 0 1 0 1]
; #bic r0, r0, #0x2 ; #bic r0, r0, #0x2
; #mcr 15, 0, r0, c1, c0, 1 ; #mcr 15, 0, r0, c1, c0, 1
arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)] arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
; #/* reconfigure L2 cache aux control reg */ ; #/* reconfigure L2 cache aux control reg */
; #mov r0, #0xC0 /* tag RAM */ ; #mov r0, #0xC0 /* tag RAM */
@ -139,7 +139,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2 ; # change uart clk parent to pll2
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
; # make sure change is effective ; # make sure change is effective
while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
@ -157,7 +157,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6 ; # make uart div=6
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
; # Restore the default values in the Gate registers ; # Restore the default values in the Gate registers
mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
@ -243,7 +243,7 @@ proc setup_pll { PLL_ADDR CLK } {
mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
} }

16
tcl/board/icnova_sam9g45_sodimm.cfg
View File

@ -89,27 +89,27 @@ proc at91sam9g45_init { } {
# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR. # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
mww 0xfffffc20 0x00004001 mww 0xfffffc20 0x00004001
while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 } while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43). # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
#mww 0xfffffc28 0x202a3f01 #mww 0xfffffc28 0x202a3f01
mww 0xfffffc28 0x20c73f03 mww 0xfffffc28 0x20c73f03
while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 } while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
# Wait for MCKRDY signal from PMC_SR to assert. # Wait for MCKRDY signal from PMC_SR to assert.
#mww 0xfffffc30 0x00000101 #mww 0xfffffc30 0x00000101
mww 0xfffffc30 0x00001301 mww 0xfffffc30 0x00001301
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
# Now change PMC_MCKR register to select PLLA. # Now change PMC_MCKR register to select PLLA.
# Wait for MCKRDY signal from PMC_SR to assert. # Wait for MCKRDY signal from PMC_SR to assert.
mww 0xfffffc30 0x00001302 mww 0xfffffc30 0x00001302
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
# Processor and master clocks are now operating and stable at maximum frequency possible: # Processor and master clocks are now operating and stable at maximum frequency possible:
# -> MCLK = 132.096 MHz # -> MCLK = 132.096 MHz
@ -214,7 +214,7 @@ proc at91sam9g45_init { } {
sleep 1 sleep 1
# 9. Enable DLL Reset (set DLL bit) # 9. Enable DLL Reset (set DLL bit)
set CR [expr [read_register 0xffffe608] | 0x80] set CR [expr {[read_register 0xffffe608] | 0x80}]
mww 0xffffe608 $CR mww 0xffffe608 $CR
# 10. mode register cycle to reset the DLL # 10. mode register cycle to reset the DLL
@ -236,7 +236,7 @@ proc at91sam9g45_init { } {
# 12.3 delay 10 cycles # 12.3 delay 10 cycles
# 13. disable DLL reset (clear DLL bit) # 13. disable DLL reset (clear DLL bit)
set CR [expr [read_register 0xffffe608] & 0xffffff7f] set CR [expr {[read_register 0xffffe608] & 0xffffff7f}]
mww 0xffffe608 $CR mww 0xffffe608 $CR
# 14. mode register set cycle # 14. mode register set cycle
@ -244,7 +244,7 @@ proc at91sam9g45_init { } {
mww 0x70000000 0x1 mww 0x70000000 0x1
# 15. program OCD field (set OCD bits) # 15. program OCD field (set OCD bits)
set CR [expr [read_register 0xffffe608] | 0x7000] set CR [expr {[read_register 0xffffe608] | 0x7000}]
mww 0xffffe608 $CR mww 0xffffe608 $CR
# 16. (EMRS1) # 16. (EMRS1)
@ -253,7 +253,7 @@ proc at91sam9g45_init { } {
# 16.1 delay 2 cycles # 16.1 delay 2 cycles
# 17. disable OCD field (clear OCD bits) # 17. disable OCD field (clear OCD bits)
set CR [expr [read_register 0xffffe608] & 0xffff8fff] set CR [expr {[read_register 0xffffe608] & 0xffff8fff}]
mww 0xffffe608 $CR mww 0xffffe608 $CR
# 18. (EMRS1) # 18. (EMRS1)

8
tcl/board/imx53-m53evk.cfg
View File

@ -65,7 +65,7 @@ proc init_l2cc { } {
set tR [arm mrc 15 0 1 0 1] set tR [arm mrc 15 0 1 0 1]
; #bic r0, r0, #0x2 ; #bic r0, r0, #0x2
; #mcr 15, 0, r0, c1, c0, 1 ; #mcr 15, 0, r0, c1, c0, 1
arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)] arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
; #/* reconfigure L2 cache aux control reg */ ; #/* reconfigure L2 cache aux control reg */
; #mov r0, #0xC0 /* tag RAM */ ; #mov r0, #0xC0 /* tag RAM */
@ -135,7 +135,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2 ; # change uart clk parent to pll2
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
; # make sure change is effective ; # make sure change is effective
while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
@ -153,7 +153,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6 ; # make uart div=6
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
; # Restore the default values in the Gate registers ; # Restore the default values in the Gate registers
mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
@ -239,7 +239,7 @@ proc setup_pll { PLL_ADDR CLK } {
mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
} }

8
tcl/board/imx53loco.cfg
View File

@ -70,7 +70,7 @@ proc init_l2cc { } {
set tR [arm mrc 15 0 1 0 1] set tR [arm mrc 15 0 1 0 1]
; #bic r0, r0, #0x2 ; #bic r0, r0, #0x2
; #mcr 15, 0, r0, c1, c0, 1 ; #mcr 15, 0, r0, c1, c0, 1
arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)] arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
; #/* reconfigure L2 cache aux control reg */ ; #/* reconfigure L2 cache aux control reg */
; #mov r0, #0xC0 /* tag RAM */ ; #mov r0, #0xC0 /* tag RAM */
@ -140,7 +140,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2 ; # change uart clk parent to pll2
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000] mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
; # make sure change is effective ; # make sure change is effective
while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 } while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
@ -158,7 +158,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6 ; # make uart div=6
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a] mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
; # Restore the default values in the Gate registers ; # Restore the default values in the Gate registers
mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
@ -244,7 +244,7 @@ proc setup_pll { PLL_ADDR CLK } {
mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232 mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 } while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
} }

2
tcl/board/nxp_imx7sabre.cfg
View File

@ -27,7 +27,7 @@ proc imx7_uart_dbgconf { } {
} }
proc check_bits_set_32 { addr mask } { proc check_bits_set_32 { addr mask } {
while { [expr [mrw $addr] & $mask == 0] } { } while { [expr {[mrw $addr] & $mask} == 0] } { }
} }
proc apply_dcd { } { proc apply_dcd { } {

2
tcl/chip/atmel/at91/at91_pmc.cfg
View File

@ -87,7 +87,7 @@ set AT91_PMC_USBS_PLLA [expr {0 << 0}]
set AT91_PMC_USBS_UPLL [expr {1 << 0}] set AT91_PMC_USBS_UPLL [expr {1 << 0}]
set AT91_PMC_OHCIUSBDIV [expr {0xF << 8}] ;# Divider for USB OHCI Clock set AT91_PMC_OHCIUSBDIV [expr {0xF << 8}] ;# Divider for USB OHCI Clock
;# set AT91_PMC_PCKR(n) [expr ($AT91_PMC + 0x40 + ((n) * 4))] ;# Programmable Clock 0-N Registers ;# set AT91_PMC_PCKR(n) [expr {$AT91_PMC + 0x40 + ((n) * 4)}] ;# Programmable Clock 0-N Registers
set AT91_PMC_CSSMCK [expr {0x1 << 8}] ;# CSS or Master Clock Selection set AT91_PMC_CSSMCK [expr {0x1 << 8}] ;# CSS or Master Clock Selection
set AT91_PMC_CSSMCK_CSS [expr {0 << 8}] set AT91_PMC_CSSMCK_CSS [expr {0 << 8}]
set AT91_PMC_CSSMCK_MCK [expr {1 << 8}] set AT91_PMC_CSSMCK_MCK [expr {1 << 8}]

18
tcl/chip/atmel/at91/at91sam9_init.cfg
View File

@ -11,7 +11,7 @@ proc at91sam9_reset_start { } {
jtag_rclk 8 jtag_rclk 8
halt halt
wait_halt 10000 wait_halt 10000
set rstc_mr_val [expr $::AT91_RSTC_KEY] set rstc_mr_val $::AT91_RSTC_KEY
set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}] set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]
set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}] set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset. mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset.
@ -24,25 +24,25 @@ proc at91sam9_reset_init { config } {
set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}] set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]
mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc. mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc.
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 } while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS}] != $::AT91_PMC_MOSCS } { sleep 1 }
set pllar_val [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog set pllar_val $::AT91_PMC_PLLA_WR_ERRATA ;# Bit 29 must be 1 when prog
set pllar_val [expr {$pllar_val | $::AT91_PMC_OUT}] set pllar_val [expr {$pllar_val | $::AT91_PMC_OUT}]
set pllar_val [expr {$pllar_val | $::AT91_PMC_PLLCOUNT}] set pllar_val [expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]
set pllar_val [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)] set pllar_val [expr {$pllar_val | ($config(master_pll_mul) - 1) << 16}]
set pllar_val [expr ($pllar_val | $config(master_pll_div))] set pllar_val [expr {$pllar_val | $config(master_pll_div)}]
mww $::AT91_CKGR_PLLAR $pllar_val ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz mww $::AT91_CKGR_PLLAR $pllar_val ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA] != $::AT91_PMC_LOCKA } { sleep 1 } while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA}] != $::AT91_PMC_LOCKA } { sleep 1 }
;# PCK/2 = MCK Master Clock from PLLA ;# PCK/2 = MCK Master Clock from PLLA
set mckr_val [expr $::AT91_PMC_CSS_PLLA] set mckr_val $::AT91_PMC_CSS_PLLA
set mckr_val [expr {$mckr_val | $::AT91_PMC_PRES_1}] set mckr_val [expr {$mckr_val | $::AT91_PMC_PRES_1}]
set mckr_val [expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}] set mckr_val [expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]
set mckr_val [expr {$mckr_val | $::AT91_PMC_PDIV_1}] set mckr_val [expr {$mckr_val | $::AT91_PMC_PDIV_1}]
mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz) mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 } while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY}] != $::AT91_PMC_MCKRDY } { sleep 1 }
## switch JTAG clock to highspeed clock ## switch JTAG clock to highspeed clock
jtag_rclk 0 jtag_rclk 0
@ -50,7 +50,7 @@ proc at91sam9_reset_init { config } {
arm7_9 dcc_downloads enable ;# Enable faster DCC downloads arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
arm7_9 fast_memory_access enable arm7_9 fast_memory_access enable
set rstc_mr_val [expr ($::AT91_RSTC_KEY)] set rstc_mr_val $::AT91_RSTC_KEY
set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}] set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable

2
tcl/chip/atmel/at91/usarts.tcl
View File

@ -63,7 +63,7 @@ proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
} }
echo [format "\tParity: %s " $s] echo [format "\tParity: %s " $s]
set x [expr 5 + [show_normalize_bitfield $VAL 7 6]] set x [expr {5 + [show_normalize_bitfield $VAL 7 6]}]
echo [format "\tDatabits: %d" $x] echo [format "\tDatabits: %d" $x]
set x [show_normalize_bitfield $VAL 13 12] set x [show_normalize_bitfield $VAL 13 12]

2
tcl/chip/st/spear/quirk_no_srst.tcl
View File

@ -24,7 +24,7 @@ set sp_reset_mode ""
proc sp_is_halted {} { proc sp_is_halted {} {
global sp_target_name global sp_target_name
return [expr [string compare [$sp_target_name curstate] "halted" ] == 0] return [expr {[string compare [$sp_target_name curstate] "halted" ] == 0}]
} }
# wait for reset button to be pressed, causing CPU to get halted # wait for reset button to be pressed, causing CPU to get halted

8
tcl/chip/st/spear/spear3xx.tcl
View File

@ -19,7 +19,7 @@ proc sp3xx_clock_default {} {
mww 0xfca00014 0x0ffffff8 ;# set pll timeout to minimum (100us ?!?) mww 0xfca00014 0x0ffffff8 ;# set pll timeout to minimum (100us ?!?)
# DDRCORE disable to change frequency # DDRCORE disable to change frequency
set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000] set val [expr {([mrw 0xfca8002c] & ~0x20000000) | 0x40000000}]
mww 0xfca8002c $val mww 0xfca8002c $val
mww 0xfca8002c $val ;# Yes, write twice! mww 0xfca8002c $val ;# Yes, write twice!
@ -29,7 +29,7 @@ proc sp3xx_clock_default {} {
mww 0xfca80008 0x00001c0e ;# enable mww 0xfca80008 0x00001c0e ;# enable
mww 0xfca80008 0x00001c06 ;# strobe mww 0xfca80008 0x00001c06 ;# strobe
mww 0xfca80008 0x00001c0e mww 0xfca80008 0x00001c0e
while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 } while { [expr {[mrw 0xfca80008] & 0x01}] == 0x00 } { sleep 1 }
# programming PLL2 # programming PLL2
mww 0xfca80018 0xa600010c ;# M=166, P=1, N=12 mww 0xfca80018 0xa600010c ;# M=166, P=1, N=12
@ -37,13 +37,13 @@ proc sp3xx_clock_default {} {
mww 0xfca80014 0x00001c0e ;# enable mww 0xfca80014 0x00001c0e ;# enable
mww 0xfca80014 0x00001c06 ;# strobe mww 0xfca80014 0x00001c06 ;# strobe
mww 0xfca80014 0x00001c0e mww 0xfca80014 0x00001c0e
while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 } while { [expr {[mrw 0xfca80014] & 0x01}] == 0x00 } { sleep 1 }
mww 0xfca80028 0x00000082 ;# enable plltimeen mww 0xfca80028 0x00000082 ;# enable plltimeen
mww 0xfca80024 0x00000511 ;# set hclkdiv="/2" & pclkdiv="/2" mww 0xfca80024 0x00000511 ;# set hclkdiv="/2" & pclkdiv="/2"
mww 0xfca00000 0x00000004 ;# setting SYSCTL to NORMAL mode mww 0xfca00000 0x00000004 ;# setting SYSCTL to NORMAL mode
while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 } while { [expr {[mrw 0xfca00000] & 0x20}] != 0x20 } { sleep 1 }
# Select source of DDR clock # Select source of DDR clock
#mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1 #mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1

2
tcl/fpga/xilinx-xadc.cfg
View File

@ -16,7 +16,7 @@ proc xadc_cmd {cmd addr data} {
READ 0x01 READ 0x01
WRITE 0x02 WRITE 0x02
} }
return [expr ($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)] return [expr {($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)}]
} }
# XADC register addresses # XADC register addresses

2
tcl/memory.tcl
View File

@ -58,7 +58,7 @@ set ACCESS_WIDTH_ANY [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_
set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
proc iswithin { ADDRESS BASE LEN } { proc iswithin { ADDRESS BASE LEN } {
return [expr ((($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0))] return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}]
} }
proc address_info { ADDRESS } { proc address_info { ADDRESS } {

4
tcl/mmr_helpers.tcl
View File

@ -2,7 +2,7 @@
proc proc_exists { NAME } { proc proc_exists { NAME } {
set n [info commands $NAME] set n [info commands $NAME]
set l [string length $n] set l [string length $n]
return [expr $l != 0] return [expr {$l != 0}]
} }
# Give: REGISTER name - must be a global variable. # Give: REGISTER name - must be a global variable.
@ -52,7 +52,7 @@ proc show_mmr32_bits { NAMES VAL } {
echo -n " " echo -n " "
for { set y 7 } { $y >= 0 } { incr y -1 } { for { set y 7 } { $y >= 0 } { incr y -1 } {
echo -n [format " %d%*s | " [expr !!($VAL & (1 << ($x + $y)))] [expr {$w -1}] ""] echo -n [format " %d%*s | " [expr {!!($VAL & (1 << ($x + $y)))}] [expr {$w -1}] ""]
} }
echo "" echo ""
} }

4
tcl/target/am335x.cfg
View File

@ -103,10 +103,10 @@ proc disable_watchdog { } {
# Empty body to make sure this executes as fast as possible. # Empty body to make sure this executes as fast as possible.
# We don't want any delays here otherwise romcode might start # We don't want any delays here otherwise romcode might start
# executing and end up changing state of certain IPs. # executing and end up changing state of certain IPs.
while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2 mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
} }
} }
$_TARGETNAME configure -event reset-end { disable_watchdog } $_TARGETNAME configure -event reset-end { disable_watchdog }

14
tcl/target/am437x.cfg
View File

@ -512,10 +512,10 @@ proc disable_watchdog { } {
# Empty body to make sure this executes as fast as possible. # Empty body to make sure this executes as fast as possible.
# We don't want any delays here otherwise romcode might start # We don't want any delays here otherwise romcode might start
# executing and end up changing state of certain IPs. # executing and end up changing state of certain IPs.
while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2 mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { } while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
} }
} }
@ -725,13 +725,13 @@ proc emif_prcm_clk_enable { } {
proc vtp_enable { } { proc vtp_enable { } {
global VTP_CTRL_REG global VTP_CTRL_REG
set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x40 ] set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }]
mww $VTP_CTRL_REG $vtp mww $VTP_CTRL_REG $vtp
set vtp [ expr [ mrw $VTP_CTRL_REG ] & ~0x01 ] set vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }]
mww $VTP_CTRL_REG $vtp mww $VTP_CTRL_REG $vtp
set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x01 ] set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }]
mww $VTP_CTRL_REG $vtp mww $VTP_CTRL_REG $vtp
} }
@ -948,7 +948,7 @@ proc config_ddr3 { SDRAM_CONFIG } {
emif_prcm_clk_enable emif_prcm_clk_enable
vtp_enable vtp_enable
set dll [ expr [ mrw $CM_DLL_CTRL ] & ~0x01 ] set dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }]
mww $CM_DLL_CTRL $dll mww $CM_DLL_CTRL $dll
while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { } while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { }
@ -978,7 +978,7 @@ proc config_ddr3 { SDRAM_CONFIG } {
sleep 10 sleep 10
set tmp [ expr [ mrw $EXT_PHY_CTRL_36 ] | 0x0100 ] set tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }]
mww $EXT_PHY_CTRL_36 $tmp mww $EXT_PHY_CTRL_36 $tmp
mww $EXT_PHY_CTRL_36_SHDW $tmp mww $EXT_PHY_CTRL_36_SHDW $tmp

2
tcl/target/bluenrg-x.cfg
View File

@ -65,7 +65,7 @@ $_TARGETNAME configure -event resumed {
global WDOG_VALUE_SET global WDOG_VALUE_SET
set _JTAG_IDCODE [mrw 0x40000004] set _JTAG_IDCODE [mrw 0x40000004]
if {$_JTAG_IDCODE != 0x0201E041} { if {$_JTAG_IDCODE != 0x0201E041} {
if [expr $WDOG_VALUE_SET] { if {$WDOG_VALUE_SET} {
# Restore watchdog enable value after resume. Only Bluenrg-1/2 # Restore watchdog enable value after resume. Only Bluenrg-1/2
mww 0x40700008 $WDOG_VALUE mww 0x40700008 $WDOG_VALUE
set WDOG_VALUE_SET 0 set WDOG_VALUE_SET 0

6
tcl/target/c100config.tcl
View File

@ -26,14 +26,14 @@ proc configC100 {} {
dict set configC100 w_amba 1 dict set configC100 w_amba 1
dict set configC100 x_amba 1 dict set configC100 x_amba 1
# y = amba_clk * (w+1)*(x+1)*2/xtal_clk # y = amba_clk * (w+1)*(x+1)*2/xtal_clk
dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] dict set configC100 y_amba [expr {[dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
# Arm Clk 450MHz, must be a multiple of 25 MHz # Arm Clk 450MHz, must be a multiple of 25 MHz
dict set configC100 CFG_ARM_CLOCK 450000000 dict set configC100 CFG_ARM_CLOCK 450000000
dict set configC100 w_arm 0 dict set configC100 w_arm 0
dict set configC100 x_arm 1 dict set configC100 x_arm 1
# y = arm_clk * (w+1)*(x+1)*2/xtal_clk # y = arm_clk * (w+1)*(x+1)*2/xtal_clk
dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ] dict set configC100 y_arm [expr {[dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
} }
@ -362,7 +362,7 @@ proc putcUART0 {char} {
# convert the 'char' to digit # convert the 'char' to digit
set tmp [ scan $char %c ] set tmp [ scan $char %c ]
# /* wait for room in the tx FIFO on FFUART */ # /* wait for room in the tx FIFO on FFUART */
while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 } while {[expr {[mrw $UART0_LSR] & $LSR_TEMT}] == 0} { sleep 1 }
mww $UART0_THR $tmp mww $UART0_THR $tmp
if { $char == "\n" } { putcUART0 \r } if { $char == "\n" } { putcUART0 \r }
} }

22
tcl/target/c100helper.tcl
View File

@ -119,17 +119,17 @@ proc showAmbaClk {} {
echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]] echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1 mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
# see if the PLL is in bypass mode # see if the PLL is in bypass mode
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}]
echo [format "PLL bypass bit: %d" $bypass] echo [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} { if {$bypass == 1} {
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
} else { } else {
# nope, extract x,y,w and compute the PLL output freq. # nope, extract x,y,w and compute the PLL output freq.
set x [expr ($value(0) & 0x0001F0000) >> 16] set x [expr {($value(0) & 0x0001F0000) >> 16}]
echo [format "x: %d" $x] echo [format "x: %d" $x]
set y [expr ($value(0) & 0x00000007F)] set y [expr {($value(0) & 0x00000007F)}]
echo [format "y: %d" $y] echo [format "y: %d" $y]
set w [expr ($value(0) & 0x000000300) >> 8] set w [expr {($value(0) & 0x000000300) >> 8}]
echo [format "w: %d" $w] echo [format "w: %d" $w]
echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
} }
@ -177,7 +177,7 @@ proc setupAmbaClk {} {
mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
# wait for PLL to lock # wait for PLL to lock
echo "Waiting for Amba PLL to lock" echo "Waiting for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 } while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 }
# remove the internal PLL bypass # remove the internal PLL bypass
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX # remove PLL from BYPASS mode using MUX
@ -194,17 +194,17 @@ proc showArmClk {} {
echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]] echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1 mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
# see if the PLL is in bypass mode # see if the PLL is in bypass mode
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ] set bypass [expr {($value(0) & $PLL_CLK_BYPASS) >> 24}]
echo [format "PLL bypass bit: %d" $bypass] echo [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} { if {$bypass == 1} {
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]] echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
} else { } else {
# nope, extract x,y,w and compute the PLL output freq. # nope, extract x,y,w and compute the PLL output freq.
set x [expr ($value(0) & 0x0001F0000) >> 16] set x [expr {($value(0) & 0x0001F0000) >> 16}]
echo [format "x: %d" $x] echo [format "x: %d" $x]
set y [expr ($value(0) & 0x00000007F)] set y [expr {($value(0) & 0x00000007F)}]
echo [format "y: %d" $y] echo [format "y: %d" $y]
set w [expr ($value(0) & 0x000000300) >> 8] set w [expr {($value(0) & 0x000000300) >> 8}]
echo [format "w: %d" $w] echo [format "w: %d" $w]
echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]] echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
} }
@ -251,7 +251,7 @@ proc setupArmClk {} {
mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0 mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
# wait for PLL to lock # wait for PLL to lock
echo "Waiting for Amba PLL to lock" echo "Waiting for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 } while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 }
# remove the internal PLL bypass # remove the internal PLL bypass
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX # remove PLL from BYPASS mode using MUX
@ -442,7 +442,7 @@ proc initC100 {} {
# APB init # APB init
# // Setting APB Bus Wait states to 1, set post write # // Setting APB Bus Wait states to 1, set post write
# (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40; # (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
mww [expr $APB_ACCESS_WS_REG] 0x40 mww $APB_ACCESS_WS_REG 0x40
# AHB init # AHB init
# // enable all 6 masters for ARAM # // enable all 6 masters for ARAM
mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0 mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0

12
tcl/target/davinci.cfg
View File

@ -4,7 +4,7 @@
# davinci_pinmux: assigns PINMUX$reg <== $value # davinci_pinmux: assigns PINMUX$reg <== $value
proc davinci_pinmux {soc reg value} { proc davinci_pinmux {soc reg value} {
mww [expr [dict get $soc sysbase] + 4 * $reg] $value mww [expr {[dict get $soc sysbase] + 4 * $reg}] $value
} }
source [find mem_helper.tcl] source [find mem_helper.tcl]
@ -110,7 +110,7 @@ proc pll_v02_setup {pll_addr mult config} {
# write pllcmd.GO; poll pllstat.GO # write pllcmd.GO; poll pllstat.GO
mww [expr {$pll_addr + 0x0138}] 0x01 mww [expr {$pll_addr + 0x0138}] 0x01
set pllstat [expr {$pll_addr + 0x013c}] set pllstat [expr {$pll_addr + 0x013c}]
while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
} }
mww [expr {$pll_addr + 0x0138}] 0x00 mww [expr {$pll_addr + 0x0138}] 0x00
@ -272,11 +272,11 @@ proc pll_v03_setup {pll_addr mult config} {
# write pllcmd.GO; poll pllstat.GO # write pllcmd.GO; poll pllstat.GO
mww [expr {$pll_addr + 0x0138}] 0x01 mww [expr {$pll_addr + 0x0138}] 0x01
set pllstat [expr {$pll_addr + 0x013c}] set pllstat [expr {$pll_addr + 0x013c}]
while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 } while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
} }
mww [expr {$pll_addr + 0x0138}] 0x00 mww [expr {$pll_addr + 0x0138}] 0x00
set addr [dict get $config ctladdr] set addr [dict get $config ctladdr]
while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 } while {[expr {[mrw $addr] & 0x0e000000}] != 0x0e000000} { sleep 1 }
# 12 - set PLLEN (bit 0) ... leave bypass mode # 12 - set PLLEN (bit 0) ... leave bypass mode
set pll_ctrl [expr {$pll_ctrl | 0x0001}] set pll_ctrl [expr {$pll_ctrl | 0x0001}]
@ -306,13 +306,13 @@ proc psc_go {} {
set ptstat_addr [expr {$psc_addr + 0x0128}] set ptstat_addr [expr {$psc_addr + 0x0128}]
# just in case PTSTAT.go isn't clear # just in case PTSTAT.go isn't clear
while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
# write PTCMD.go ... ignoring any DSP power domain # write PTCMD.go ... ignoring any DSP power domain
mww [expr {$psc_addr + 0x0120}] 1 mww [expr {$psc_addr + 0x0120}] 1
# wait for PTSTAT.go to clear (again ignoring DSP power domain) # wait for PTSTAT.go to clear (again ignoring DSP power domain)
while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 } while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
} }
# #

4
tcl/target/hilscher_netx500.cfg
View File

@ -36,10 +36,10 @@ proc mread32 {addr} {
proc sdram_fix { } { proc sdram_fix { } {
set accesskey [mread32 0x00100070] set accesskey [mread32 0x00100070]
mww 0x00100070 [expr $accesskey] mww 0x00100070 $accesskey
mww 0x0010002c 0x00000001 mww 0x0010002c 0x00000001
if {[expr [mread32 0x0010002c] & 0x07] == 0x07} { if {[expr {[mread32 0x0010002c] & 0x07}] == 0x07} {
puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!" puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!"
} else { } else {
puts "SDRAM Fix succeeded!" puts "SDRAM Fix succeeded!"

4
tcl/target/icepick.cfg
View File

@ -54,8 +54,8 @@ proc icepick_c_disconnect {jrc} {
proc icepick_c_router {jrc rw block register payload} { proc icepick_c_router {jrc rw block register payload} {
set new_dr_value \ set new_dr_value \
[expr ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \ [expr { ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \
( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) ] ( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) } ]
# echo "\tNew router value:\t0x[format %x $new_dr_value]" # echo "\tNew router value:\t0x[format %x $new_dr_value]"

12
tcl/target/psoc4.cfg
View File

@ -78,18 +78,18 @@ proc psoc4_get_family_id {} {
if { $err } { if { $err } {
return 0 return 0
} }
if { [expr $romtable_pid(0) & 0xffffff00 ] if { [expr {$romtable_pid(0) & 0xffffff00 }]
|| [expr $romtable_pid(1) & 0xffffff00 ] || [expr {$romtable_pid(1) & 0xffffff00 }]
|| [expr $romtable_pid(2) & 0xffffff00 ] } { || [expr {$romtable_pid(2) & 0xffffff00 }] } {
echo "Unexpected data in ROMTABLE" echo "Unexpected data in ROMTABLE"
return 0 return 0
} }
set designer_id [expr (( $romtable_pid(1) & 0xf0 ) >> 4) | (( $romtable_pid(2) & 0xf ) << 4 ) ] set designer_id [expr {(( $romtable_pid(1) & 0xf0 ) >> 4) | (( $romtable_pid(2) & 0xf ) << 4 ) }]
if { $designer_id != 0xb4 } { if { $designer_id != 0xb4 } {
echo [format "ROMTABLE Designer ID 0x%02x is not Cypress" $designer_id] echo [format "ROMTABLE Designer ID 0x%02x is not Cypress" $designer_id]
return 0 return 0
} }
set family_id [expr ( $romtable_pid(0) & 0xff ) | (( $romtable_pid(1) & 0xf ) << 8 ) ] set family_id [expr {( $romtable_pid(0) & 0xff ) | (( $romtable_pid(1) & 0xf ) << 8 ) }]
return $family_id return $family_id
} }
@ -194,7 +194,7 @@ proc ocd_process_reset_inner { MODE } {
# Set registers to reset vector values # Set registers to reset vector values
mem2array value 32 0 2 mem2array value 32 0 2
reg pc [expr $value(1) & 0xfffffffe ] reg pc [expr {$value(1) & 0xfffffffe} ]
reg msp $value(0) reg msp $value(0)
if { $PSOC4_TEST_MODE_WORKAROUND } { if { $PSOC4_TEST_MODE_WORKAROUND } {

8
tcl/target/stellaris.cfg
View File

@ -83,7 +83,7 @@ proc reset_peripherals {family} {
mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0 mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
# RCC and RCC2 to their reset values # RCC and RCC2 to their reset values
mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))] mww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}]
mww $SYSCTL_RCC2 0x07806810 mww $SYSCTL_RCC2 0x07806810
mww $SYSCTL_RCC 0x078e3ad1 mww $SYSCTL_RCC 0x078e3ad1
@ -121,8 +121,8 @@ proc reset_peripherals {family} {
mww $SYSCTL_MISC 0xffffffff mww $SYSCTL_MISC 0xffffffff
# Wait for any pending flash operations to complete # Wait for any pending flash operations to complete
while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 } while {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 }
while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 } while {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 }
# Reset the flash controller registers # Reset the flash controller registers
mww $FLASH_FMA 0 mww $FLASH_FMA 0
@ -152,7 +152,7 @@ $_TARGETNAME configure -event reset-start {
if {$_DEVICECLASS != 0xff} { if {$_DEVICECLASS != 0xff} {
set device_class $_DEVICECLASS set device_class $_DEVICECLASS
} else { } else {
set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)] set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}]
} }
if {$device_class == 0 || $device_class == 1 || if {$device_class == 0 || $device_class == 1 ||

2
tcl/target/stm32mp15x.cfg
View File

@ -107,7 +107,7 @@ proc toggle_cpu0_dbg_claim0 {} {
proc detect_cpu1 {} { proc detect_cpu1 {} {
$::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1 $::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
set dual_core [expr $cpu1_prsr(0) & 1] set dual_core [expr {$cpu1_prsr(0) & 1}]
if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine} if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
} }

4
tcl/target/u8500.cfg
View File

@ -18,12 +18,12 @@ proc ocd_gdb_restart {target_id} {
global _TARGETNAME_1 global _TARGETNAME_1
global _SMP global _SMP
targets $_TARGETNAME_1 targets $_TARGETNAME_1
if { [expr ($_SMP == 1)] } { if { $_SMP == 1 } {
cortex_a smp off cortex_a smp off
} }
rst_run rst_run
halt halt
if { [expr ($_SMP == 1)]} { if { $_SMP == 1 } {
cortex_a smp on cortex_a smp on
} }
} }

4
tcl/tools/memtest.tcl
View File

@ -166,7 +166,7 @@ proc memTestDevice { baseAddress nBytes } {
return $pattern return $pattern
} }
set antiPattern [expr ~$pattern] set antiPattern [expr {~$pattern}]
memwrite32 [expr {$baseAddress + $offset}] $antiPattern memwrite32 [expr {$baseAddress + $offset}] $antiPattern
} }
@ -177,7 +177,7 @@ proc memTestDevice { baseAddress nBytes } {
set data [memread32 $addr] set data [memread32 $addr]
set dataHex [convertToHex $data] set dataHex [convertToHex $data]
set antiPatternHex [convertToHex $antiPattern] set antiPatternHex [convertToHex $antiPattern]
if {[expr $dataHex != $antiPatternHex]} { if {$dataHex != $antiPatternHex} {
echo "FAILED memTestDevice_antipattern: Address: [convertToHex $addr], antiPattern: $antiPatternHex, Returned: $dataHex, offset: $offset" echo "FAILED memTestDevice_antipattern: Address: [convertToHex $addr], antiPattern: $antiPatternHex, Returned: $dataHex, offset: $offset"
return $pattern return $pattern
} }