flash/stm32l4x: add support of STM32WL5x dual core
according the RM0453, the second core have a different Flash CR and SR registers for flash operations (called C2CR and C2SR). so we need to a different flash_regs than older L4 devices. @see stm32wl_cpu2_flash_regs the C2CR register don't contain LOCK and OPTLOCK bits, and this explain the addition of new register index called STM32_FLASH_CR_WLK_INDEX to look-up the CR with lock, to be used in locking/unlocking the flash. note: DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1, to solve this read the UID64 (IEEE 64-bit unique device ID register) Change-Id: Ifb6e291bf97f814f0b9987b2c40f3037959f7af4 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6050 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This commit is contained in:
Tarek BOCHKATI
Oleksij Rempel
parent
64fbd60787
commit
6c1e1a212a
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@ -27,7 +27,7 @@
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#include <helper/align.h>
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#include <helper/binarybuffer.h>
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#include <target/algorithm.h>
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#include <target/armv7m.h>
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#include <target/cortex_m.h>
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#include "bits.h"
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#include "stm32l4x.h"
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@ -80,6 +80,9 @@
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*
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* RM0461 (STM32WLEx)
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* http://www.st.com/resource/en/reference_manual/dm00530369.pdf
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*
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* RM0453 (STM32WL5x)
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* http://www.st.com/resource/en/reference_manual/dm00451556.pdf
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*/
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/* STM32G0xxx series for reference.
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@ -139,6 +142,9 @@ enum stm32l4_flash_reg_index {
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STM32_FLASH_OPTKEYR_INDEX,
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STM32_FLASH_SR_INDEX,
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STM32_FLASH_CR_INDEX,
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/* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
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* so it uses the C2CR for flash operations and CR for checking locks and locking */
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STM32_FLASH_CR_WLK_INDEX, /* FLASH_CR_WITH_LOCK */
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STM32_FLASH_OPTR_INDEX,
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STM32_FLASH_WRP1AR_INDEX,
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STM32_FLASH_WRP1BR_INDEX,
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@ -167,6 +173,18 @@ static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
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[STM32_FLASH_WRP2BR_INDEX] = 0x050,
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};
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static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
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[STM32_FLASH_ACR_INDEX] = 0x000,
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[STM32_FLASH_KEYR_INDEX] = 0x008,
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[STM32_FLASH_OPTKEYR_INDEX] = 0x010,
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[STM32_FLASH_SR_INDEX] = 0x060,
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[STM32_FLASH_CR_INDEX] = 0x064,
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[STM32_FLASH_CR_WLK_INDEX] = 0x014,
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[STM32_FLASH_OPTR_INDEX] = 0x020,
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[STM32_FLASH_WRP1AR_INDEX] = 0x02C,
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[STM32_FLASH_WRP1BR_INDEX] = 0x030,
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};
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static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
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[STM32_FLASH_ACR_INDEX] = 0x000,
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[STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
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@ -514,7 +532,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
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.id = 0x497,
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.revs = stm32_497_revs,
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.num_revs = ARRAY_SIZE(stm32_497_revs),
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.device_str = "STM32WLEx",
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.device_str = "STM32WLEx/WL5x",
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.max_flash_size_kb = 256,
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.flags = F_NONE,
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.flash_regs_base = 0x58004000,
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@ -789,14 +807,22 @@ static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
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return ERROR_OK;
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}
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static inline int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
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{
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struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
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return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
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STM32_FLASH_CR_WLK_INDEX : STM32_FLASH_CR_INDEX;
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}
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static int stm32l4_unlock_reg(struct flash_bank *bank)
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{
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const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
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uint32_t ctrl;
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/* first check if not already unlocked
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* otherwise writing on STM32_FLASH_KEYR will fail
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*/
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int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
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int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
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if (retval != ERROR_OK)
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return retval;
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@ -812,7 +838,7 @@ static int stm32l4_unlock_reg(struct flash_bank *bank)
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if (retval != ERROR_OK)
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return retval;
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retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
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retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
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if (retval != ERROR_OK)
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return retval;
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@ -826,9 +852,10 @@ static int stm32l4_unlock_reg(struct flash_bank *bank)
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static int stm32l4_unlock_option_reg(struct flash_bank *bank)
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{
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const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
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uint32_t ctrl;
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int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
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int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
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if (retval != ERROR_OK)
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return retval;
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@ -844,7 +871,7 @@ static int stm32l4_unlock_option_reg(struct flash_bank *bank)
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if (retval != ERROR_OK)
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return retval;
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retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
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retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
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if (retval != ERROR_OK)
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return retval;
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@ -884,7 +911,8 @@ static int stm32l4_perform_obl_launch(struct flash_bank *bank)
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stm32l4_info->probed = false;
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err_lock:
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retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK);
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retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
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FLASH_LOCK | FLASH_OPTLOCK);
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if (retval != ERROR_OK)
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return retval;
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@ -930,7 +958,8 @@ static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
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retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
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err_lock:
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retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK);
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retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
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FLASH_LOCK | FLASH_OPTLOCK);
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stm32l4_info->flash_regs = saved_flash_regs;
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if (retval != ERROR_OK)
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@ -1124,7 +1153,7 @@ static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
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}
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err_lock:
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retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
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retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
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if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
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/* restore all FLASH pages as non-secure */
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@ -1511,7 +1540,7 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
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err_lock:
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retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
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retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
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if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
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/* restore all FLASH pages as non-secure */
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@ -1540,6 +1569,30 @@ static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
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return ERROR_OK;
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}
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/* Workaround for STM32WL5x devices:
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* DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
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* to solve this read the UID64 (IEEE 64-bit unique device ID register) */
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struct cortex_m_common *cortex_m = target_to_cm(bank->target);
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if (cortex_m->core_info->partno == CORTEX_M0P_PARTNO && cortex_m->armv7m.debug_ap->ap_num == 1) {
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uint32_t uid64_ids;
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/* UID64 is contains
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* - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
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* - Bits 31:08 : STID (company ID) = 0x0080E1
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* - Bits 07:00 : DEVID (device ID) = 0x15
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*
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* read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
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*/
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retval = target_read_u32(bank->target, UID64_IDS, &uid64_ids);
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if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
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/* force the DEV_ID to 0x497 and the REV_ID to unknown */
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*id = 0x00000497;
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return ERROR_OK;
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}
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}
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LOG_ERROR("can't get the device id");
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return (retval == ERROR_OK) ? ERROR_FAIL : retval;
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}
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@ -1570,6 +1623,7 @@ static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
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static int stm32l4_probe(struct flash_bank *bank)
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{
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struct target *target = bank->target;
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struct armv7m_common *armv7m = target_to_armv7m(target);
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struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
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const struct stm32l4_part_info *part_info;
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uint16_t flash_size_kb = 0xffff;
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@ -1722,7 +1776,6 @@ static int stm32l4_probe(struct flash_bank *bank)
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case 0x466: /* STM32G03/G04xx */
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case 0x468: /* STM32G43/G44xx */
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case 0x479: /* STM32G49/G4Axx */
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case 0x497: /* STM32WLEx */
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/* single bank flash */
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page_size_kb = 2;
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num_pages = flash_size_kb / page_size_kb;
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@ -1806,6 +1859,14 @@ static int stm32l4_probe(struct flash_bank *bank)
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num_pages = flash_size_kb / page_size_kb;
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stm32l4_info->bank1_sectors = num_pages;
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break;
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case 0x497: /* STM32WLEx/WL5x */
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/* single bank flash */
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page_size_kb = 2;
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num_pages = flash_size_kb / page_size_kb;
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stm32l4_info->bank1_sectors = num_pages;
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if (armv7m->debug_ap->ap_num == 1)
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stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
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break;
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default:
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LOG_ERROR("unsupported device");
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return ERROR_FAIL;
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@ -1953,7 +2014,7 @@ static int stm32l4_mass_erase(struct flash_bank *bank)
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retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
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err_lock:
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retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
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retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
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if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
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/* restore all FLASH pages as non-secure */
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@ -83,6 +83,9 @@
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#define DBGMCU_IDCODE_G0 0x40015800
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#define DBGMCU_IDCODE_L4_G4 0xE0042000
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#define DBGMCU_IDCODE_L5 0xE0044000
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#define UID64_DEVNUM 0x1FFF7580
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#define UID64_IDS 0x1FFF7584
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#define UID64_IDS_STM32WL 0x0080E115
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#define STM32_FLASH_BANK_BASE 0x08000000
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#define STM32_FLASH_S_BANK_BASE 0x0C000000
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@ -12,16 +12,47 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME stm32wlx
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}
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set _ENDIAN little
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if { [info exists DUAL_CORE] } {
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set $_CHIPNAME.DUAL_CORE $DUAL_CORE
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unset DUAL_CORE
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} else {
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set $_CHIPNAME.DUAL_CORE 0
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}
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if { [info exists WKUP_CM0P] } {
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set $_CHIPNAME.WKUP_CM0P $WKUP_CM0P
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unset WKUP_CM0P
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} else {
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set $_CHIPNAME.WKUP_CM0P 0
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}
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# Issue a warning when hla is used, and fallback to single core configuration
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if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
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echo "Warning : hla does not support multicore debugging"
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set $_CHIPNAME.DUAL_CORE 0
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set $_CHIPNAME.WKUP_CM0P 0
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}
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# setup the Work-area start address and size
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# Work-area is a space in RAM used for flash programming
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# By default use 20kB
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# Memory map for known devices:
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# STM32WL x5JC x5JB x5J8
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# FLASH 256 128 64
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# SRAM1 32 16 0
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# SRAM2 32 32 20
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# By default use 8kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x5000
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set _WORKAREASIZE 0x2000
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}
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# Use SRAM2 as work area (some devices do not have SRAM1):
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set WORKAREASTART_CM4 0x20008000
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set WORKAREASTART_CM0P [expr {$WORKAREASTART_CM4 + $_WORKAREASIZE}]
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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@ -41,13 +72,104 @@ if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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target create $_CHIPNAME.cpu0 cortex_m -endian little -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM4 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.flash.cpu0 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu0
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flash bank $_CHIPNAME.otp.cpu0 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu0
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
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}
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$_CHIPNAME.cpu0 configure -event reset-init {
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# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
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# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
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# 2 WS compliant with VOS=Range1 and 24 MHz.
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mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTEN | 2(Latency)
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mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
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# Boost JTAG frequency
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adapter speed 4000
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}
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$_CHIPNAME.cpu0 configure -event reset-start {
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# Reset clock is MSI (4 MHz)
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adapter speed 500
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}
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$_CHIPNAME.cpu0 configure -event examine-end {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE004203C 0x00001800 0
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set _CHIPNAME [stm32wlx_get_chipname]
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global $_CHIPNAME.WKUP_CM0P
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if {[set $_CHIPNAME.WKUP_CM0P]} {
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stm32wlx_wkup_cm0p
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}
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}
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$_CHIPNAME.cpu0 configure -event trace-config {
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# nothing to do
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}
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if {[set $_CHIPNAME.DUAL_CORE]} {
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target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
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$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM0P -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1
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flash bank $_CHIPNAME.otp.cpu1 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu1
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
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}
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proc stm32wlx_wkup_cm0p {} {
|
||||
set _CHIPNAME [stm32wlx_get_chipname]
|
||||
|
||||
# enable CPU2 boot after reset and after wakeup from Stop or Standby mode
|
||||
# PWR_CR4 |= C2BOOT
|
||||
stm32wlx_mmw $_CHIPNAME.cpu0 0x5800040C 0x00008000 0
|
||||
}
|
||||
}
|
||||
|
||||
# get _CHIPNAME from current target
|
||||
proc stm32wlx_get_chipname {} {
|
||||
set t [target current]
|
||||
set sep [string last "." $t]
|
||||
if {$sep == -1} {
|
||||
return $t
|
||||
}
|
||||
return [string range $t 0 [expr $sep - 1]]
|
||||
}
|
||||
|
||||
# like mrw, but with target selection
|
||||
proc stm32wlx_mrw {used_target reg} {
|
||||
set value ""
|
||||
$used_target mem2array value 32 $reg 1
|
||||
return $value(0)
|
||||
}
|
||||
|
||||
# like mmw, but with target selection
|
||||
proc stm32wlx_mmw {used_target reg setbits clearbits} {
|
||||
set old [stm32wlx_mrw $used_target $reg]
|
||||
set new [expr {($old & ~$clearbits) | $setbits}]
|
||||
$used_target mww $reg $new
|
||||
}
|
||||
|
||||
# Make sure that cpu0 is selected
|
||||
targets $_CHIPNAME.cpu0
|
||||
|
||||
# Common knowledges tells JTAG speed should be <= F_CPU/6.
|
||||
# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
|
||||
|
|
@ -63,38 +185,3 @@ if {[using_jtag]} {
|
|||
}
|
||||
|
||||
reset_config srst_nogate
|
||||
|
||||
if {![using_hla]} {
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
|
||||
# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
|
||||
# 2 WS compliant with VOS=Range1 and 24 MHz.
|
||||
mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTEN | 2(Latency)
|
||||
mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
|
||||
# Boost JTAG frequency
|
||||
adapter speed 4000
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-start {
|
||||
# Reset clock is MSI (4 MHz)
|
||||
adapter speed 500
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event examine-end {
|
||||
# Enable debug during low power modes (uses more power)
|
||||
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
|
||||
mmw 0xE0042004 0x00000007 0
|
||||
|
||||
# Stop watchdog counters during halt
|
||||
# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
|
||||
mmw 0xE004203C 0x00001800 0
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event trace-config {
|
||||
# nothing to do
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue