flash/nor/stm32h7x: use of wait queue flag instead of the busy flag
Based on RM0433.rev5 > Section 3.3.9 : Flash program operations: QW1/2: this bit indicates that a write, erase or option byte change operation is pending in the write queue or command queue buffer. It remains high until the write operation is complete. It supersedes the BSY1/2 status bit. On this basis, stm32x_wait_status_busy is renamed accordingly to be 'stm32x_wait_flash_op_queue' Note : In this commit there is a fix of SR_ERROR_MASK value in flash loader algo Note : This modification is mandatory for revision X, and backward compatible with old revisions Change-Id: I59d2973317d76b01fbb0fb5e4a472a47d0a7a5b5 Signed-off-by: Laurent LEMELE <laurent.lemele@st.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/4883 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Tarek BOCHKATI
Tomas Vanek
parent
f78a7046a9
commit
7ee618692f
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@ -48,8 +48,8 @@
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#define STM32_FLASH_CR_OFFSET 0x0C /* offset of CR register in FLASH struct */
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#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
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#define STM32_CR_PROG 0x00000032 /* PSIZE64 | PG */
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#define STM32_SR_BUSY_MASK 0x00000001 /* BSY */
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#define STM32_SR_ERROR_MASK 0x03ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
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#define STM32_SR_QW_MASK 0x00000004 /* QW */
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#define STM32_SR_ERROR_MASK 0x07ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
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| INCERR | STRBERR | PGSERR | WRPERR */
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.thumb_func
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@ -73,6 +73,7 @@ wait_fifo:
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mov r7, #8 /* program by 8 words = 32 bytes */
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write_flash:
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dsb
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ldr r6, [r5], #0x04 /* read one word from src, increment ptr */
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str r6, [r2], #0x04 /* write one word to dst, increment ptr */
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dsb
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@ -84,7 +85,7 @@ write_flash:
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busy:
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ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
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tst r6, #STM32_SR_BUSY_MASK
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tst r6, #STM32_SR_QW_MASK
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bne busy /* operation in progress, wait ... */
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ldr r7, =STM32_SR_ERROR_MASK
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@ -1,7 +1,7 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x45,0x68,0x06,0x68,0x26,0xb3,0x76,0x1b,0x42,0xbf,0x76,0x18,0x36,0x1a,0x08,0x3e,
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0x20,0x2e,0xf6,0xd3,0x4f,0xf0,0x32,0x06,0xe6,0x60,0x4f,0xf0,0x08,0x07,0x55,0xf8,
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0x04,0x6b,0x42,0xf8,0x04,0x6b,0xbf,0xf3,0x4f,0x8f,0x8d,0x42,0x28,0xbf,0x00,0xf1,
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0x08,0x05,0x01,0x3f,0xf3,0xd1,0x26,0x69,0x16,0xf0,0x01,0x0f,0xfb,0xd1,0x05,0x4f,
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0x3e,0x42,0x03,0xd1,0x45,0x60,0x01,0x3b,0xdb,0xd1,0x01,0xe0,0x00,0x27,0x47,0x60,
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0x30,0x46,0x00,0xbe,0x00,0x00,0xee,0x03,
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0x45,0x68,0x06,0x68,0x36,0xb3,0x76,0x1b,0x42,0xbf,0x76,0x18,0x36,0x1a,0x08,0x3e,
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0x20,0x2e,0xf6,0xd3,0x4f,0xf0,0x32,0x06,0xe6,0x60,0x4f,0xf0,0x08,0x07,0xbf,0xf3,
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0x4f,0x8f,0x55,0xf8,0x04,0x6b,0x42,0xf8,0x04,0x6b,0xbf,0xf3,0x4f,0x8f,0x8d,0x42,
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0x28,0xbf,0x00,0xf1,0x08,0x05,0x01,0x3f,0xf1,0xd1,0x26,0x69,0x16,0xf0,0x04,0x0f,
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0xfb,0xd1,0x05,0x4f,0x3e,0x42,0x03,0xd1,0x45,0x60,0x01,0x3b,0xd9,0xd1,0x01,0xe0,
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0x00,0x27,0x47,0x60,0x30,0x46,0x00,0xbe,0x00,0x00,0xee,0x07,
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@ -61,6 +61,7 @@
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/* FLASH_SR register bits */
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#define FLASH_BSY (1 << 0) /* Operation in progress */
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#define FLASH_QW (1 << 2) /* Operation queue in progress */
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#define FLASH_WRPERR (1 << 17) /* Write protection error */
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#define FLASH_PGSERR (1 << 18) /* Programming sequence error */
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#define FLASH_STRBERR (1 << 19) /* Strobe error */
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@ -132,7 +133,7 @@ struct stm32h7x_flash_bank {
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};
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static const struct stm32h7x_rev stm32_450_revs[] = {
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{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" },
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{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" },
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};
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static const struct stm32h7x_part_info stm32h7x_parts[] = {
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@ -184,33 +185,33 @@ static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *sta
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return target_read_u32(target, stm32x_get_flash_reg(bank, FLASH_SR), status);
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}
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static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
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static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
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{
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struct target *target = bank->target;
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struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
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uint32_t status;
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int retval;
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/* wait for busy to clear */
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/* wait for flash operations completion */
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for (;;) {
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retval = stm32x_get_flash_status(bank, &status);
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if (retval != ERROR_OK) {
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LOG_INFO("wait_status_busy, target_read_u32 : error : remote address 0x%x", stm32x_info->flash_base);
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LOG_INFO("wait_flash_op_queue, target_read_u32 : error : remote address 0x%x", stm32x_info->flash_base);
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return retval;
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}
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if ((status & FLASH_BSY) == 0)
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if ((status & FLASH_QW) == 0)
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break;
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if (timeout-- <= 0) {
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LOG_INFO("wait_status_busy, time out expired, status: 0x%" PRIx32 "", status);
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LOG_INFO("wait_flash_op_queue, time out expired, status: 0x%" PRIx32 "", status);
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return ERROR_FAIL;
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}
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alive_sleep(1);
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}
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if (status & FLASH_WRPERR) {
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LOG_INFO("wait_status_busy, WRPERR : error : remote address 0x%x", stm32x_info->flash_base);
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LOG_INFO("wait_flash_op_queue, WRPERR : error : remote address 0x%x", stm32x_info->flash_base);
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retval = ERROR_FAIL;
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}
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@ -393,14 +394,14 @@ static int stm32x_write_options(struct flash_bank *bank)
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uint32_t status;
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retval = target_read_u32(target, FLASH_REG_BASE_B0 + FLASH_SR, &status);
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if (retval != ERROR_OK) {
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LOG_INFO("stm32x_write_options: wait_status_busy : error");
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LOG_INFO("stm32x_write_options: wait_flash_op_queue : error");
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return retval;
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}
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if ((status & FLASH_BSY) == 0)
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if ((status & FLASH_QW) == 0)
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break;
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if (timeout-- <= 0) {
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LOG_INFO("wait_status_busy, time out expired, status: 0x%" PRIx32 "", status);
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LOG_INFO("wait_flash_op_queue, time out expired, status: 0x%" PRIx32 "", status);
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return ERROR_FAIL;
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}
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alive_sleep(1);
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@ -459,12 +460,12 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
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/*
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Sector Erase
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To erase a sector, follow the procedure below:
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1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
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1. Check that no Flash memory operation is ongoing by checking the QW bit in the
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FLASH_SR register
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2. Set the SER bit and select the sector
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you wish to erase (SNB) in the FLASH_CR register
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3. Set the STRT bit in the FLASH_CR register
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4. Wait for the BSY bit to be cleared
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4. Wait for flash operations completion
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*/
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for (int i = first; i <= last; i++) {
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LOG_DEBUG("erase sector %d", i);
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@ -480,7 +481,7 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
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LOG_ERROR("Error erase sector %d", i);
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return retval;
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}
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retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
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retval = stm32x_wait_flash_op_queue(bank, FLASH_ERASE_TIMEOUT);
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if (retval != ERROR_OK) {
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LOG_ERROR("erase time-out or operation error sector %d", i);
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@ -687,11 +688,11 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
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/*
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Standard programming
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The Flash memory programming sequence is as follows:
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1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
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1. Check that no main Flash memory operation is ongoing by checking the QW bit in the
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FLASH_SR register.
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2. Set the PG bit in the FLASH_CR register
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3. 8 x Word access (or Force Write FW)
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4. Wait for the BSY bit to be cleared
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4. Wait for flash operations completion
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*/
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while (blocks_remaining > 0) {
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retval = target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CR), FLASH_PG | FLASH_PSIZE_64);
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@ -702,7 +703,7 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
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if (retval != ERROR_OK)
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goto flash_lock;
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retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
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retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
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if (retval != ERROR_OK)
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goto flash_lock;
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@ -725,7 +726,7 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
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if (retval != ERROR_OK)
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goto flash_lock;
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retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
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retval = stm32x_wait_flash_op_queue(bank, FLASH_WRITE_TIMEOUT);
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if (retval != ERROR_OK)
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goto flash_lock;
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}
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@ -1038,7 +1039,7 @@ static int stm32x_mass_erase(struct flash_bank *bank)
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if (retval != ERROR_OK)
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return retval;
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retval = stm32x_wait_status_busy(bank, 30000);
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retval = stm32x_wait_flash_op_queue(bank, 30000);
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if (retval != ERROR_OK)
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return retval;
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