flash: add stm32f2x async flash loader
This enable the stm32f2x flash driver to use the asynchronous algorithm support. Speed increase is as follows: before - wrote 1048576 bytes from file stm32f4x.bin in 30.453804s (33.625 KiB/s) after - wrote 1048576 bytes from file stm32f4x.bin in 23.679497s (43.244 KiB/s) This also fixes a bug that was in the old flash loader. The old loader waited while bit16 of the status reg was 0, the new loader waits until this bit is 0 as stated in the flash spec. Bizarrely this bug did not effect programming on any tested parts. Change-Id: I3efc94d42cbe81283673a8f4203700638080af6e Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/460 Tested-by: jenkins
This commit is contained in:
Spencer Oliver
Andreas Fritiofson
parent
90cee35696
commit
94db77a0e6
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@ -21,43 +21,60 @@
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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// Build : arm-eabi-gcc -c stm32f2xxx.S
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.text
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.syntax unified
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.cpu cortex-m3
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.thumb
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.thumb_func
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.global write
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/*
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r0 - source address
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r1 - target address
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r2 - count (halfword-16bit)
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r3 - result out
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r4 - flash base
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*/
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* Params :
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* r0 = workarea start, status (out)
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* r1 = workarea end
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* r2 = target address
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* r3 = count (16bit words)
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* r4 = flash base
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*
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* Clobbered:
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* r6 - temp
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* r7 - rp
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* r8 - wp, tmp
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*/
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#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
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#define STM32_FLASH_SR_OFFSET 0x0c /* offset of CR register in FLASH struct */
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#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register in FLASH struct */
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write:
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wait_fifo:
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ldr r8, [r0, #0] /* read wp */
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cmp r8, #0 /* abort if wp == 0 */
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beq exit
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ldr r7, [r0, #4] /* read rp */
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cmp r7, r8 /* wait until rp != wp */
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beq wait_fifo
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write_half_word:
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ldr r3, STM32_PROG16
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str r3, [r4, #STM32_FLASH_CR_OFFSET]
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ldrh r3, [r0], #0x02 /* read one half-word from src, increment ptr */
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strh r3, [r1], #0x02 /* write one half-word from src, increment ptr */
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ldr r6, STM32_PROG16
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str r6, [r4, #STM32_FLASH_CR_OFFSET]
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ldrh r6, [r7], #0x02 /* read one half-word from src, increment ptr */
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strh r6, [r2], #0x02 /* write one half-word from src, increment ptr */
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busy:
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ldr r3, [r4, #STM32_FLASH_SR_OFFSET]
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tst r3, #0x10000 /* BSY (bit0) == 1 => operation in progress */
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beq busy /* wait more... */
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tst r3, #0xf0 /* PGSERR | PGPERR | PGAERR | WRPERR */
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bne exit /* fail... */
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subs r2, r2, #0x01 /* decrement counter */
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bne write_half_word /* write next half-word if anything left */
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ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
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tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
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bne busy /* wait more... */
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tst r6, #0xf0 /* PGSERR | PGPERR | PGAERR | WRPERR */
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bne error /* fail... */
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cmp r7, r1 /* wrap rp at end of buffer */
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it cs
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addcs r7, r0, #8 /* skip loader args */
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str r7, [r0, #4] /* store rp */
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subs r3, r3, #1 /* decrement halfword count */
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cbz r3, exit /* loop if not done */
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b wait_fifo
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error:
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movs r1, #0
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str r1, [r0, #4] /* set rp = 0 on error */
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exit:
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mov r0, r6 /* return status in r0 */
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bkpt #0x00
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STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/
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STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/
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@ -327,35 +327,44 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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/* see contrib/loaders/flash/stm32f2x.S for src */
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static const uint16_t stm32x_flash_write_code_16[] = {
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/* 00000000 <write>: */
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0x4b07, /* ldr r3, [pc, #28] (20 <STM32_PROG16>) */
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0x6123, /* str r3, [r4, #16] */
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0xf830, 0x3b02, /* ldrh.w r3, [r0], #2 */
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0xf821, 0x3b02, /* strh.w r3, [r1], #2 */
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static const uint8_t stm32x_flash_write_code[] = {
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/* wait_fifo: */
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0xD0, 0xF8, 0x00, 0x80, /* ldr r8, [r0, #0] */
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0xB8, 0xF1, 0x00, 0x0F, /* cmp r8, #0 */
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0x1A, 0xD0, /* beq exit */
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0x47, 0x68, /* ldr r7, [r0, #4] */
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0x47, 0x45, /* cmp r7, r8 */
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0xF7, 0xD0, /* beq wait_fifo */
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/* 0000000c <busy>: */
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0x68e3, /* ldr r3, [r4, #12] */
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0xf413, 0x3f80, /* tst.w r3, #65536 ; 0x10000 */
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0xd0fb, /* beq.n c <busy> */
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0xf013, 0x0ff0, /* tst.w r3, #240 ; 0xf0 */
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0xd101, /* bne.n 1e <exit> */
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0x3a01, /* subs r2, #1 */
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0xd1f0, /* bne.n 0 <write> */
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/* 0000001e <exit>: */
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0xbe00, /* bkpt 0x0000 */
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0xDF, 0xF8, 0x30, 0x60, /* ldr r6, STM32_PROG16 */
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0x26, 0x61, /* str r6, [r4, #STM32_FLASH_CR_OFFSET] */
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0x37, 0xF8, 0x02, 0x6B, /* ldrh r6, [r7], #0x02 */
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0x22, 0xF8, 0x02, 0x6B, /* strh r6, [r2], #0x02 */
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/* busy: */
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0xE6, 0x68, /* ldr r6, [r4, #STM32_FLASH_SR_OFFSET] */
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0x16, 0xF4, 0x80, 0x3F, /* tst r6, #0x10000 */
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0xFB, 0xD1, /* bne busy */
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0x16, 0xF0, 0xF0, 0x0F, /* tst r6, #0xf0 */
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0x07, 0xD1, /* bne error */
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/* 00000020 <STM32_PROG16>: */
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0x0101, 0x0000, /* .word 0x00000101 */
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0x8F, 0x42, /* cmp r7, r1 */
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0x28, 0xBF, /* it cs */
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0x00, 0xF1, 0x08, 0x07, /* addcs r7, r0, #8 */
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0x47, 0x60, /* str r7, [r0, #4] */
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0x01, 0x3B, /* subs r3, r3, #1 */
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0x13, 0xB1, /* cbz r3, exit */
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0xE1, 0xE7, /* b wait_fifo */
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/* error: */
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0x00, 0x21, /* movs r1, #0 */
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0x41, 0x60, /* str r1, [r0, #4] */
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/* exit: */
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0x30, 0x46, /* mov r0, r6 */
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0x00, 0xBE, /* bkpt #0x00 */
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/* <STM32_PROG16>: */
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0x01, 0x01, 0x00, 0x00, /* .word 0x00000101 */
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};
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/* Flip endian */
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uint8_t stm32x_flash_write_code[sizeof(stm32x_flash_write_code_16)*2];
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for (unsigned i = 0; i < sizeof(stm32x_flash_write_code_16) / 2; i++) {
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stm32x_flash_write_code[i*2 + 0] = stm32x_flash_write_code_16[i] & 0xff;
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stm32x_flash_write_code[i*2 + 1] = (stm32x_flash_write_code_16[i] >> 8) & 0xff;
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}
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if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
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&stm32x_info->write_algorithm) != ERROR_OK) {
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LOG_WARNING("no working area available, can't do block memory writes");
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@ -385,38 +394,29 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
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armv7m_info.core_mode = ARMV7M_MODE_ANY;
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init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
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init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
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init_reg_param(®_params[3], "r3", 32, PARAM_IN_OUT);
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init_reg_param(®_params[4], "r4", 32, PARAM_OUT);
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init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
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init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
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init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (halfword-16bit) */
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init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash base */
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while (count > 0) {
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uint32_t thisrun_count = (count > (buffer_size / 2)) ?
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(buffer_size / 2) : count;
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buf_set_u32(reg_params[0].value, 0, 32, source->address);
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buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
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buf_set_u32(reg_params[2].value, 0, 32, address);
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buf_set_u32(reg_params[3].value, 0, 32, count);
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buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
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retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer);
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if (retval != ERROR_OK)
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break;
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retval = target_run_flash_async_algorithm(target, buffer, count, 2,
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0, NULL,
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5, reg_params,
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source->address, source->size,
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stm32x_info->write_algorithm->address, 0,
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&armv7m_info);
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buf_set_u32(reg_params[0].value, 0, 32, source->address);
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buf_set_u32(reg_params[1].value, 0, 32, address);
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buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
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/* R3 is a return value only */
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buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
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if (retval == ERROR_FLASH_OPERATION_FAILED) {
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LOG_ERROR("error executing stm32x flash write algorithm");
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retval = target_run_algorithm(target, 0, NULL,
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sizeof(reg_params) / sizeof(*reg_params),
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reg_params,
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stm32x_info->write_algorithm->address,
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0,
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10000, &armv7m_info);
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if (retval != ERROR_OK) {
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LOG_ERROR("error executing stm32x flash write algorithm");
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break;
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}
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uint32_t error = buf_get_u32(reg_params[3].value, 0, 32) & FLASH_ERROR;
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uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
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if (error & FLASH_WRPERR)
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LOG_ERROR("flash memory write protected");
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@ -426,12 +426,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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/* Clear but report errors */
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target_write_u32(target, STM32_FLASH_SR, error);
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retval = ERROR_FAIL;
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break;
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}
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buffer += thisrun_count * 2;
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address += thisrun_count * 2;
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count -= thisrun_count;
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}
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target_free_working_area(target, source);
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