Allow transports to override the selected target (hla configs unification)

This should allow to share common configs for both regular access and
high-level adapters.

Use the newly-added functionality in stlink and icdi drivers, amend
the configs accordingly.

Runtime-tested with a TI tm4c123g board.

Change-Id: Ibb88266a4ca25f06f6c073e916c963f017447bad
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
[gus@projectgus.com: context-specific deprecation warnings]
Signed-off-by: Angus Gratton <gus@projectgus.com>
[andrew.smirnov@gmail.com: additional nrf51.cfg mods]
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Tested-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Reviewed-on: http://openocd.zylin.com/1664
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit is contained in:
Paul Fertser 2013-09-28 14:23:15 +04:00 committed by Andreas Fritiofson
parent f701c0cbeb
commit c7384117c6
67 changed files with 489 additions and 596 deletions

View File

@ -1570,6 +1570,12 @@ static int stlink_usb_write_mem(void *handle, uint32_t addr, uint32_t size,
return retval;
}
/** */
static int stlink_usb_override_target(const char *targetname)
{
return !strcmp(targetname, "cortex_m");
}
/** */
static int stlink_usb_close(void *fd)
{
@ -1798,5 +1804,7 @@ struct hl_layout_api_s stlink_usb_layout_api = {
/** */
.write_mem = stlink_usb_write_mem,
/** */
.write_debug_reg = stlink_usb_write_debug_reg
.write_debug_reg = stlink_usb_write_debug_reg,
/** */
.override_target = stlink_usb_override_target,
};

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@ -645,6 +645,11 @@ static int icdi_usb_write_mem(void *handle, uint32_t addr, uint32_t size,
return retval;
}
static int icdi_usb_override_target(const char *targetname)
{
return !strcmp(targetname, "cortex_m");
}
static int icdi_usb_close(void *handle)
{
struct icdi_usb_handle_s *h = handle;
@ -770,5 +775,6 @@ struct hl_layout_api_s icdi_usb_layout_api = {
.write_reg = icdi_usb_write_reg,
.read_mem = icdi_usb_read_mem,
.write_mem = icdi_usb_write_mem,
.write_debug_reg = icdi_usb_write_debug_reg
.write_debug_reg = icdi_usb_write_debug_reg,
.override_target = icdi_usb_override_target,
};

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@ -145,6 +145,35 @@ int hl_interface_init_reset(void)
return ERROR_OK;
}
static int dummy_khz(int khz, int *jtag_speed)
{
*jtag_speed = khz;
return ERROR_OK;
}
static int dummy_speed_div(int speed, int *khz)
{
*khz = speed;
return ERROR_OK;
}
static int dummy_speed(int speed)
{
return ERROR_OK;
}
int hl_interface_override_target(const char **targetname)
{
if (hl_if.layout->api->override_target) {
if (hl_if.layout->api->override_target(*targetname)) {
*targetname = "hla_target";
return ERROR_OK;
} else
return ERROR_FAIL;
}
return ERROR_FAIL;
}
COMMAND_HANDLER(hl_interface_handle_device_desc_command)
{
LOG_DEBUG("hl_interface_handle_device_desc_command");
@ -286,4 +315,7 @@ struct jtag_interface hl_interface = {
.init = hl_interface_init,
.quit = hl_interface_quit,
.execute_queue = hl_interface_execute_queue,
.speed = &dummy_speed,
.khz = &dummy_khz,
.speed_div = &dummy_speed_div,
};

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@ -67,5 +67,6 @@ int hl_interface_open(enum hl_transports tr);
int hl_interface_init_target(struct target *t);
int hl_interface_init_reset(void);
int hl_interface_override_target(const char **targetname);
#endif /* _HL_INTERFACE */

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@ -74,7 +74,9 @@ struct hl_layout_api_s {
*/
int (*idcode) (void *handle, uint32_t *idcode);
/** */
enum target_state (*state) (void *handle);
int (*override_target) (const char *targetname);
/** */
enum target_state (*state) (void *fd);
};
/** */

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@ -59,7 +59,13 @@ static int jim_newtap_expected_id(Jim_Nvp *n, Jim_GetOptInfo *goi,
return JIM_OK;
}
#define NTAP_OPT_EXPECTED_ID 0
#define NTAP_OPT_IRLEN 0
#define NTAP_OPT_IRMASK 1
#define NTAP_OPT_IRCAPTURE 2
#define NTAP_OPT_ENABLED 3
#define NTAP_OPT_DISABLED 4
#define NTAP_OPT_EXPECTED_ID 5
#define NTAP_OPT_VERSION 6
static int jim_hl_newtap_cmd(Jim_GetOptInfo *goi)
{
@ -69,8 +75,14 @@ static int jim_hl_newtap_cmd(Jim_GetOptInfo *goi)
Jim_Nvp *n;
char *cp;
const Jim_Nvp opts[] = {
{.name = "-expected-id", .value = NTAP_OPT_EXPECTED_ID},
{.name = NULL, .value = -1},
{ .name = "-irlen", .value = NTAP_OPT_IRLEN },
{ .name = "-irmask", .value = NTAP_OPT_IRMASK },
{ .name = "-ircapture", .value = NTAP_OPT_IRCAPTURE },
{ .name = "-enable", .value = NTAP_OPT_ENABLED },
{ .name = "-disable", .value = NTAP_OPT_DISABLED },
{ .name = "-expected-id", .value = NTAP_OPT_EXPECTED_ID },
{ .name = "-ignore-version", .value = NTAP_OPT_VERSION },
{ .name = NULL, .value = -1},
};
pTap = calloc(1, sizeof(struct jtag_tap));
@ -121,6 +133,12 @@ static int jim_hl_newtap_cmd(Jim_GetOptInfo *goi)
return e;
}
break;
case NTAP_OPT_IRLEN:
case NTAP_OPT_IRMASK:
case NTAP_OPT_IRCAPTURE:
/* dummy read to ignore the next argument */
Jim_GetOpt_Wide(goi, NULL);
break;
} /* switch (n->value) */
} /* while (goi->argc) */

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@ -134,6 +134,12 @@ static const struct command_registration stlink_transport_command_handlers[] = {
.usage = "",
.chain = hl_transport_jtag_subcommand_handlers,
},
{
.name = "jtag_ntrst_delay",
.mode = COMMAND_ANY,
.handler = hl_transport_jtag_command,
.usage = "",
},
COMMAND_REGISTRATION_DONE
};
@ -204,12 +210,14 @@ static struct transport hl_swd_transport = {
.name = "hla_swd",
.select = hl_transport_select,
.init = hl_transport_init,
.override_target = hl_interface_override_target,
};
static struct transport hl_jtag_transport = {
.name = "hla_jtag",
.select = hl_transport_select,
.init = hl_transport_init,
.override_target = hl_interface_override_target,
};
static struct transport stlink_swim_transport = {

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@ -55,6 +55,7 @@
#include "trace.h"
#include "image.h"
#include "rtos/rtos.h"
#include "transport/transport.h"
/* default halt wait timeout (ms) */
#define DEFAULT_HALT_TIMEOUT 5000
@ -5066,6 +5067,15 @@ static int target_create(Jim_GetOptInfo *goi)
if (e != JIM_OK)
return e;
cp = cp2;
struct transport *tr = get_current_transport();
if (tr->override_target) {
e = tr->override_target(&cp);
if (e != ERROR_OK) {
LOG_ERROR("The selected transport doesn't support this target");
return JIM_ERR;
}
LOG_INFO("The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD");
}
/* now does target type exist */
for (x = 0 ; target_types[x] ; x++) {
if (0 == strcmp(cp, target_types[x]->name)) {

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@ -65,6 +65,14 @@ struct transport {
*/
int (*init)(struct command_context *ctx);
/**
* Optional. If defined, allows transport to override target
* name prior to initialisation.
*
* @returns ERROR_OK on success, or an error code on failure.
*/
int (*override_target)(const char **targetname);
/**
* Transports are stored in a singly linked list.
*/

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@ -10,6 +10,8 @@
#
source [find interface/ti-icdi.cfg]
transport select hla_jtag
set WORKAREASIZE 0x8000
set CHIPNAME lm4f120h5qr
source [find target/stellaris_icdi.cfg]
source [find target/stellaris.cfg]

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@ -10,6 +10,8 @@
#
source [find interface/ti-icdi.cfg]
transport select hla_jtag
set WORKAREASIZE 0x8000
set CHIPNAME lm4f23x
source [find target/stellaris_icdi.cfg]
source [find target/stellaris.cfg]

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@ -6,6 +6,8 @@
source [find interface/ti-icdi.cfg]
transport select hla_jtag
set WORKAREASIZE 0x8000
set CHIPNAME tm4c123gh6pm
source [find target/stellaris_icdi.cfg]
source [find target/stellaris.cfg]

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@ -3,7 +3,9 @@
source [find interface/stlink-v2-1.cfg]
source [find target/stm32f0x_stlink.cfg]
transport select hla_swd
source [find target/stm32f0x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -3,7 +3,9 @@
source [find interface/stlink-v2-1.cfg]
source [find target/stm32f1x_stlink.cfg]
transport select hla_swd
source [find target/stm32f1x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -3,7 +3,9 @@
source [find interface/stlink-v2-1.cfg]
source [find target/stm32f3x_stlink.cfg]
transport select hla_swd
source [find target/stm32f3x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -3,7 +3,9 @@
source [find interface/stlink-v2-1.cfg]
source [find target/stm32f4x_stlink.cfg]
transport select hla_swd
source [find target/stm32f4x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -6,13 +6,15 @@
source [find interface/stlink-v2.cfg]
transport select hla_swd
# increase working area to 8KB
set WORKAREASIZE 0x2000
# chip name
set CHIPNAME STM32F051R8T6
source [find target/stm32f0x_stlink.cfg]
source [find target/stm32f0x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -6,13 +6,15 @@
source [find interface/stlink-v2.cfg]
transport select hla_swd
# increase working area to 128KB
set WORKAREASIZE 0x20000
# chip name
set CHIPNAME STM32F207IGH6
source [find target/stm32f2x_stlink.cfg]
source [find target/stm32f2x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -6,13 +6,15 @@
source [find interface/stlink-v2.cfg]
transport select hla_swd
# increase working area to 128KB
set WORKAREASIZE 0x20000
# chip name
set CHIPNAME STM32F417IGH6
source [find target/stm32f4x_stlink.cfg]
source [find target/stm32f4x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -6,13 +6,15 @@
source [find interface/stlink-v2.cfg]
transport select hla_swd
# increase working area to 128KB
set WORKAREASIZE 0x20000
# chip name
set CHIPNAME STM32F429NIH6
source [find target/stm32f4x_stlink.cfg]
source [find target/stm32f4x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -6,13 +6,15 @@
source [find interface/stlink-v2.cfg]
transport select hla_swd
# increase working area to 128KB
set WORKAREASIZE 0x20000
# chip name
set CHIPNAME STM32F439NIH6
source [find target/stm32f4x_stlink.cfg]
source [find target/stm32f4x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -3,8 +3,10 @@
source [find interface/stlink-v2.cfg]
transport select hla_swd
set WORKAREASIZE 0x2000
source [find target/stm32f0x_stlink.cfg]
source [find target/stm32f0x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -3,7 +3,9 @@
source [find interface/stlink-v2.cfg]
source [find target/stm32f3x_stlink.cfg]
transport select hla_swd
source [find target/stm32f3x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -5,7 +5,9 @@
source [find interface/stlink-v2.cfg]
source [find target/stm32f4x_stlink.cfg]
transport select hla_swd
source [find target/stm32f4x.cfg]
# use hardware reset, connect under reset supported
reset_config srst_only srst_nogate

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@ -3,7 +3,9 @@
source [find interface/stlink-v2.cfg]
source [find target/stm32f4x_stlink.cfg]
transport select hla_swd
source [find target/stm32f4x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -3,8 +3,10 @@
source [find interface/stlink-v2.cfg]
transport select hla_swd
set WORKAREASIZE 0x4000
source [find target/stm32lx_stlink.cfg]
source [find target/stm32lx.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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@ -3,6 +3,8 @@
source [find interface/stlink-v1.cfg]
set WORKAREASIZE 0x2000
source [find target/stm32f1x_stlink.cfg]
transport select hla_swd
set WORKAREASIZE 0x2000
source [find target/stm32f1x.cfg]

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@ -26,8 +26,12 @@ if { [info exists WORKAREASIZE] } {
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
set _CPUTAPID 0x4ba00477
# SWD IDCODE 0x2ba01477
} {
# SWD IDCODE
set _CPUTAPID 0x2ba01477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@ -52,6 +56,8 @@ if {[using_jtag]} {
jtag_ntrst_delay 100
}
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

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@ -80,6 +80,8 @@ if {[using_jtag]} {
jtag_ntrst_delay 100
}
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

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@ -3,6 +3,8 @@
# Configuration for Atmel's SAM3N series
#
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
@ -15,7 +17,7 @@ if { [info exists CPUTAPID] } {
set _CPUTAPID 0x4ba00477
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
@ -23,7 +25,8 @@ target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
set _FLASHNAME $_CHIPNAME.flash
flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

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@ -42,10 +42,6 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAM
# 16K is plenty, the smallest chip has this much
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
$_TARGETNAME configure -event gdb-flash-erase-start {
halt
}
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
#
# Since we may be running of an RC oscilator, we crank down the speed a
@ -60,6 +56,8 @@ if {[using_jtag]} {
jtag_ntrst_delay 100
}
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

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@ -40,10 +40,6 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAM
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
$_TARGETNAME configure -event gdb-flash-erase-start {
halt
}
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
#
# Since we may be running of an RC oscilator, we crank down the speed a
@ -54,9 +50,11 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
adapter_khz 500
adapter_nsrst_delay 100
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME

43
tcl/target/efm32.cfg Normal file
View File

@ -0,0 +1,43 @@
#
# efm32 target
#
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME efm32
}
# Work-area is a space in RAM used for flash programming
# By default use 2kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x800
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x2ba01477
}
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
adapter_khz 1000
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

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@ -1,42 +1,2 @@
#
# efm32 stlink pseudo target
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME efm32
}
# Work-area is a space in RAM used for flash programming
# By default use 2kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x800
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x2ba01477
}
# EFM32 MCUs only support SWD interface
set _TRANSPORT hla_swd
transport select $_TRANSPORT
hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
echo "WARNING: target/efm32_stlink.cfg is deprecated, please switch to target/efm32.cfg"
source [find target/efm32.cfg]

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@ -1,6 +1,8 @@
# MB9BF506
# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
@ -21,12 +23,14 @@ if { [info exists CPUTAPID] } {
# delays on reset lines
adapter_nsrst_delay 100
jtag_ntrst_delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
# Fujitsu cortex-M3 reset configuration
reset_config trst_only
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
@ -42,6 +46,8 @@ flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
# 4MHz / 6 = 666kHz, so use 500
adapter_khz 500
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

View File

@ -34,6 +34,8 @@ target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

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@ -34,6 +34,8 @@ target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

View File

@ -55,9 +55,11 @@ flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
# specifies up to 1MHz for VLPR mode.
adapter_khz 1000
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
$_TARGETNAME configure -event reset-init {
# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual

View File

@ -1,63 +1,2 @@
# MKL25Z128VLK4
# FreeScale Cortex-M0plus with 128kB Flash and 16kB Local On-Chip SRAM
if { [info exists CHIPNAME] == 0 } {
set _CHIPNAME kl25z
}
if { [info exists CPUTAPID] == 0 } {
set _CPUTAPID 0x0BC11477
}
if { [info exists WORKAREASIZE] == 0 } {
set _WORKAREASIZE 0x3000
}
if { [info exists TRANSPORT] == 0 } {
set _TRANSPORT hla_swd
}
transport select $_TRANSPORT
hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
# It is important that "kinetis mdm check_security" is called for
# 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start'
# causes "kinetis mdm check_security" to fail the first time openocd
# calls it when it tries to connect after the CPU has been power-cycled.
$_CHIPNAME.cpu configure -event examine-end {
kinetis mdm check_security
}
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
flash bank pflash kinetis 0x00000000 0x20000 0 4 $_TARGETNAME
proc kl25z_enable_pll {} {
echo "KL25Z: Enabling PLL"
# SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
mww 0x40048044 0x00020000
# /* Switch to FEI Mode */
# MCG->C1 = (uint8_t)0x06U;
mwb 0x40064000 0x06
# MCG->C2 = (uint8_t)0x00U;
mwb 0x40064001 0x00
# /* MCG->C4: DMX32=0,DRST_DRS=1 */
# MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
mwb 0x40064003 0x37
#OSC0->CR = (uint8_t)0x80U;
mwb 0x40065000 0x80
# MCG->C5 = (uint8_t)0x00U;
mwb 0x40064004 0x00
# MCG->C6 = (uint8_t)0x00U;
mwb 0x40064005 0x00
sleep 100
}
$_TARGETNAME configure -event reset-init {
kl25z_enable_pll
}
echo "WARNING: target/kl25z_hla.cfg is deprecated, please switch to target/kl25.cfg"
source [find target/kl25.cfg]

View File

@ -43,6 +43,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

View File

@ -43,6 +43,8 @@ $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
#set _FLASHNAME $_CHIPNAME.flash
#flash bank $_FLASHNAME lpc2000 0 0 0 0 $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

View File

@ -14,7 +14,4 @@ set CPUROMSIZE 0x80000
set CCLK 12000
#Include the main configuration file.
source [find target/lpc17xx.cfg];
# if srst is not fitted, use SYSRESETREQ to perform a soft reset
cortex_m reset_config sysresetreq
source [find target/lpc17xx.cfg]

View File

@ -94,6 +94,8 @@ $_TARGETNAME configure -event reset-init {
mww 0x400FC040 0x01
}
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

View File

@ -1,3 +1,4 @@
source [find target/swj-dp.tcl]
adapter_khz 500
@ -21,11 +22,13 @@ if { [info exists M3_JTAG_TAPID] } {
set _M3_JTAG_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
swj_newdap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
set _TARGETNAME $_CHIPNAME.m3
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

View File

@ -1,3 +1,4 @@
source [find target/swj-dp.tcl]
adapter_khz 500
@ -25,6 +26,12 @@ if { [info exists M4_SWD_TAPID] } {
set _M4_SWD_TAPID 0x2ba01477
}
if { [using_jtag] } {
set _M4_TAPID $_M4_JTAG_TAPID
} {
set _M4_TAPID $_M4_SWD_TAPID
}
#
# M0 TAP
#
@ -34,18 +41,21 @@ if { [info exists M0_JTAG_TAPID] } {
set _M0_JTAG_TAPID 0x0ba01477
}
jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M4_JTAG_TAPID
jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M0_JTAG_TAPID
swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M4_TAPID
target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
# on this CPU we should use VECTRESET to perform a soft reset and
# manually reset the periphery
# SRST or SYSRESETREQ disable the debug interface for the time of
# the reset and will not fit our requirements for a consistent debug
# session
cortex_m reset_config vectreset
if { [using_jtag] } {
swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M0_JTAG_TAPID
target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
}
if {![using_hla]} {
# on this CPU we should use VECTRESET to perform a soft reset and
# manually reset the periphery
# SRST or SYSRESETREQ disable the debug interface for the time of
# the reset and will not fit our requirements for a consistent debug
# session
cortex_m reset_config vectreset
}

View File

@ -26,7 +26,12 @@ if { [info exists WORKAREASIZE] } {
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
set _CPUTAPID 0x4ba00477
} {
# SWD IDCODE
set _CPUTAPID 0x2ba01477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@ -50,6 +55,8 @@ if {[using_jtag]} {
jtag_ntrst_delay 100
}
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

52
tcl/target/nrf51.cfg Normal file
View File

@ -0,0 +1,52 @@
#
# script for Nordic nRF51 series, a CORTEX-M0 chip
#
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME nrf51
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
# Work-area is a space in RAM used for flash programming
# By default use 2kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x800
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x0bb11477
}
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
if {![using_hla]} {
# The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
cortex_m reset_config sysresetreq
}
flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME
flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
#
# The chip should start up from internal 16Mhz RC, so setting adapter
# clock to 1Mhz should be OK
#
adapter_khz 1000

View File

@ -1,70 +1,2 @@
#
# script for Nordic nRF51 series, a CORTEX-M0 chip
#
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME nrf51
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
# Work-area is a space in RAM used for flash programming
# By default use 2kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x800
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x0bb11477
}
if { [info exists TRANSPORT] } {
set _TRANSPORT $TRANSPORT
if { $TRANSPORT == "hla_jtag" } {
if { [info exists CPUTAPID] == 0 } {
# jtag requires us to use the jtag tap id
set _CPUTAPID 0x3ba00477
}
}
} else {
set _TRANSPORT hla_swd
}
# add deprecated transport name check
if { $_TRANSPORT == "stlink_swd" } {
set _TRANSPORT "hla_swd"
echo "DEPRECATED! use 'hla_swd' transport not 'stlink_swd'"
}
if { $_TRANSPORT == "stlink_jtag" } {
set _TRANSPORT "hla_jtag"
echo "DEPRECATED! use 'hla_jtag' transport not 'stlink_jtag'"
}
# end deprecated checks
transport select $_TRANSPORT
hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal, so for
# non-"hla" targets it would be useful to have the following in the config.
# cortex_m reset_config sysresetreq
flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME
flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
echo "WARNING: target/nrf51_stlink.cfg is deprecated, please switch to target/nrf51.cfg"
source [find target/nrf51.cfg]

View File

@ -156,13 +156,16 @@ $_TARGETNAME configure -event reset-start {
if {$device_class == 0 || $device_class == 1 ||
$device_class == 3 || $device_class == 5} {
if {![using_hla]} {
# Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ
cortex_m reset_config sysresetreq
}
} else {
if {![using_hla]} {
# Tempest and Firestorm default to using NVIC VECTRESET
# peripherals will need reseting manually, see proc reset_peripherals
cortex_m reset_config vectreset
}
# reset peripherals, based on code in
# http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
reset_peripherals $device_class

View File

@ -1,34 +1,2 @@
#
# lm3s icdi pseudo target
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lm3s
}
# Work-area is a space in RAM used for flash programming
# By default use 16kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x4000
}
#
# possible value are hla_jtag
# currently swd is not supported
#
transport select hla_jtag
# do not check id as icdi currently does not support it
hla newtap $_CHIPNAME cpu -expected-id 0
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# flash configuration ... autodetects sizes, autoprobed
flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
echo "WARNING: target/stellaris_icdi.cfg is deprecated, please switch to target/stellaris.cfg"
source [find target/stellaris.cfg]

View File

@ -1,60 +1 @@
#
# stm32 stlink pseudo target
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32f1x
}
# Work-area is a space in RAM used for flash programming
# By default use 4kB (as found on some STM32F100s)
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x1000
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# this is the SW-DP tap id not the jtag tap id
set _CPUTAPID 0x1ba01477
}
if { [info exists TRANSPORT] } {
set _TRANSPORT $TRANSPORT
if { $TRANSPORT == "hla_jtag" } {
if { [info exists CPUTAPID] == 0 } {
# jtag requires us to use the jtag tap id
set _CPUTAPID 0x3ba00477
}
}
} else {
set _TRANSPORT hla_swd
}
# add deprecated transport name check
if { $_TRANSPORT == "stlink_swd" } {
set _TRANSPORT "hla_swd"
echo "DEPRECATED! use 'hla_swd' transport not 'stlink_swd'"
}
if { $_TRANSPORT == "stlink_jtag" } {
set _TRANSPORT "hla_jtag"
echo "DEPRECATED! use 'hla_jtag' transport not 'stlink_jtag'"
}
# end deprecated checks
#
# possibles value are hla_swd or hla_jtag
#
transport select $_TRANSPORT
hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
echo "WARNING: stm32_stlink.cfg is deprecated (and does nothing, you can safely remove it.)"

View File

@ -50,6 +50,8 @@ adapter_khz 1000
adapter_nsrst_delay 100
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

View File

@ -1,21 +1,2 @@
#
# STM32f0x stlink pseudo target
#
if { [info exists CHIPNAME] == 0 } {
set CHIPNAME stm32f0x
}
if { [info exists CPUTAPID] == 0 } {
set CPUTAPID 0x0bb11477
}
if { [info exists WORKAREASIZE] == 0 } {
set WORKAREASIZE 0x1000
}
source [find target/stm32_stlink.cfg]
# stm32f0x family uses stm32f1x driver
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
echo "WARNING: target/stm32f0x_stlink.cfg is deprecated, please switch to target/stm32f0x.cfg"
source [find target/stm32f0x.cfg]

View File

@ -29,9 +29,13 @@ if { [info exists WORKAREASIZE] } {
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# See STM Document RM0008
# Section 26.6.3
if { [using_jtag] } {
# See STM Document RM0008 Section 26.6.3
set _CPUTAPID 0x3ba00477
} {
# this is the SW-DP tap id not the jtag tap id
set _CPUTAPID 0x1ba01477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@ -62,7 +66,7 @@ if { [info exists BSTAPID] } {
}
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
-expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
-expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
-expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \
@ -86,6 +90,8 @@ if {[using_jtag]} {
jtag_ntrst_delay 100
}
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

View File

@ -1,20 +1,2 @@
#
# STM32f1x stlink pseudo target
#
if { [info exists CHIPNAME] == 0 } {
set CHIPNAME stm32f1x
}
if { [info exists CPUTAPID] == 0 } {
set CPUTAPID 0x1ba01477
}
if { [info exists WORKAREASIZE] == 0 } {
set WORKAREASIZE 0x1000
}
source [find target/stm32_stlink.cfg]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
echo "WARNING: target/stm32f1x_stlink.cfg is deprecated, please switch to target/stm32f1x.cfg"
source [find target/stm32f1x.cfg]

View File

@ -42,9 +42,13 @@ if {[using_jtag]} {
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
# See STM Document RM0033
# Section 32.6.3 - corresponds to Cortex-M3 r2p0
set _CPUTAPID 0x4ba00477
} {
set _CPUTAPID 0x2ba01477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@ -59,7 +63,7 @@ if { [info exists BSTAPID] } {
}
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
}
set _TARGETNAME $_CHIPNAME.cpu
@ -70,6 +74,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

View File

@ -1,20 +1,2 @@
#
# STM32f2x stlink pseudo target
#
if { [info exists CHIPNAME] == 0 } {
set CHIPNAME stm32f2x
}
if { [info exists CPUTAPID] == 0 } {
set CPUTAPID 0x2ba01477
}
if { [info exists WORKAREASIZE] == 0 } {
set WORKAREASIZE 0x10000
}
source [find target/stm32_stlink.cfg]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
echo "WARNING: target/stm32f2x_stlink.cfg is deprecated, please switch to target/stm32f2x.cfg"
source [find target/stm32f2x.cfg]

View File

@ -42,9 +42,13 @@ if {[using_jtag]} {
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
# See STM Document RM0316
# Section 29.6.3 - corresponds to Cortex-M4 r0p1
set _CPUTAPID 0x4ba00477
} {
set _CPUTAPID 0x2ba01477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@ -59,7 +63,7 @@ if { [info exists BSTAPID] } {
}
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
}
set _TARGETNAME $_CHIPNAME.cpu
@ -70,6 +74,8 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

View File

@ -1,20 +1,2 @@
#
# STM32f3x stlink pseudo target
#
if { [info exists CHIPNAME] == 0 } {
set CHIPNAME stm32f3x
}
if { [info exists CPUTAPID] == 0 } {
set CPUTAPID 0x2ba01477
}
if { [info exists WORKAREASIZE] == 0 } {
set WORKAREASIZE 0x4000
}
source [find target/stm32_stlink.cfg]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
echo "WARNING: target/stm32f3x_stlink.cfg is deprecated, please switch to target/stm32f3x.cfg"
source [find target/stm32f3x.cfg]

View File

@ -29,9 +29,13 @@ if { [info exists WORKAREASIZE] } {
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
# See STM Document RM0090
# Section 38.6.3 - corresponds to Cortex-M4 r0p1
set _CPUTAPID 0x4ba00477
} {
set _CPUTAPID 0x2ba01477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@ -48,7 +52,7 @@ if { [info exists BSTAPID] } {
}
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
-expected-id $_BSTAPID2
}
@ -73,6 +77,8 @@ if {[using_jtag]} {
jtag_ntrst_delay 100
}
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}

View File

@ -1,21 +1,2 @@
#
# STM32f4x stlink pseudo target
#
if { [info exists CHIPNAME] == 0 } {
set CHIPNAME stm32f4x
}
if { [info exists CPUTAPID] == 0 } {
set CPUTAPID 0x2ba01477
}
if { [info exists WORKAREASIZE] == 0 } {
set WORKAREASIZE 0x10000
}
source [find target/stm32_stlink.cfg]
# stm32f4x family uses stm32f2x driver
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
echo "WARNING: target/stm32f4x_stlink.cfg is deprecated, please switch to target/stm32f4x.cfg"
source [find target/stm32f4x.cfg]

View File

@ -38,9 +38,13 @@ if {[using_jtag]} {
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
# See STM Document RM0038
# Section 24.6.3
set _CPUTAPID 0x4ba00477
} {
set _CPUTAPID 0x2ba01477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@ -55,7 +59,7 @@ if { [info exists BSTAPID] } {
}
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
}
set _TARGETNAME $_CHIPNAME.cpu
@ -67,9 +71,11 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
proc stm32l_enable_HSI {} {
# Enable HSI as clock source

View File

@ -1,9 +1,8 @@
source [find target/stm32l.cfg]
# The stm32lx 384kb have a dual bank flash.
# Let's add a definition for the second bank here.
# script for stm32lx family
source [find target/stm32lx_stlink.cfg]
# Add the second flash bank.
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32lx 0x8030000 0 0 0 $_TARGETNAME

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@ -1,47 +1,2 @@
#
# STM32lx stlink pseudo target
#
if { [info exists CHIPNAME] == 0 } {
set CHIPNAME stm32lx
}
if { [info exists CPUTAPID] == 0 } {
set CPUTAPID 0x2ba01477
}
if { [info exists WORKAREASIZE] == 0 } {
set WORKAREASIZE 0x2800
}
source [find target/stm32_stlink.cfg]
# Flash base address is known by driver. Flash size will be probed.
#
# Please note that the larger stm32lx targets (256Kb and 384Kb) uses dual
# bank flash. For such targets use target/stm32lx_dual_bank.cfg.
#
# Some samples of ST's stm32lx chips are known to have incorrect flash size
# values programmed in their FLASH_SIZE register. The driver will warn
# for strange values. It is possible to override the flash size probe by
# defining the correct size here. Notice though that it is the size of
# the flash bank
#
# flash bank stm32lx <base> <size> 0 0 <target#> <variant>
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
proc stm32l_enable_HSI {} {
# Enable HSI as clock source
echo "STM32L: Enabling HSI"
# Set HSION in RCC_CR
mww 0x40023800 0x00000101
# Set HSI as SYSCLK
mww 0x40023808 0x00000001
}
$_TARGETNAME configure -event reset-init {
stm32l_enable_HSI
}
echo "WARNING: target/stm32lx_stlink.cfg is deprecated, please switch to target/stm32l.cfg"
source [find target/stm32l.cfg]

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@ -1,23 +1,2 @@
#
# STM32W108xx stlink pseudo target
#
if { [info exists CHIPNAME] == 0 } {
set CHIPNAME stm32w108
}
if { [info exists CPUTAPID] == 0 } {
set CPUTAPID 0x1ba01477
}
if { [info exists WORKAREASIZE] == 0 } {
# 4k -- This should work for all chips, though perhaps not optimally
set WORKAREASIZE 0x1000
}
source [find target/stm32_stlink.cfg]
# Use the flash driver from the EM357
set _FLASHNAME $_CHIPNAME.flash
# 64k (0x10000) of flash
flash bank $_FLASHNAME em357 0x08000000 0x10000 0 0 $_TARGETNAME
echo "WARNING: target/stm32w108xx_stlink.cfg is deprecated, please switch to target/stm32w108xx.cfg"
source [find target/stm32w108xx.cfg]

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@ -27,7 +27,11 @@ if { [info exists WORKAREASIZE] } {
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
set _CPUTAPID 0x3ba00477
} {
set _CPUTAPID 0x1ba01477
}
}
if { [info exists ENDIAN] } {
@ -41,11 +45,11 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
if {[using_jtag]} {
if { [info exists BSTAPID] } {
set _BSTAPID $BSTAPID
jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id 0x269a862b
swj_newdap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID
} else {
set _BSTAPID_1 0x169a862b
set _BSTAPID_2 0x269a862b
jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \
swj_newdap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \
-expected-id $_BSTAPID_1 -expected-id $_BSTAPID_2
}
}
@ -63,5 +67,6 @@ set _FLASHNAME $_CHIPNAME.flash
# 64k (0x10000) of flash
flash bank $_FLASHNAME em357 0x08000000 0x10000 0 0 $_TARGETNAME
cortex_m reset_config sysresetreq
if {![using_hla]} {
cortex_m reset_config sysresetreq
}

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@ -24,7 +24,13 @@ if [catch {transport select}] {
}
proc swj_newdap {chip tag args} {
if {[using_jtag]} { eval jtag newtap $chip $tag $args }
if {[using_swd]} { eval swd newdap $chip $tag $args }
if {[string equal [transport select] "cmsis-dap"]} { eval cmsis-dap newdap $chip $tag $args }
if [using_hla] {
eval hla newtap $chip $tag $args
} elseif [using_jtag] {
eval jtag newtap $chip $tag $args
} elseif [using_swd] {
eval swd newdap $chip $tag $args
} elseif [string equal [transport select] "cmsis-dap"] {
eval cmsis-dap newdap $chip $tag $args
}
}