imi415
/
openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arm_adi_v5: move in a separate function devtype decode/display 

For readability, move in a separate function the decoding and the
display of devtype register.
The function will be reused with ADIv6.

Split from change https://review.openocd.org/6077/

Change-Id: I7a26a2c9759d5db5f9acfae5c169b90b3deb2f18
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6448
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
This commit is contained in:
Kevin Burke 2021-08-10 16:26:42 +02:00 committed by Antonio Borneo
parent ddbc13a6f2
commit cf6909a57c
1 changed files with 149 additions and 140 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

233
src/target/arm_adi_v5.c
View File

@ -1227,120 +1227,11 @@ static const struct {
{ ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
};
static int dap_rom_display(struct command_invocation *cmd,
struct adiv5_ap *ap, target_addr_t dbgbase, int depth)
static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
{
int retval;
uint64_t pid;
uint32_t cid;
char tabs[16] = "";
if (depth > 16) {
command_print(cmd, "\tTables too deep");
return ERROR_FAIL;
}
if (depth)
snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
target_addr_t base_addr = dbgbase & 0xFFFFFFFFFFFFF000ull;
command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, base_addr);
retval = dap_read_part_id(ap, base_addr, &cid, &pid);
if (retval != ERROR_OK) {
command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
return ERROR_OK; /* Don't abort recursion */
}
if (!is_valid_arm_cs_cidr(cid)) {
command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, cid);
return ERROR_OK; /* Don't abort recursion */
}
/* component may take multiple 4K pages */
uint32_t size = ARM_CS_PIDR_SIZE(pid);
if (size > 0)
command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, base_addr - 0x1000 * size);
command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
uint8_t class = (cid & ARM_CS_CIDR_CLASS_MASK) >> ARM_CS_CIDR_CLASS_SHIFT;
uint16_t part_num = ARM_CS_PIDR_PART(pid);
uint16_t designer_id = ARM_CS_PIDR_DESIGNER(pid);
if (pid & ARM_CS_PIDR_JEDEC) {
/* JEP106 code */
command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s",
designer_id, jep106_manufacturer(designer_id));
} else {
/* Legacy ASCII ID, clear invalid bits */
designer_id &= 0x7f;
command_print(cmd, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
}
/* default values to be overwritten upon finding a match */
const char *type = "Unrecognized";
const char *full = "";
/* search dap_partnums[] array for a match */
for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
continue;
if (dap_partnums[entry].part_num != part_num)
continue;
type = dap_partnums[entry].type;
full = dap_partnums[entry].full;
break;
}
command_print(cmd, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
command_print(cmd, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
uint32_t memtype;
retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C1_MEMTYPE, &memtype);
if (retval != ERROR_OK)
return retval;
if (memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK)
command_print(cmd, "\t\tMEMTYPE system memory present on bus");
else
command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
/* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
uint32_t romentry;
retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
if (retval != ERROR_OK)
return retval;
command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
tabs, entry_offset, romentry);
if (romentry & ARM_CS_ROMENTRY_PRESENT) {
/* Recurse. "romentry" is signed */
retval = dap_rom_display(cmd, ap, base_addr + (int32_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK),
depth + 1);
if (retval != ERROR_OK)
return retval;
} else if (romentry != 0) {
command_print(cmd, "\t\tComponent not present");
} else {
command_print(cmd, "\t%s\tEnd of ROM table", tabs);
break;
}
}
} else if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
const char *major = "Reserved", *subtype = "Reserved";
uint32_t devtype;
retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C9_DEVTYPE, &devtype);
if (retval != ERROR_OK)
return retval;
unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
const unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
const unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
switch (devtype_major) {
case 0:
major = "Miscellaneous";
@ -1477,6 +1368,124 @@ static int dap_rom_display(struct command_invocation *cmd,
command_print(cmd, "\t\tType is 0x%02x, %s, %s",
devtype & ARM_CS_C9_DEVTYPE_MASK,
major, subtype);
return ERROR_OK;
}
static int dap_rom_display(struct command_invocation *cmd,
struct adiv5_ap *ap, target_addr_t dbgbase, int depth)
{
int retval;
uint64_t pid;
uint32_t cid;
char tabs[16] = "";
if (depth > 16) {
command_print(cmd, "\tTables too deep");
return ERROR_FAIL;
}
if (depth)
snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
target_addr_t base_addr = dbgbase & 0xFFFFFFFFFFFFF000ull;
command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, base_addr);
retval = dap_read_part_id(ap, base_addr, &cid, &pid);
if (retval != ERROR_OK) {
command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
return ERROR_OK; /* Don't abort recursion */
}
if (!is_valid_arm_cs_cidr(cid)) {
command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, cid);
return ERROR_OK; /* Don't abort recursion */
}
/* component may take multiple 4K pages */
uint32_t size = ARM_CS_PIDR_SIZE(pid);
if (size > 0)
command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, base_addr - 0x1000 * size);
command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
uint8_t class = (cid & ARM_CS_CIDR_CLASS_MASK) >> ARM_CS_CIDR_CLASS_SHIFT;
uint16_t part_num = ARM_CS_PIDR_PART(pid);
uint16_t designer_id = ARM_CS_PIDR_DESIGNER(pid);
if (pid & ARM_CS_PIDR_JEDEC) {
/* JEP106 code */
command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s",
designer_id, jep106_manufacturer(designer_id));
} else {
/* Legacy ASCII ID, clear invalid bits */
designer_id &= 0x7f;
command_print(cmd, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
}
/* default values to be overwritten upon finding a match */
const char *type = "Unrecognized";
const char *full = "";
/* search dap_partnums[] array for a match */
for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
continue;
if (dap_partnums[entry].part_num != part_num)
continue;
type = dap_partnums[entry].type;
full = dap_partnums[entry].full;
break;
}
command_print(cmd, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
command_print(cmd, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
uint32_t memtype;
retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C1_MEMTYPE, &memtype);
if (retval != ERROR_OK)
return retval;
if (memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK)
command_print(cmd, "\t\tMEMTYPE system memory present on bus");
else
command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
/* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
uint32_t romentry;
retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
if (retval != ERROR_OK)
return retval;
command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
tabs, entry_offset, romentry);
if (romentry & ARM_CS_ROMENTRY_PRESENT) {
/* Recurse. "romentry" is signed */
retval = dap_rom_display(cmd, ap, base_addr + (int32_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK),
depth + 1);
if (retval != ERROR_OK)
return retval;
} else if (romentry != 0) {
command_print(cmd, "\t\tComponent not present");
} else {
command_print(cmd, "\t%s\tEnd of ROM table", tabs);
break;
}
}
} else if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
uint32_t devtype;
retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C9_DEVTYPE, &devtype);
if (retval != ERROR_OK)
return retval;
retval = dap_devtype_display(cmd, devtype);
if (retval != ERROR_OK)
return retval;
/* REVISIT also show ARM_CS_C9_DEVID */
}