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tcl/target/renesas_rz_five: Added RZ/Five 

Added support for the new Renesas RISC-V
device: RZ/Five

Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Change-Id: Id8ba29b83528c0bfe4f9b4ed21b0151a6e853bd7
Reviewed-on: https://review.openocd.org/c/openocd/+/6974
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
This commit is contained in:
micbis 2022-05-12 15:17:49 +02:00 committed by Antonio Borneo
parent 19e992e882
commit e5f515f990
1 changed files with 22 additions and 0 deletions
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22
tcl/target/renesas_rz_five.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# Renesas RZ/Five SoC
#
# General-purpose Microprocessors with RISC-V CPU Core (Andes AX45MP Single) (1.0 GHz)
transport select jtag
reset_config trst_and_srst srst_gates_jtag
adapter speed 4000
adapter srst delay 500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME r9A07g043u
}
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME