Cortex-A8: basic watchpoint support
Actually this should handle both breakpoints and watchpoints ... but the DPM framework only handles watchpoints for now. Works on Beagle. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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@ -460,6 +460,66 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
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return cortex_a8_read_dcc(a8, data, &dscr);
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}
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static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
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uint32_t addr, uint32_t control)
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{
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struct cortex_a8_common *a8 = dpm_to_a8(dpm);
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uint32_t vr = a8->armv7a_common.debug_base;
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uint32_t cr = a8->armv7a_common.debug_base;
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int retval;
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switch (index) {
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case 0 ... 15: /* breakpoints */
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vr += CPUDBG_BVR_BASE;
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cr += CPUDBG_BCR_BASE;
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break;
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case 16 ... 31: /* watchpoints */
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vr += CPUDBG_WVR_BASE;
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cr += CPUDBG_WCR_BASE;
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index -= 16;
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break;
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default:
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return ERROR_FAIL;
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}
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vr += 4 * index;
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cr += 4 * index;
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LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
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(unsigned) vr, (unsigned) cr);
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retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
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vr, addr);
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if (retval != ERROR_OK)
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return retval;
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retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
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cr, control);
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return retval;
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}
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static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index)
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{
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struct cortex_a8_common *a8 = dpm_to_a8(dpm);
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uint32_t cr;
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switch (index) {
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case 0 ... 15:
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cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
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break;
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case 16 ... 31:
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cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
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index -= 16;
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break;
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default:
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return ERROR_FAIL;
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}
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cr += 4 * index;
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LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
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/* clear control register */
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return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
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}
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static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
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{
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struct arm_dpm *dpm = &a8->armv7a_common.dpm;
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@ -477,6 +537,9 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
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dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
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dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
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dpm->bpwp_enable = cortex_a8_bpwp_enable;
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dpm->bpwp_disable = cortex_a8_bpwp_disable;
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return arm_dpm_setup(dpm);
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}
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@ -745,6 +808,7 @@ static int cortex_a8_debug_entry(struct target *target)
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case 5: /* vector catch */
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target->debug_reason = DBG_REASON_BREAKPOINT;
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break;
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case 2: /* asynch watchpoint */
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case 10: /* precise watchpoint */
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target->debug_reason = DBG_REASON_WATCHPOINT;
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/* REVISIT could collect WFAR later, to see just
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@ -1276,6 +1340,8 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address,
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*
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* For both ICache and DCache, walk all cache lines in the
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* address range. Cortex-A8 has fixed 64 byte line length.
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*
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* REVISIT per ARMv7, these may trigger watchpoints ...
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*/
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/* invalidate I-Cache */
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