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flash/stm32fxx.c: do not read CPUID as this info is stored in cortex_m_common 

In these drivers we read CPUID to check the Cortex-M PARTNO,
but now the PARTNO is stored in struct cortex_m_common.core_info.

Change-Id: I5bb3b95210ab6e23b8e1252686dd81015740bf68
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6240
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tarek BOCHKATI 2021-05-13 14:28:24 +01:00 committed by Antonio Borneo
parent 1185760729
commit f5898bd93f
2 changed files with 37 additions and 44 deletions
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61
src/flash/nor/stm32f1x.c
View File

@ -29,7 +29,7 @@
#include "imp.h" #include "imp.h"
#include <helper/binarybuffer.h> #include <helper/binarybuffer.h>
#include <target/algorithm.h> #include <target/algorithm.h>
#include <target/armv7m.h> #include <target/cortex_m.h>
/* stm32x register locations */ /* stm32x register locations */
@ -623,34 +623,32 @@ cleanup:
static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id) static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
{ {
/* This check the device CPUID core register to detect
* the M0 from the M3 devices. */
struct target *target = bank->target; struct target *target = bank->target;
uint32_t cpuid, device_id_register = 0; struct cortex_m_common *cortex_m = target_to_cm(target);
uint32_t device_id_register = 0;
/* Get the CPUID from the ARM Core if (!target_was_examined(target)) {
* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */ LOG_ERROR("Target not examined yet");
int retval = target_read_u32(target, 0xE000ED00, &cpuid); return ERROR_FAIL;
if (retval != ERROR_OK) }
return retval;
if (((cpuid >> 4) & 0xFFF) == 0xC20) { switch (cortex_m->core_info->partno) {
/* 0xC20 is M0 devices */ case CORTEX_M0_PARTNO: /* STM32F0x devices */
device_id_register = 0x40015800; device_id_register = 0x40015800;
} else if (((cpuid >> 4) & 0xFFF) == 0xC23) { break;
/* 0xC23 is M3 devices */ case CORTEX_M3_PARTNO: /* STM32F1x devices */
device_id_register = 0xE0042000; device_id_register = 0xE0042000;
} else if (((cpuid >> 4) & 0xFFF) == 0xC24) { break;
/* 0xC24 is M4 devices */ case CORTEX_M4_PARTNO: /* STM32F3x devices */
device_id_register = 0xE0042000; device_id_register = 0xE0042000;
} else { break;
default:
LOG_ERROR("Cannot identify target as a stm32x"); LOG_ERROR("Cannot identify target as a stm32x");
return ERROR_FAIL; return ERROR_FAIL;
} }
/* read stm32 device id register */ /* read stm32 device id register */
retval = target_read_u32(target, device_id_register, device_id); int retval = target_read_u32(target, device_id_register, device_id);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
@ -660,27 +658,30 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb) static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
{ {
struct target *target = bank->target; struct target *target = bank->target;
uint32_t cpuid, flash_size_reg; struct cortex_m_common *cortex_m = target_to_cm(target);
uint32_t flash_size_reg;
int retval = target_read_u32(target, 0xE000ED00, &cpuid); if (!target_was_examined(target)) {
if (retval != ERROR_OK) LOG_ERROR("Target not examined yet");
return retval; return ERROR_FAIL;
}
if (((cpuid >> 4) & 0xFFF) == 0xC20) { switch (cortex_m->core_info->partno) {
/* 0xC20 is M0 devices */ case CORTEX_M0_PARTNO: /* STM32F0x devices */
flash_size_reg = 0x1FFFF7CC; flash_size_reg = 0x1FFFF7CC;
} else if (((cpuid >> 4) & 0xFFF) == 0xC23) { break;
/* 0xC23 is M3 devices */ case CORTEX_M3_PARTNO: /* STM32F1x devices */
flash_size_reg = 0x1FFFF7E0; flash_size_reg = 0x1FFFF7E0;
} else if (((cpuid >> 4) & 0xFFF) == 0xC24) { break;
/* 0xC24 is M4 devices */ case CORTEX_M4_PARTNO: /* STM32F3x devices */
flash_size_reg = 0x1FFFF7CC; flash_size_reg = 0x1FFFF7CC;
} else { break;
default:
LOG_ERROR("Cannot identify target as a stm32x"); LOG_ERROR("Cannot identify target as a stm32x");
return ERROR_FAIL; return ERROR_FAIL;
} }
retval = target_read_u16(target, flash_size_reg, flash_size_in_kb); int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;

20
src/flash/nor/stm32f2x.c
View File

@ -29,7 +29,7 @@
#include "imp.h" #include "imp.h"
#include <helper/binarybuffer.h> #include <helper/binarybuffer.h>
#include <target/algorithm.h> #include <target/algorithm.h>
#include <target/armv7m.h> #include <target/cortex_m.h>
/* Regarding performance: /* Regarding performance:
* *
@ -968,25 +968,17 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
* Only effects Rev A silicon */ * Only effects Rev A silicon */
struct target *target = bank->target; struct target *target = bank->target;
uint32_t cpuid; struct cortex_m_common *cortex_m = target_to_cm(target);
/* read stm32 device id register */ /* read stm32 device id register */
int retval = target_read_u32(target, 0xE0042000, device_id); int retval = target_read_u32(target, 0xE0042000, device_id);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
if ((*device_id & 0xfff) == 0x411) { if ((*device_id & 0xfff) == 0x411 && cortex_m->core_info->partno == CORTEX_M4_PARTNO) {
/* read CPUID reg to check core type */ *device_id &= ~((0xFFFF << 16) | 0xfff);
retval = target_read_u32(target, 0xE000ED00, &cpuid); *device_id |= (0x1000 << 16) | 0x413;
if (retval != ERROR_OK) LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
return retval;
/* check for cortex_m4 */
if (((cpuid >> 4) & 0xFFF) == 0xC24) {
*device_id &= ~((0xFFFF << 16) | 0xfff);
*device_id |= (0x1000 << 16) | 0x413;
LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
}
} }
return retval; return retval;
} }