riscv: Regenerated debug_defines.h and encoding.h

The main intention is to get access to some of the CSRs
that were so far unknown to OpenOCD (tinfo, mcountinhibit, ...).

https://github.com/riscv/riscv-openocd/pull/659

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I824fdb558d5c1f73432b0f56f3b0b4d865eceeba
Reviewed-on: https://review.openocd.org/c/openocd/+/6682
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Jan Matyas 2021-11-04 17:48:23 +01:00 committed by Antonio Borneo
parent ee670f9dce
commit f8bd2566a9
2 changed files with 1705 additions and 165 deletions

View File

@ -1,6 +1,6 @@
/* /*
* This file is auto-generated by running 'make debug_defines.h' in * This file is auto-generated by running 'make debug_defines.h' in
* https://github.com/riscv/riscv-debug-spec/ (63c985f) * https://github.com/riscv/riscv-debug-spec/ (3dfe4f7)
* License: Creative Commons Attribution 4.0 International Public License (CC BY 4.0) * License: Creative Commons Attribution 4.0 International Public License (CC BY 4.0)
*/ */
@ -266,7 +266,7 @@
* *
* 1: An {\tt ebreak} instruction was executed. (priority 3) * 1: An {\tt ebreak} instruction was executed. (priority 3)
* *
* 2: The Trigger Module caused a breakpoint exception. (priority 4) * 2: A Trigger Module trigger fired with action=0. (priority 4)
* *
* 3: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq. * 3: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
* (priority 1) * (priority 1)
@ -461,7 +461,7 @@
* *
* \FcsrTcontrolMpte and \FcsrTcontrolMte provide one solution to a problem * \FcsrTcontrolMpte and \FcsrTcontrolMte provide one solution to a problem
* regarding triggers with action=0 firing in M-mode trap handlers. See * regarding triggers with action=0 firing in M-mode trap handlers. See
* Section~\ref{sec:mmtrigger} for more details. * Section~\ref{sec:nativetrigger} for more details.
* *
* When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of * When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of
* \FcsrTcontrolMte. * \FcsrTcontrolMte.
@ -811,8 +811,9 @@
#define CSR_MCONTROL6_VU_LENGTH 1 #define CSR_MCONTROL6_VU_LENGTH 1
#define CSR_MCONTROL6_VU (0x1ULL << CSR_MCONTROL6_VU_OFFSET) #define CSR_MCONTROL6_VU (0x1ULL << CSR_MCONTROL6_VU_OFFSET)
/* /*
* If this bit is implemented, the hardware sets it when this * If this bit is implemented then it must become set when this
* trigger matches. The trigger's user can set or clear it at any * trigger fires and may become set when this trigger matches.
* The trigger's user can set or clear it at any
* time. It is used to determine which * time. It is used to determine which
* trigger(s) matched. If the bit is not implemented, it is always 0 * trigger(s) matched. If the bit is not implemented, it is always 0
* and writing it has no effect. * and writing it has no effect.
@ -1237,7 +1238,8 @@
#define CSR_ETRIGGER_VU (0x1ULL << CSR_ETRIGGER_VU_OFFSET) #define CSR_ETRIGGER_VU (0x1ULL << CSR_ETRIGGER_VU_OFFSET)
/* /*
* When set, non-maskable interrupts cause this * When set, non-maskable interrupts cause this
* trigger to fire, regardless of the values of \FcsrEtriggerM, \FcsrEtriggerS, and \FcsrEtriggerU. * trigger to fire, regardless of the values of \FcsrEtriggerM,
* \FcsrEtriggerS, \FcsrEtriggerU, \FcsrEtriggerVs, and \FcsrEtriggerVu.
*/ */
#define CSR_ETRIGGER_NMI_OFFSET 10 #define CSR_ETRIGGER_NMI_OFFSET 10
#define CSR_ETRIGGER_NMI_LENGTH 1 #define CSR_ETRIGGER_NMI_LENGTH 1
@ -1361,10 +1363,15 @@
* 1: This trigger will only match if the low bits of * 1: This trigger will only match if the low bits of
* \RcsrScontext equal \FcsrTextraThirtytwoSvalue. * \RcsrScontext equal \FcsrTextraThirtytwoSvalue.
* *
* 2: This trigger will only match if the currently active ASID * 2: This trigger will only match if:
* value, from either \Rsatp or \Rvsatp, * \begin{itemize}[noitemsep,nolistsep]
* equals the lower ASIDMAX (defined in the Privileged Spec) bits of * \item the mode is VS-mode or VU-mode and ASID in \Rvsatp
* equals the lower ASIDMAX (defined in the Privileged Spec) bits
* of \FcsrTextraThirtytwoSvalue.
* \item in all other modes, ASID in \Rsatp equals the lower
* ASIDMAX (defined in the Privileged Spec) bits of
* \FcsrTextraThirtytwoSvalue. * \FcsrTextraThirtytwoSvalue.
* \end{itemize}
* *
* This field should be tied to 0 when S-mode is not supported. * This field should be tied to 0 when S-mode is not supported.
*/ */

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