Adds a flash driver for Nuvoton MINI51, MINI52 and MINI54 microcontrollers.
At the moment, it only supports the erase and write operations.
These microcontrollers have a 4 / 8 / 16 KB APROM for application code and a
2 KB LDROM for bootloaders. When the MCU has booted off the APROM, the LDROM
isn't mapped in memory but can be programmed, and the other way around.
This means that the ARM core is typically rebooted for programming. After a
successful write or erase operation, it is rebooted again, using the initial
boot source.
This driver only supports programming the APROM.
This driver is a pure JTAG implementation, it doesn't use any SRAM.
I've tested it on a MINI54ZAN microcontroller using an ST-LINK/V2. With the
microcontroller running at the default clock frequency of 22.1184 MHz, speed
seems to be around 1.1 KB/s.
Change-Id: I180889c55af9fb5614cd99a953b755baba14288a
Signed-off-by: Cosmin Gorgovan <cosmin@linux-geek.org>
Reviewed-on: http://openocd.zylin.com/1546
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This adds example config and flash driver for russian Cortex-M3
microcontroller model.
Run-time tested on MDR32F9Q2I evaluation board; the flash driver
should be compatible with MDR32F2x (Cortex-M0) too but I lack hardware
to test.
There're no status bits at all, the datasheets specifies some delays
for flash operations instead. All being in <100us range, they're hard
to violate with JTAG, I hope. There're also no flash identification
registers so the flash size and type has to be hardcoded into the
config.
The flashing is considerably complicated because the flash is split
into pages, and each page consists of 4 interleaved non-consecutive
"sectors" (on MDR32F9 only, MDR32F2 is single-sectored), so the
fastest way is to latch the page and sector address and then write
only the part that should go into the current page and current sector.
Performance testing results with adapter_khz 1000 and the chip running
on its default HSI 8MHz oscillator:
When working area is specified, a target helper algorithm is used:
wrote 131072 bytes from file testfile.bin in 3.698427s (34.609 KiB/s)
This can theoretically be sped up by ~1.4 times if the helper
algorithm is fed some kind of "loader instructions stream" to allow
sector-by-sector writing.
Pure JTAG implementation (when target memory area is not available)
flashes all the 128k memory in 49.5s.
Flashing "info" memory region is also implemented, but due to the
overlapping memory addresses (resulting in incorrect memory map
calculations for GDB) it can't be used at the same time, so OpenOCD
needs to be started this way: -c "set IMEMORY true" -f
target/mdr32f9q2i.cfg
It also can't be read/verified because it's not memory-mapped anywhere
ever, and OpenOCD NOR framework doesn't really allow to provide a
custom handler that would be used when verifying.
Change-Id: I80c0632da686d49856fdbf9e05d908846dd44316
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1532
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Limited (no page unprotect, no block writes) implementation of EFM32
flash support. Verified with EFM32 development kit and STLink V2 adapter
using SWD.
Change-Id: I3db2054d9aa628a1fe4814430425db3c9959c71c
Signed-off-by: Roman D <me@iamroman.org>
Reviewed-on: http://openocd.zylin.com/1106
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Added a flash driver designed to allow program/erase of
memory-mapped SPI flash chips for LPC43xx/LPC18xx family
micros. This driver includes three algorithms - erase,
write, and SPIFI peripheral initialization (to allow
memory-mapped access after a reset). The driver has been
added to the flash driver table (drivers.c), and the
OpenOCD documentation has been updated to include the flash
driver configuration command.
Change-Id: I79f4ff8f1f07de4e5f2fe4f8c23aeb903f868514
Signed-off-by: George Harris <george@luminairecoffee.com>
Reviewed-on: http://openocd.zylin.com/783
Tested-by: jenkins
Reviewed-by: Aurelien Jacobs <aurel@gnuage.org>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Atmel introduced 6 new Cortex-M4 processors on 2011-10-26
SAM4S16C - 1024KB flash LQFP100/BGA100
SAM4S16B - 1024KB flash LQFP64/QFN64
SAM4S16A - 1024KB flash LQFP48/QFN48
SAM4S8C - 512KB flash LQFP100/BGA100
SAM4S8B - 512KB flash LQFP64/QFN64
SAM4S8A - 512KB flash LQFP48/QFN48
The SAM4S processors still suffer from the "6 waitstates needed
to program device" errata.
Other relevant changes are:
1. Address of flash memory starts at 0x400000.
2. EWP (Erase page and write page) only works for the first two 8KB "sectors"
3. Because of the EWP not working for all the sectors, normal page writes have
to be used. The default_flash_blank_check is used to check if lockregions
should be erased.
4. The EA (Erase All) command takes 7.3s to complete. (Previous timeout was
500 ms)
5. There are 128 lockable regions of 8KB each.
Implemented default blank checking, and page erase for load_image scenarios.
This is to compensate for the EWP flash commands only working on the
first 2 8KB sectors.
Change-Id: I7c5a52b177f7849a107611fd0f635fc416cfb724
Signed-off-by: Olivier Schonken <olivier.schonken@gmail.com>
Reviewed-on: http://openocd.zylin.com/528
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
even the AT91EB40a's flash is covered by CFI and nobody ever submitted
any other drivers based on eCos code. It's just possible that this
idea was missing documentation and "marketing", but it's in git if
somebody wants to resurrect it.
Change-Id: I66449aa6e0997301f9d67f28098789bfc891d6e9
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Reviewed-on: http://openocd.zylin.com/502
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Use consistent names for the stm32 family flash drivers, eg.
stm32x -> stm32f1x
stm32f2xxx -> stm32f2x
this makes it easier to add support for newer stm32 families.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Use "git revert <commit>" to revert this commit, then build and
repair and post patch to the mailing list.
Warnings generated with:
nios2-elf-gcc (GCC) 3.4.6 (Altera Nios II 9.1 b222)
openocd/src/target/dsp5680xx.c: In function 'eonce_rx_upper_data':
openocd/src/target/dsp5680xx.c:252: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'eonce_rx_lower_data':
openocd/src/target/dsp5680xx.c:268: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'eonce_pc_store':
openocd/src/target/dsp5680xx.c:508: warning: dereferencing type-punned
pointer will break strict-aliasing rules
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_read':
openocd/src/target/dsp5680xx.c:736: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c:737: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write_8':
openocd/src/target/dsp5680xx.c:823: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_write':
openocd/src/target/dsp5680xx.c:938: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c:941: warning: cast increases required
alignment of target type
openocd/src/target/dsp5680xx.c: In function 'dsp5680xx_f_wr':
openocd/src/target/dsp5680xx.c:1355: warning: cast increases required
alignment of target type
Hi,
I took the stm32x NOR flash driver and adapted it for the Ember EM357
chip. This chip is very similar to em351 and stm32w so the driver
should be easily extended to support those as well if anyone can get
their hands on some of those for testing.
changelog:
Added NOR flash driver em357
Best regards,
Erik Botö
STMicroelectronics controller SMI is not SPEAr specific.
Rename it and change name to every symbol in the code.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Add support and documentation for STMicroelectronics
SPEAr Serial Memory Interface (SMI).
Code tested on SPEAr3xx only.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
This adds a virtual flash bank driver that allows virtual banks to
be defined that refer to an existing flash bank.
For example the real address for bank0 on the pic32 is 0x1fc00000
but the user program will either be in kseg0 (0xbfc00000) or
kseg1 (0x9fc00000).
This also means that gdb will be aware of all the read only flash
addresses.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Move the bulk of the flash.h file into flash/nor/core.h, leaving an
empty husk that will be removed in the next patch.
The NOR driver structure is an implementation detail, so move it into
its own private header file <flash/nor/driver.h> along with helper
declaration for finding them by name.
