the flash module clock was set according to a spreadsheet from freescale, now it's set according to the configuration file used by the Freescale Flash Programmer.
both work, but i think it's better to use the one used by a software that's made by Freescale (should be correct...)
Change-Id: I382197a3eb43dd47ff4b9b83d5e05008d5613fc6
Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/223
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
i had assumed two possible halt/debug states:
- halted + debug mode
- running + not debug mode
turns out this one also exists
- halted + NOT in debug mode
added code to handle this in an appropiate way.
Change-Id: Ia0ddcd55d1890c90d100a9e6f5e84ed8dda812a3
Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/220
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
moved reset_jtag to the top, since it will be needed in future changes.
also send a define to the .h
Change-Id: I53ef9c02ffa70e7d0416364525a6fbfef855e222
Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/216
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
added logging of target error codes to enable automatic error handling from tcl.
the plan is to use a computer to execute a series of tcl commands, the changes allow simple parsing of return messages to detect errors.
Change-Id: Ia98d3bd036e1b6065b475ffff6c1d30baeaf7417
Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/215
Tested-by: jenkins
Tested-by: Øyvind Harboe <oyvindharboe@gmail.com>
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
crc check was always performed on newly flashed data, now it is optional
flash mem can be locked by writing a specific word to a specific address in flash.
to verify flash, target must be halted, and this will (when the new halt sequence is implemented) require reseting the chip. if the target is reset after writing the lock words, then it will lock, hence the CRC will fail because it is not possible to read stuff from the target.
also added a function that resets the jtag state machine.
this is not used yet, but will be soon.
it is implemented to allow strict control over JTAG state machine, necessary to implement to halt and unlocking sequences.
