Robert Jarzmik 9188a9bc68 target: xscale make reset init work properly ... On XScale architecture, to write debug control register DCSR and activate JTAG debug (ie. to choose Halt Mode), the enabling can only be done while the board is held in reset state (ie. PXAxx #RST line held low). The current implementation writes to the register before asserting the SRST line. Swap the order to activate the SRST line before writing to DCSR. Change-Id: I914b9d53d39bdeb5fe4ee5e11068cafafe0da4d2 Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Reviewed-on: http://openocd.zylin.com/1458 Tested-by: jenkins Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>		2013-07-01 08:49:11 +00:00
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flash	at91sam3: Added support for at91sam3s8a, b and c	2013-07-01 08:40:21 +00:00
helper	Add support for 64 bit parameter to irscan	2013-07-01 08:37:14 +00:00
jtag	Allow autoscan up to 64 bit IR lengths	2013-07-01 08:37:27 +00:00
pld	update files to correct FSF address	2013-06-05 19:52:42 +00:00
rtos	keep gdb aware of threads if RTOS is set but no threads are created	2013-07-01 08:38:32 +00:00
server	update files to correct FSF address	2013-06-05 19:52:42 +00:00
svf	update files to correct FSF address	2013-06-05 19:52:42 +00:00
target	target: xscale make reset init work properly	2013-07-01 08:49:11 +00:00
transport	update files to correct FSF address	2013-06-05 19:52:42 +00:00
xsvf	update files to correct FSF address	2013-06-05 19:52:42 +00:00
Makefile.am	drivers/jtag: rewrite usb_blaster driver	2013-06-04 20:00:42 +00:00
hello.c	update files to correct FSF address	2013-06-05 19:52:42 +00:00
hello.h	update files to correct FSF address	2013-06-05 19:52:42 +00:00
main.c	update files to correct FSF address	2013-06-05 19:52:42 +00:00
openocd.c	update files to correct FSF address	2013-06-05 19:52:42 +00:00
openocd.h	update files to correct FSF address	2013-06-05 19:52:42 +00:00