188 lines
6.4 KiB
INI
188 lines
6.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32f7x family
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#
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# stm32f7 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32f7x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 128kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x20000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0385
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# Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
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set _CPUTAPID 0x5ba00477
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} {
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set _CPUTAPID 0x5ba02477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME
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# On the STM32F7, the Flash is mapped at address 0x08000000 via the AXI and
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# also address 0x00200000 via the ITCM. The former mapping is read-write in
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# hardware, while the latter is read-only. By presenting an alias, we
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# accomplish two things:
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# (1) We allow writing at 0x00200000 (because the alias acts identically to the
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# original bank), which allows code intended to run from that address to
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# also be linked for loading at that address, simplifying linking.
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# (2) We allow the proper memory map to be delivered to GDB, which will cause
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# it to use hardware breakpoints at the 0x00200000 mapping (correctly
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# identifying it as Flash), which it would otherwise not do. Configuring
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# the Flash via ITCM alias as virtual
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flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
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if { [info exists QUADSPI] && $QUADSPI } {
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set a [llength [flash list]]
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set _QSPINAME $_CHIPNAME.qspi
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flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
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}
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# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
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adapter speed 2000
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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# Use hardware reset.
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#
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# This target is compatible with connect_assert_srst, which may be set in a
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# board file.
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
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# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
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# makes the data access cacheable. This allows reading and writing data in the
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# CPU cache from the debugger, which is far more useful than going straight to
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# RAM when operating on typical variables, and is generally no worse when
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# operating on special memory locations.
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$_CHIPNAME.dap apcsw 0x08000000 0x08000000
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}
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$_TARGETNAME configure -event examine-end {
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0042008 0x00001800 0
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}
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
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lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
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proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
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targets $_targetname
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0042004 0x00000020 0
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}
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$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
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$_TARGETNAME configure -event reset-init {
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# If the HSE was previously enabled and the external clock source
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# disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
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# properly switched back to HSI. This situation persists even over a system
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# reset, including a pin reset via SRST. However, activating the clock
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# security system will detect the problem and clear HSERDY to 0, which in
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# turn allows the PLL to switch back to HSI properly. Since we just came
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# out of reset, HSEON should be 0. If HSERDY is 1, then this situation must
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# have happened; in that case, activate the clock security system to clear
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# HSERDY.
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if {[mrw 0x40023800] & 0x00020000} {
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mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON
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sleep 10 ;# Wait for CSS to fire, if it wants to
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mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON
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mww 0x4002380C 0x00800000 ;# RCC_CIR = CSSC
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sleep 1 ;# Wait for CSSF to clear
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}
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# If the clock security system fired, it will pend an NMI. A pending NMI
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# will cause a bad time for any subsequent executing code, such as a
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# programming algorithm.
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if {[mrw 0xE000ED04] & 0x80000000} {
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# ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be
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# cleared by any normal means (such as ICSR or NVIC). It can only be
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# cleared by entering the NMI handler or by resetting the processor.
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echo "[target current]: Clock security system generated NMI. Clearing."
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# Keep the old DEMCR value.
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set old [mrw 0xE000EDFC]
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# Enable vector catch on reset.
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mww 0xE000EDFC 0x01000001
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# Issue local reset via AIRCR.
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mww 0xE000ED0C 0x05FA0001
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# Restore old DEMCR value.
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mww 0xE000EDFC $old
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}
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# Configure PLL to boost clock to HSI x 10 (160 MHz)
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mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
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mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency)
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mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
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sleep 10 ;# Wait for PLL to lock
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mww 0x40023808 0x00009400 ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
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mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
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# Boost SWD frequency
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# Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
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# suffers from DAP WAITs
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if {[using_jtag]} {
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[[target current] cget -dap] memaccess 16
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} {
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adapter speed 8000
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}
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}
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$_TARGETNAME configure -event reset-start {
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# Reduce speed since CPU speed will slow down to 16MHz with the reset
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adapter speed 2000
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}
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