c008d30fe8
This implements the DPM interface for Cortex-A8 cores. It also adds a synchronization operation to the DPM framework, which is needed by the Cortex-A8 after CPSR writes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
91 lines
2.9 KiB
C
91 lines
2.9 KiB
C
/*
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* Copyright (C) 2009 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef __ARM_DPM_H
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#define __ARM_DPM_H
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/**
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* @file
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* This is the interface to the Debug Programmers Model for ARMv6 and
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* ARMv7 processors. ARMv6 processors (such as ARM11xx implementations)
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* introduced a model which became part of the ARMv7-AR architecture
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* which is most familiar through the Cortex-A series parts. While
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* specific details differ (like how to write the instruction register),
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* the high level models easily support shared code because those
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* registers are compatible.
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*/
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/**
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* This wraps an implementation of DPM primitives. Each interface
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* provider supplies a structure like this, which is the glue between
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* upper level code and the lower level hardware access.
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*
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* It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with
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* support for CPU register access.
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*/
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struct arm_dpm {
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struct arm *arm;
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/** Cache of DIDR */
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uint32_t didr;
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/** Invoke before a series of instruction operations */
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int (*prepare)(struct arm_dpm *);
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/** Invoke after a series of instruction operations */
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int (*finish)(struct arm_dpm *);
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/* WRITE TO CPU */
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/** Runs one instruction, writing data to DCC before execution. */
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int (*instr_write_data_dcc)(struct arm_dpm *,
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uint32_t opcode, uint32_t data);
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/** Runs one instruction, writing data to R0 before execution. */
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int (*instr_write_data_r0)(struct arm_dpm *,
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uint32_t opcode, uint32_t data);
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/** Optional core-specific operation invoked after CPSR writes. */
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int (*instr_cpsr_sync)(struct arm_dpm *dpm);
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/* READ FROM CPU */
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/** Runs one instruction, reading data from dcc after execution. */
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int (*instr_read_data_dcc)(struct arm_dpm *,
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uint32_t opcode, uint32_t *data);
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/** Runs one instruction, reading data from r0 after execution. */
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int (*instr_read_data_r0)(struct arm_dpm *,
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uint32_t opcode, uint32_t *data);
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// FIXME -- add breakpoint support
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// FIXME -- add watchpoint support (including context-sensitive ones)
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// FIXME -- read/write DCSR methods and symbols
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};
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int arm_dpm_setup(struct arm_dpm *dpm);
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int arm_dpm_reinitialize(struct arm_dpm *dpm);
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int arm_dpm_read_current_registers(struct arm_dpm *);
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int arm_dpm_write_dirty_registers(struct arm_dpm *);
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#endif /* __ARM_DPM_H */
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